diff options
93 files changed, 754 insertions, 5889 deletions
@@ -2,4 +2,3 @@ *.wdb *.exe *.un~ -*.prj @@ -30,7 +30,7 @@ reg [2:0] i = 0; reg [19:0] work; -always @ ( hun, ten, one ) begin +always @ ( hun, ten, one, bin ) begin work = {hun, ten, one, bin}; @@ -39,13 +39,13 @@ always @ ( hun, ten, one ) begin for (i = 0; i < 7; i = i + 1) begin work = work >> 1; if (work[19:16] >= 5) begin - work[19:16] = work[19:16] - 3; + work[19:16] = work[19:16] - 4'd3; end if (work[15:12] >= 5) begin - work[15:12] = work[15:12] - 3; + work[15:12] = work[15:12] - 4'd3; end if (work[11:8] >= 5) begin - work [11:8] = work[11:8] - 3; + work [11:8] = work[11:8] - 4'd3; end end @@ -36,13 +36,13 @@ always @( bin ) begin for (i = 0; i < 7; i = i +1) begin work = work << 1; if (work[19:16] >= 5) begin - work[19:16] = work[19:16] + 3; + work[19:16] = work[19:16] + 4'd3; end if (work[15:12] >= 5) begin - work[15:12] = work[15:12] + 3; + work[15:12] = work[15:12] + 4'd3; end if (work[11:8] >= 5) begin - work[11:8] = work[11:8] + 3; + work[11:8] = work[11:8] + 4'd3; end end diff --git a/ClockDivider.v b/ClockDivider.v index 2447e7e..7ced5a7 100644 --- a/ClockDivider.v +++ b/ClockDivider.v @@ -36,7 +36,7 @@ always @(posedge clk_in or posedge rst) begin clk_out = ~clk_out; c = 0; end else begin - c = c + 1; + c = c + 24'd1; end diff --git a/Countdown.v b/Countdown.v index 78e4162..a8c7506 100644 --- a/Countdown.v +++ b/Countdown.v @@ -23,35 +23,43 @@ module Countdown( input rst, input start, input [7:0] init, - output [7:0] t + output [7:0] t,
+ output running ); reg [7:0] t; -reg running = 0; +reg running = 0;
+reg [7:0] count;
+
+always @(posedge clk_1hz or posedge rst) begin
+ if (rst)
+ count <= 0;
+ else if (running)
+ count <= count + 1;
+ else
+ count <= 0;
+end
-always @(init) begin - if (!running) begin - t = init; - end else begin - t = t; - end -end - -always @(posedge clk_1hz) begin - if (running) begin - t <= t - 1; - end else begin - t <= init; - end -end +always @(posedge clk_1hz or posedge rst) begin
+
+ if (rst)
+ t <= 0;
+ else //if (running)
+ t <= init - count;
-always @(posedge start) begin - running = 1; end -always @(rst) begin - running = 0; - t = 0; +always @(posedge start or posedge rst) begin
+
+ if (rst)
+ running <= 0;
+ else if (count == init) begin
+ running <= 0;
+ end else if (start)
+ running <= 1;
+ else
+ running <= running;
+ end endmodule diff --git a/CountdownController.v b/CountdownController.v index 35c84f9..626eef3 100644 --- a/CountdownController.v +++ b/CountdownController.v @@ -31,16 +31,20 @@ module CountdownController( reg [6:0] ssd; reg [3:0] AN; -wire [6:0] ssdo; -wire [3:0] ANo; +wire [6:0] ssd1;
+wire [6:0] ssd2; +wire [3:0] AN1;
+wire [3:0] AN2; // clocks wire seconds; wire dbclk; -wire dispclk; +wire dispclk;
+
+wire running; // buttons -wire a, b; +wire a, b, c; // bcd things wire [3:0] ad, bd; @@ -50,34 +54,36 @@ wire [3:0] ado, bdo, cdo; wire [7:0] init; wire [7:0] tout; -//ClockDivider dbc(.count(1_000_000), .rst(rst), .clk_in(clk), .clk_out(dbclk)); -//ClockDivider sec(.count(100_000_000), .rst(rst), .clk_in(clk), .clk_out(seconds)); -//ClockDivider dcc(.count(7_500_000), .rst(rst), .clk_in(clk), .clk_out(dispclk)); +ClockDivider dbc(.count(100), .rst(rst), .clk_in(clk), .clk_out(dbclk)); +ClockDivider sec(.count(100_000_000), .rst(rst), .clk_in(clk), .clk_out(seconds)); +ClockDivider dcc(.count(7_500_0), .rst(rst), .clk_in(clk), .clk_out(dispclk)); -ClockDivider dbc(.count(10), .rst(rst), .clk_in(clk), .clk_out(dbclk)); -ClockDivider sec(.count(100), .rst(rst), .clk_in(clk), .clk_out(seconds)); -ClockDivider dcc(.count(25), .rst(rst), .clk_in(clk), .clk_out(dispclk)); +//ClockDivider dbc(.count(24'd10), .rst(rst), .clk_in(clk), .clk_out(dbclk)); +//ClockDivider sec(.count(24'd100), .rst(rst), .clk_in(clk), .clk_out(seconds)); +//ClockDivider dcc(.count(24'd25), .rst(rst), .clk_in(clk), .clk_out(dispclk)); debouncer dbA(.dout(a), .din(btnA), .rst(rst), .clk_1M(dbclk)); debouncer dbB(.dout(b), .din(btnB), .rst(rst), .clk_1M(dbclk)); +debouncer dbC(.dout(c), .din(btnC), .rst(rst), .clk_1M(dbclk));
-Increment inc1(.value(ad), .btn(a)); -Increment inc2(.value(bd), .btn(b)); +Increment inc1(.value(ad), .btn(a), .rst(rst)); +Increment inc2(.value(bd), .btn(b), .rst(rst)); -//Increment inc1(.value(ad), .btn(btnA)); +//Increment inc1(.value(ad), .btn(btnA));
//Increment inc2(.value(bd), .btn(btnB)); -BCD2Bin bcd2b(.hun(0), .ten(ad), .one(bd), .bin(init)); +BCD2Bin bcd2b(.hun(4'd0), .ten(ad), .one(bd), .bin(init)); -Countdown cntdwn(.t(tout), .rst(rst), .init(init), .clk_1hz(seconds), .start(btnC)); +Countdown cntdwn(.t(tout), .running(running), .rst(rst), .init(init), .clk_1hz(seconds), .start(c)); Bin2BCD b2bcb(.hun(cdo), .ten(ado), .one(bdo), .bin(tout)); -DisplayController dispcont(.result(ssdo), .AN(ANo), .A(ado), .B(bdo), .clk_in(dispclk), .rst(rst)); - - -assign ssd = ssdo; -assign AN = ANo; +DisplayController dispcont1(.result(ssd1), .AN(AN1), .A(ado), .B(bdo), .clk_in(dispclk), .rst(rst)); +DisplayController dispcont2(.result(ssd2), .AN(AN2), .A(ad), .B(bd), .clk_in(dispclk), .rst(rst)); +always @(posedge clk) begin + ssd <= running ? ssd1 : ssd2; + AN <= running ? AN1 : AN2; +end
endmodule diff --git a/CountdownController_summary.html b/CountdownController_summary.html index b9ce724..d2dc1c9 100644 --- a/CountdownController_summary.html +++ b/CountdownController_summary.html @@ -22,7 +22,7 @@ <TD> </TD> </TR> <TR ALIGN=LEFT> -<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 13.4</TD> +<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 13.3</TD> <TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD> <TD> </TD> </TR> @@ -72,9 +72,9 @@ <BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'> <TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR> <TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR> -<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/michael/Documents/School/EC311/lab4/isim.log'>ISIM Simulator Log</A></TD><TD>Current</TD><TD COLSPAN='2'>Wed Mar 21 13:14:04 2012</TD></TR> +<TR ALIGN=LEFT><TD><A HREF_DISABLED='X:/My Documents/ec311/ec311-lab4\isim.log'>ISIM Simulator Log</A></TD><TD>Current</TD><TD COLSPAN='2'>Wed Mar 21 13:22:33 2012</TD></TR> </TABLE> -<br><center><b>Date Generated:</b> 03/21/2012 - 13:43:14</center> +<br><center><b>Date Generated:</b> 03/21/2012 - 17:32:54</center> </BODY></HTML>
\ No newline at end of file diff --git a/DisplayController.v b/DisplayController.v index 1ea2bf1..108d7a9 100644 --- a/DisplayController.v +++ b/DisplayController.v @@ -35,13 +35,13 @@ wire [6:0] ssd2; reg prev = 0; -SevSegDisp d1(.A(A), .out(ssd1)); -SevSegDisp d2(.A(B), .out(ssd2)); +SevSegDisp d1(.A(A), .result(ssd1)); +SevSegDisp d2(.A(B), .result(ssd2)); always @( posedge clk_in ) begin prev <= ~prev; result <= prev ? ssd1 : ssd2; - AN <= { 2'b11, prev, ~prev }; + AN <= { 2'b11, ~prev, prev }; end diff --git a/Increment.v b/Increment.v index b386d13..105a557 100644 --- a/Increment.v +++ b/Increment.v @@ -19,14 +19,18 @@ // ////////////////////////////////////////////////////////////////////////////////// module Increment( - input btn, + input btn,
+ input rst, output [3:0] value ); reg [3:0] value = 0; -always @ ( posedge btn ) begin - value = value == 9 ? 0 : value + 1; +always @ ( posedge btn or posedge rst) begin
+ if (rst)
+ value <= 0;
+ else + value <= value == 4'd9 ? 4'd0 : value + 4'd1; end endmodule diff --git a/SevSegDisp.v b/SevSegDisp.v index f0b6ee9..8d2c3b1 100644 --- a/SevSegDisp.v +++ b/SevSegDisp.v @@ -21,24 +21,24 @@ module SevSegDisp( input [3:0] A, - output [6:0] out + output [6:0] result ); -reg [6:0] out = 0; +reg [6:0] result = 0; always @ ( * ) begin case ( A ) - 4'b0000 : out = 7'b0000001; - 4'b0001 : out = 7'b1001111; - 4'b0010 : out = 7'b0010010; |