`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    14:51:02 03/16/2012 
// Design Name: 
// Module Name:    Countdown 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module Countdown(
    input clk_1hz,
    input rst,
    input start,
    input [7:0] init,
    output [7:0] t,
	 output running
    );

reg [7:0] t;
reg running = 0;
reg [7:0] count;

always @(posedge clk_1hz or posedge rst) begin
	if (rst)
		count <= 0;
	else if (running)
		count <= count + 1;
	else
		count <= 0;
end

always @(posedge clk_1hz or posedge rst) begin

	if (rst)
		t <= 0;
	else //if (running)
		t <= init - count;

end

always @(posedge start or posedge rst) begin
	
	if (rst)
		running <= 0;
	else if (count == init) begin
		running <= 0;
	end else if (start)
		running <= 1;
	else
		running <= running;
	
end

endmodule