`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   14:24:49 03/16/2012
// Design Name:   Increment
// Module Name:   /home/michael/Documents/School/EC311/lab4/TEST_Increment.v
// Project Name:  lab4
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: Increment
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module TEST_Increment;

	// Inputs
	reg btn;
	reg rst;

	// Outputs
	wire [3	:0] value;
	
	// count
	reg [4:0] i;
	
	
	// Instantiate the Unit Under Test (UUT)
	Increment uut (
		.btn(btn),
		.rst(rst),
		.value(value)
	);

	initial begin
		// Initialize Inputs
		btn = 0;

		// Wait 100 ns for global reset to finish
		#100;
		
		for (i = 0; i < 20; i = i + 1) begin
		    btn = 1; #10;
			 btn = 0; #10;
		end
		
      #100;
		// Add stimulus here

	end
      
endmodule