`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   15:26:38 03/29/2012
// Design Name:   Bin2BCD
// Module Name:   /home/michael/Documents/School/EC311/lab5/TEST_Bin2BCD.v
// Project Name:  lab5
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: Bin2BCD
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module TEST_Bin2BCD;

	// Inputs
	reg [15:0] bin;

	// Outputs
	wire [3:0] one;
	wire [3:0] ten;
	wire [3:0] hun;
	wire [3:0] thous;

	// Instantiate the Unit Under Test (UUT)
	Bin2BCD uut (
		.bin(bin), 
		.one(one), 
		.ten(ten), 
		.hun(hun), 
		.thous(thous)
	);

	initial begin
		// Initialize Inputs
		bin = 0;

		// Wait 100 ns for global reset to finish
		#100;
      bin = 7; #50;
		bin = 16;#50;
		bin = 217;#50;
		bin = 1839; #50;
		// Add stimulus here

	end
      
endmodule