`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   13:25:07 10/05/2012
// Design Name:   slt
// Module Name:   /ad/eng/users/m/g/mgabed/Documents/ec413/mgabed-lab4/test_slt.v
// Project Name:  mgabed-lab4
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: slt
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module test_slt;

	// Inputs
	reg r2;
	reg r3;
	reg signres;
	reg carryres;

	// Outputs
	wire out;

	// Instantiate the Unit Under Test (UUT)
	slt uut (
		.out(out), 
		.r2(r2), 
		.r3(r3), 
		.signres(signres), 
		.carryres(carryres)
	);

	initial begin
		// Initialize Inputs
		r2 = 0;
		r3 = 0;
		signres = 0;
		carryres = 0;

		// Wait 100 ns for global reset to finish
		#100;
        
		// Add stimulus here
		signres = 1; carryres = 1; r2 = 1; r3 = 1; #5;
		signres = 1; carryres = 1; r2 = 1; r3 = 0; #5;
		signres = 1; carryres = 1; r2 = 0; r3 = 1; #5;
		signres = 1; carryres = 1; r2 = 0; r3 = 0; #5;
		signres = 1; carryres = 0; r2 = 1; r3 = 1; #5;
		signres = 1; carryres = 0; r2 = 1; r3 = 0; #5;
		signres = 1; carryres = 0; r2 = 0; r3 = 1; #5;
		signres = 1; carryres = 0; r2 = 0; r3 = 0; #5;
		signres = 0; carryres = 1; r2 = 1; r3 = 1; #5;
		signres = 0; carryres = 1; r2 = 1; r3 = 0; #5;
		signres = 0; carryres = 1; r2 = 0; r3 = 1; #5;
		signres = 0; carryres = 1; r2 = 0; r3 = 0; #5;
		signres = 0; carryres = 0; r2 = 1; r3 = 1; #5;
		signres = 0; carryres = 0; r2 = 1; r3 = 0; #5;
		signres = 0; carryres = 0; r2 = 0; r3 = 1; #5;
		signres = 0; carryres = 0; r2 = 0; r3 = 0; #5;

	end
      
endmodule