1 files changed, 46 insertions, 66 deletions
diff --git a/planAhead_run_1/planAhead_run.log b/planAhead_run_1/planAhead_run.log
index bae2bd8..9d4c5fa 100755
--- a/planAhead_run_1/planAhead_run.log
+++ b/planAhead_run_1/planAhead_run.log
@@ -9,72 +9,38 @@ INFO: [Device-25] Loading parts and site information from C:/Xilinx/13.3/ISE_DS/
 Finished parsing RTL primitives file [C:/Xilinx/13.3/ISE_DS/PlanAhead\parts\xilinx\rtl\prims\rtl_prims.xml]
 start_gui
 starting gui ...
-source {X:/My Documents/ec311/lab1/pa.fromHdl.tcl}
-# create_project -name lab1 -dir "X:/My Documents/ec311/lab1/planAhead_run_1" -part xc6slx16csg324-3
+source {X:/My Documents/ec311/ec311-lab1/pa.fromNetlist.tcl}
+# create_project -name lab1 -dir "X:/My Documents/ec311/ec311-lab1/planAhead_run_1" -part xc6slx16csg324-3
 Parsing template File [C:/Xilinx/13.3/ISE_DS/ISE\data\projnav\templates\verilog.xml].
 Finished parsing template File [C:/Xilinx/13.3/ISE_DS/ISE\data\projnav\templates\verilog.xml].
 Parsing template File [C:/Xilinx/13.3/ISE_DS/ISE\data\projnav\templates\vhdl.xml].
 Finished parsing template File [C:/Xilinx/13.3/ISE_DS/ISE\data\projnav\templates\vhdl.xml].
 Parsing template File [C:/Xilinx/13.3/ISE_DS/ISE\data\projnav\templates\ucf.xml].
 Finished parsing template File [C:/Xilinx/13.3/ISE_DS/ISE\data\projnav\templates\ucf.xml].
-# set_param project.pinAheadLayout yes
-# set srcset [get_property srcset [current_run -impl]]
-# set_property top ALU $srcset
+# set_property design_mode GateLvl [get_property srcset [current_run -impl]]
+# set_property edif_top_file "X:/My Documents/ec311/ec311-lab1/ALU.ngc" [ get_property srcset [ current_run ] ]
+# add_files -norecurse { {X:/My Documents/ec311/ec311-lab1} }
+# set_param project.pinAheadLayout  yes
 # set_property target_constrs_file "ALU.ucf" [current_fileset -constrset]
-Adding file 'X:\My Documents\ec311\lab1\ALU.ucf' to fileset 'constrs_1'
-# set hdlfile [add_files [list {Negate_3.vf}]]
-# set_property file_type Verilog $hdlfile
-# set_property library work $hdlfile
-# set hdlfile [add_files [list {Negate_2.vf}]]
-# set_property file_type Verilog $hdlfile
-# set_property library work $hdlfile
-# set hdlfile [add_files [list {Negate_1.vf}]]
-# set_property file_type Verilog $hdlfile
-# set_property library work $hdlfile
-# set hdlfile [add_files [list {Negate_0.vf}]]
-# set_property file_type Verilog $hdlfile
-# set_property library work $hdlfile
-# set hdlfile [add_files [list {Modulo_3.vf}]]
-# set_property file_type Verilog $hdlfile
-# set_property library work $hdlfile
-# set hdlfile [add_files [list {Modulo_1.vf}]]
-# set_property file_type Verilog $hdlfile
-# set_property library work $hdlfile
-# set hdlfile [add_files [list {Modulo_0.vf}]]
-# set_property file_type Verilog $hdlfile
-# set_property library work $hdlfile
-# set hdlfile [add_files [list {Divide_3.vf}]]
-# set_property file_type Verilog $hdlfile
-# set_property library work $hdlfile
-# set hdlfile [add_files [list {Divide_2.vf}]]
-# set_property file_type Verilog $hdlfile
-# set_property library work $hdlfile
-# set hdlfile [add_files [list {Divide_1.vf}]]
-# set_property file_type Verilog $hdlfile
-# set_property library work $hdlfile
-# set hdlfile [add_files [list {Divide_0.vf}]]
-# set_property file_type Verilog $hdlfile
-# set_property library work $hdlfile
-# set hdlfile [add_files [list {sev_seg_disp.vf}]]
-# set_property file_type Verilog $hdlfile
-# set_property library work $hdlfile
-# set hdlfile [add_files [list {Negate.vf}]]
-# set_property file_type Verilog $hdlfile
-# set_property library work $hdlfile
-# set hdlfile [add_files [list {Modulo.vf}]]
-# set_property file_type Verilog $hdlfile
-# set_property library work $hdlfile
-# set hdlfile [add_files [list {Divide.vf}]]
-# set_property file_type Verilog $hdlfile
-# set_property library work $hdlfile
-# set hdlfile [add_files [list {ALU.vf}]]
-# set_property file_type Verilog $hdlfile
-# set_property library work $hdlfile
+Adding file 'X:\My Documents\ec311\ec311-lab1\ALU.ucf' to fileset 'constrs_1'
 # add_files [list {ALU.ucf}] -fileset [get_property constrset [current_run]]
-# open_rtl_design -part xc6slx16csg324-3
-INFO: [PlanAhead-58] Using Verific elaboration
-Parsing VHDL file "C:/Xilinx/13.3/ISE_DS/PlanAhead\parts\xilinx\rtl\lib\synplify\synattr.vhd" into library synplify
-Analyzing Verilog file "X:\My Documents\ec311\lab1\Negate.vf" into library work
+# open_netlist_design
+Design is defaulting to srcset: sources_1
+Design is defaulting to constrset: constrs_1
+Design is defaulting to part: xc6slx16csg324-3
+Release 13.3 - ngc2edif O.76xd (nt64)
+Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved.
+Reading design ALU.ngc ...
+WARNING:NetListWriters:298 - No output is written to ALU.xncf, ignored.
+Processing design ...
+   Preping design's networks ...
+   Preping design's macros ...
+  finished :Prep
+Writing EDIF netlist file ALU.edif ...
+ngc2edif: Total memory usage is 91624 kilobytes
+
+Parsing EDIF File [.\planAhead_run_1\lab1.data\cache\ALU_ngc_c04f956c.edif]
+Finished Parsing EDIF File [.\planAhead_run_1\lab1.data\cache\ALU_ngc_c04f956c.edif]
 Loading clock regions from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts/xilinx/spartan6/spartan6lx/xc6slx16/ClockRegion.xml
 Loading clock buffers from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts/xilinx/spartan6/spartan6lx/xc6slx16/ClockBuffers.xml
 Loading package pin functions from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts\xilinx\spartan6/PinFunctions.xml...
@@ -82,12 +48,26 @@ Loading package from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts/xilinx/spartan6/spart
 Loading io standards from C:/Xilinx/13.3/ISE_DS/PlanAhead\./parts/xilinx/spartan6/IOStandards.xml
 Loading device configuration modes from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts\xilinx\spartan6/ConfigModes.xml
 Loading list of drcs for the architecture : C:/Xilinx/13.3/ISE_DS/PlanAhead\./parts/xilinx/spartan6/drc.xml
-Parsing UCF File [X:\My Documents\ec311\lab1\ALU.ucf]
-Finished Parsing UCF File [X:\My Documents\ec311\lab1\ALU.ucf]
-INFO: [Designutils-20] Invalid constraints found, use command 'write_ucf -constraints invalid <file>' to save all the invalid constraints to a file
+Parsing UCF File [X:\My Documents\ec311\ec311-lab1\ALU.ucf]
+Finished Parsing UCF File [X:\My Documents\ec311\ec311-lab1\ALU.ucf]
 INFO: [PlanAhead-566] Unisim Transformation Summary:
-No Unisim elements were transformed.open_rtl_design: Time (s): 13.288w.  Memory (MB): 788.289p 223.703g
-exit
-stop_gui
-INFO: [PlanAhead-261] Exiting PlanAhead...
-INFO: [Common-83] Releasing license: PlanAhead
+No Unisim elements were transformed.open_netlist_design: Time (s): 13.291w.  Memory (MB): 734.672p 186.648g
+startgroup
+startgroup
+set_property loc PAD2 [get_ports A]
+set_property loc PAD2 [get_ports A]
+endgroup
+endgroup
+startgroup
+startgroup
+set_property loc PAD30 [get_ports D]
+set_property loc PAD30 [get_ports D]
+endgroup
+endgroup
+startgroup
+startgroup
+set_property loc PAD29 [get_ports C]
+set_property loc PAD29 [get_ports C]
+endgroup
+endgroup
+save_design