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-rwxr-xr-xplanAhead_run_2/lab1.data/cache/ALU_ngc_c04f956c.edif2476
-rwxr-xr-xplanAhead_run_2/lab1.data/constrs_1/fileset.xml25
-rwxr-xr-xplanAhead_run_2/lab1.data/runs/impl_1.psg18
-rwxr-xr-xplanAhead_run_2/lab1.data/runs/runs.xml5
-rwxr-xr-xplanAhead_run_2/lab1.data/sources_1/fileset.xml29
-rwxr-xr-xplanAhead_run_2/lab1.data/wt/webtalk_pa.xml26
-rwxr-xr-xplanAhead_run_2/lab1.ppr14
-rwxr-xr-xplanAhead_run_2/planAhead.jou18
-rwxr-xr-xplanAhead_run_2/planAhead.log198
-rwxr-xr-xplanAhead_run_2/planAhead_run.log196
10 files changed, 3005 insertions, 0 deletions
diff --git a/planAhead_run_2/lab1.data/cache/ALU_ngc_c04f956c.edif b/planAhead_run_2/lab1.data/cache/ALU_ngc_c04f956c.edif
new file mode 100755
index 0000000..b8c1e02
--- /dev/null
+++ b/planAhead_run_2/lab1.data/cache/ALU_ngc_c04f956c.edif
@@ -0,0 +1,2476 @@
+(edif ALU
+ (edifVersion 2 0 0)
+ (edifLevel 0)
+ (keywordMap (keywordLevel 0))
+ (status
+ (written
+ (timestamp 2012 2 16 19 53 2)
+ (program "Xilinx ngc2edif" (version "O.76xd"))
+ (author "Xilinx. Inc ")
+ (comment "This EDIF netlist is to be used within supported synthesis tools")
+ (comment "for determining resource/timing estimates of the design component")
+ (comment "represented by this netlist.")
+ (comment "Command line: -mdp2sp -w -secure ALU.ngc ALU.edif ")))
+ (external UNISIMS
+ (edifLevel 0)
+ (technology (numberDefinition))
+ (cell GND
+ (cellType GENERIC)
+ (view view_1
+ (viewType NETLIST)
+ (interface
+ (port G
+ (direction OUTPUT)
+ )
+ )
+ )
+ )
+ (cell VCC
+ (cellType GENERIC)
+ (view view_1
+ (viewType NETLIST)
+ (interface
+ (port P
+ (direction OUTPUT)
+ )
+ )
+ )
+ )
+ (cell OR3
+ (cellType GENERIC)
+ (view view_1
+ (viewType NETLIST)
+ (interface
+ (port I0
+ (direction INPUT)
+ )
+ (port I1
+ (direction INPUT)
+ )
+ (port I2
+ (direction INPUT)
+ )
+ (port O
+ (direction OUTPUT)
+ )
+ )
+ )
+ )
+ (cell OR2
+ (cellType GENERIC)
+ (view view_1
+ (viewType NETLIST)
+ (interface
+ (port I0
+ (direction INPUT)
+ )
+ (port I1
+ (direction INPUT)
+ )
+ (port O
+ (direction OUTPUT)
+ )
+ )
+ )
+ )
+ (cell INV
+ (cellType GENERIC)
+ (view view_1
+ (viewType NETLIST)
+ (interface
+ (port I
+ (direction INPUT)
+ )
+ (port O
+ (direction OUTPUT)
+ )
+ )
+ )
+ )
+ (cell AND2
+ (cellType GENERIC)
+ (view view_1
+ (viewType NETLIST)
+ (interface
+ (port I0
+ (direction INPUT)
+ )
+ (port I1
+ (direction INPUT)
+ )
+ (port O
+ (direction OUTPUT)
+ )
+ )
+ )
+ )
+ (cell AND4
+ (cellType GENERIC)
+ (view view_1
+ (viewType NETLIST)
+ (interface
+ (port I0
+ (direction INPUT)
+ )
+ (port I1
+ (direction INPUT)
+ )
+ (port I2
+ (direction INPUT)
+ )
+ (port I3
+ (direction INPUT)
+ )
+ (port O
+ (direction OUTPUT)
+ )
+ )
+ )
+ )
+ (cell AND3
+ (cellType GENERIC)
+ (view view_1
+ (viewType NETLIST)
+ (interface
+ (port I0
+ (direction INPUT)
+ )
+ (port I1
+ (direction INPUT)
+ )
+ (port I2
+ (direction INPUT)
+ )
+ (port O
+ (direction OUTPUT)
+ )
+ )
+ )
+ )
+ (cell OR5
+ (cellType GENERIC)
+ (view view_1
+ (viewType NETLIST)
+ (interface
+ (port I0
+ (direction INPUT)
+ )
+ (port I1
+ (direction INPUT)
+ )
+ (port I2
+ (direction INPUT)
+ )
+ (port I3
+ (direction INPUT)
+ )
+ (port I4
+ (direction INPUT)
+ )
+ (port O
+ (direction OUTPUT)
+ )
+ )
+ )
+ )
+ (cell OR4
+ (cellType GENERIC)
+ (view view_1
+ (viewType NETLIST)
+ (interface
+ (port I0
+ (direction INPUT)
+ )
+ (port I1
+ (direction INPUT)
+ )
+ (port I2
+ (direction INPUT)
+ )
+ (port I3
+ (direction INPUT)
+ )
+ (port O
+ (direction OUTPUT)
+ )
+ )
+ )
+ )
+ (cell LUT6
+ (cellType GENERIC)
+ (view view_1
+ (viewType NETLIST)
+ (interface
+ (port I0
+ (direction INPUT)
+ )
+ (port I1
+ (direction INPUT)
+ )
+ (port I2
+ (direction INPUT)
+ )
+ (port I3
+ (direction INPUT)
+ )
+ (port I4
+ (direction INPUT)
+ )
+ (port I5
+ (direction INPUT)
+ )
+ (port O
+ (direction OUTPUT)
+ )
+ )
+ )
+ )
+ (cell BUF
+ (cellType GENERIC)
+ (view view_1
+ (viewType NETLIST)
+ (interface
+ (port I
+ (direction INPUT)
+ )
+ (port O
+ (direction OUTPUT)
+ )
+ )
+ )
+ )
+ (cell XOR2
+ (cellType GENERIC)
+ (view view_1
+ (viewType NETLIST)
+ (interface
+ (port I0
+ (direction INPUT)
+ )
+ (port I1
+ (direction INPUT)
+ )
+ (port O
+ (direction OUTPUT)
+ )
+ )
+ )
+ )
+ (cell XNOR2
+ (cellType GENERIC)
+ (view view_1
+ (viewType NETLIST)
+ (interface
+ (port I0
+ (direction INPUT)
+ )
+ (port I1
+ (direction INPUT)
+ )
+ (port O
+ (direction OUTPUT)
+ )
+ )
+ )
+ )
+ (cell IBUF
+ (cellType GENERIC)
+ (view view_1
+ (viewType NETLIST)
+ (interface
+ (port I
+ (direction INPUT)
+ )
+ (port O
+ (direction OUTPUT)
+ )
+ )
+ )
+ )
+ (cell OBUF
+ (cellType GENERIC)
+ (view view_1
+ (viewType NETLIST)
+ (interface
+ (port I
+ (direction INPUT)
+ )
+ (port O
+ (direction OUTPUT)
+ )
+ )
+ )
+ )
+ )
+
+ (library ALU_lib
+ (edifLevel 0)
+ (technology (numberDefinition))
+ (cell (rename M4_1E_HXILINX_ALU_NO3_XLXI_4 "M4_1E_HXILINX_ALU")
+ (cellType GENERIC)
+ (view view_1
+ (viewType NETLIST)
+ (interface
+ (port D0
+ (direction INPUT)
+ )
+ (port D1
+ (direction INPUT)
+ )
+ (port D2
+ (direction INPUT)
+ )
+ (port D3
+ (direction INPUT)
+ )
+ (port E
+ (direction INPUT)
+ )
+ (port S0
+ (direction INPUT)
+ )
+ (port S1
+ (direction INPUT)
+ )
+ (port O
+ (direction OUTPUT)
+ )
+ )
+ (contents
+ (instance Mmux_O11
+ (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ (property INIT (string "DFD5DAD08F858A80") (owner "Xilinx"))
+ )
+ (net D0
+ (joined
+ (portRef D0)
+ (portRef I4 (instanceRef Mmux_O11))
+ )
+ )
+ (net D1
+ (joined
+ (portRef D1)
+ (portRef I3 (instanceRef Mmux_O11))
+ )
+ )
+ (net D2
+ (joined
+ (portRef D2)
+ (portRef I5 (instanceRef Mmux_O11))
+ )
+ )
+ (net D3
+ (joined
+ (portRef D3)
+ (portRef I1 (instanceRef Mmux_O11))
+ )
+ )
+ (net S0
+ (joined
+ (portRef S0)
+ (portRef I0 (instanceRef Mmux_O11))
+ )
+ )
+ (net S1
+ (joined
+ (portRef S1)
+ (portRef I2 (instanceRef Mmux_O11))
+ )
+ )
+ (net O
+ (joined
+ (portRef O)
+ (portRef O (instanceRef Mmux_O11))
+ )
+ )
+ )
+ )
+ )
+ (cell (rename M4_1E_HXILINX_ALU_NO2_XLXI_5 "M4_1E_HXILINX_ALU")
+ (cellType GENERIC)
+ (view view_1
+ (viewType NETLIST)
+ (interface
+ (port D0
+ (direction INPUT)
+ )
+ (port D1
+ (direction INPUT)
+ )
+ (port D2
+ (direction INPUT)
+ )
+ (port D3
+ (direction INPUT)
+ )
+ (port E
+ (direction INPUT)
+ )
+ (port S0
+ (direction INPUT)
+ )
+ (port S1
+ (direction INPUT)
+ )
+ (port O
+ (direction OUTPUT)
+ )
+ )
+ (contents
+ (instance Mmux_O11
+ (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ (property INIT (string "DFD5DAD08F858A80") (owner "Xilinx"))
+ )
+ (net D0
+ (joined
+ (portRef D0)
+ (portRef I4 (instanceRef Mmux_O11))
+ )
+ )
+ (net D1
+ (joined
+ (portRef D1)
+ (portRef I3 (instanceRef Mmux_O11))
+ )
+ )
+ (net D2
+ (joined
+ (portRef D2)
+ (portRef I5 (instanceRef Mmux_O11))
+ )
+ )
+ (net D3
+ (joined
+ (portRef D3)
+ (portRef I1 (instanceRef Mmux_O11))
+ )
+ )
+ (net S0
+ (joined
+ (portRef S0)
+ (portRef I0 (instanceRef Mmux_O11))
+ )
+ )
+ (net S1
+ (joined
+ (portRef S1)
+ (portRef I2 (instanceRef Mmux_O11))
+ )
+ )
+ (net O
+ (joined
+ (portRef O)
+ (portRef O (instanceRef Mmux_O11))
+ )
+ )
+ )
+ )
+ )
+ (cell (rename M4_1E_HXILINX_ALU_NO1_XLXI_6 "M4_1E_HXILINX_ALU")
+ (cellType GENERIC)
+ (view view_1
+ (viewType NETLIST)
+ (interface
+ (port D0
+ (direction INPUT)
+ )
+ (port D1
+ (direction INPUT)
+ )
+ (port D2
+ (direction INPUT)
+ )
+ (port D3
+ (direction INPUT)
+ )
+ (port E
+ (direction INPUT)
+ )
+ (port S0
+ (direction INPUT)
+ )
+ (port S1
+ (direction INPUT)
+ )
+ (port O
+ (direction OUTPUT)
+ )
+ )
+ (contents
+ (instance Mmux_O11
+ (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ (property INIT (string "DFD5DAD08F858A80") (owner "Xilinx"))
+ )
+ (net D0
+ (joined
+ (portRef D0)
+ (portRef I4 (instanceRef Mmux_O11))
+ )
+ )
+ (net D1
+ (joined
+ (portRef D1)
+ (portRef I3 (instanceRef Mmux_O11))
+ )
+ )
+ (net D2
+ (joined
+ (portRef D2)
+ (portRef I5 (instanceRef Mmux_O11))
+ )
+ )
+ (net D3
+ (joined
+ (portRef D3)
+ (portRef I1 (instanceRef Mmux_O11))
+ )
+ )
+ (net S0
+ (joined
+ (portRef S0)
+ (portRef I0 (instanceRef Mmux_O11))
+ )
+ )
+ (net S1
+ (joined
+ (portRef S1)
+ (portRef I2 (instanceRef Mmux_O11))
+ )
+ )
+ (net O
+ (joined
+ (portRef O)
+ (portRef O (instanceRef Mmux_O11))
+ )
+ )
+ )
+ )
+ )
+ (cell (rename M4_1E_HXILINX_ALU_XLXI_7 "M4_1E_HXILINX_ALU")
+ (cellType GENERIC)
+ (view view_1
+ (viewType NETLIST)
+ (interface
+ (port D0
+ (direction INPUT)
+ )
+ (port D1
+ (direction INPUT)
+ )
+ (port D2
+ (direction INPUT)
+ )
+ (port D3
+ (direction INPUT)
+ )
+ (port E
+ (direction INPUT)
+ )
+ (port S0
+ (direction INPUT)
+ )
+ (port S1
+ (direction INPUT)
+ )
+ (port O
+ (direction OUTPUT)
+ )
+ )
+ (contents
+ (instance Mmux_O11
+ (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ (property INIT (string "DFD5DAD08F858A80") (owner "Xilinx"))
+ )
+ (net D0
+ (joined
+ (portRef D0)
+ (portRef I4 (instanceRef Mmux_O11))
+ )
+ )
+ (net D1
+ (joined
+ (portRef D1)
+ (portRef I3 (instanceRef Mmux_O11))
+ )
+ )
+ (net D2
+ (joined
+ (portRef D2)
+ (portRef I5 (instanceRef Mmux_O11))
+ )
+ )
+ (net D3
+ (joined
+ (portRef D3)
+ (portRef I1 (instanceRef Mmux_O11))
+ )
+ )
+ (net S0
+ (joined
+ (portRef S0)
+ (portRef I0 (instanceRef Mmux_O11))
+ )
+ )
+ (net S1
+ (joined
+ (portRef S1)
+ (portRef I2 (instanceRef Mmux_O11))
+ )
+ )
+ (net O
+ (joined
+ (portRef O)
+ (portRef O (instanceRef Mmux_O11))
+ )
+ )
+ )
+ )
+ )
+ (cell ALU
+ (cellType GENERIC)
+ (view view_1
+ (viewType NETLIST)
+ (interface
+ (port A
+ (direction INPUT)
+ )
+ (port B
+ (direction INPUT)
+ )
+ (port C
+ (direction INPUT)
+ )
+ (port D
+ (direction INPUT)
+ )
+ (port S0
+ (direction INPUT)
+ )
+ (port S1
+ (direction INPUT)
+ )
+ (port AN0
+ (direction OUTPUT)
+ )
+ (port AN1
+ (direction OUTPUT)
+ )
+ (port AN2
+ (direction OUTPUT)
+ )
+ (port AN3
+ (direction OUTPUT)
+ )
+ (port a_out
+ (direction OUTPUT)
+ )
+ (port b_out
+ (direction OUTPUT)
+ )
+ (port c_out
+ (direction OUTPUT)
+ )
+ (port d_out
+ (direction OUTPUT)
+ )
+ (port e_out
+ (direction OUTPUT)
+ )
+ (port f_out
+ (direction OUTPUT)
+ )
+ (port g_out
+ (direction OUTPUT)
+ )
+ (port sign
+ (direction OUTPUT)
+ )
+ (designator "xc6slx16-3-csg324")
+ (property TYPE (string "ALU") (owner "Xilinx"))
+ (property SHREG_MIN_SIZE (string "2") (owner "Xilinx"))
+ (property SHREG_EXTRACT_NGC (string "YES") (owner "Xilinx"))
+ (property NLW_UNIQUE_ID (integer 0) (owner "Xilinx"))
+ (property NLW_MACRO_TAG (integer 0) (owner "Xilinx"))
+ (property NLW_MACRO_ALIAS (string "ALU_ALU") (owner "Xilinx"))
+ )
+ (contents
+ (instance XST_GND
+ (viewRef view_1 (cellRef GND (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance XLXI_8
+ (viewRef view_1 (cellRef VCC (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_1_XLXI_8_XLXI_2 "XLXI_1/XLXI_8/XLXI_2")
+ (viewRef view_1 (cellRef OR3 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_1_XLXI_8_XLXI_5 "XLXI_1/XLXI_8/XLXI_5")
+ (viewRef view_1 (cellRef OR2 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_1_XLXI_8_XLXI_7 "XLXI_1/XLXI_8/XLXI_7")
+ (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_1_XLXI_8_XLXI_6 "XLXI_1/XLXI_8/XLXI_6")
+ (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_1_XLXI_8_XLXI_4 "XLXI_1/XLXI_8/XLXI_4")
+ (viewRef view_1 (cellRef AND2 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_1_XLXI_8_XLXI_8 "XLXI_1/XLXI_8/XLXI_8")
+ (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_1_XLXI_8_XLXI_3 "XLXI_1/XLXI_8/XLXI_3")
+ (viewRef view_1 (cellRef AND2 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_1_XLXI_8_XLXI_9 "XLXI_1/XLXI_8/XLXI_9")
+ (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_1_XLXI_8_XLXI_1 "XLXI_1/XLXI_8/XLXI_1")
+ (viewRef view_1 (cellRef AND4 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_1_XLXI_9_XLXI_12 "XLXI_1/XLXI_9/XLXI_12")
+ (viewRef view_1 (cellRef OR3 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_1_XLXI_9_XLXI_10 "XLXI_1/XLXI_9/XLXI_10")
+ (viewRef view_1 (cellRef AND2 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_1_XLXI_9_XLXI_16 "XLXI_1/XLXI_9/XLXI_16")
+ (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_1_XLXI_9_XLXI_15 "XLXI_1/XLXI_9/XLXI_15")
+ (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_1_XLXI_9_XLXI_13 "XLXI_1/XLXI_9/XLXI_13")
+ (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_1_XLXI_10_XLXI_4 "XLXI_1/XLXI_10/XLXI_4")
+ (viewRef view_1 (cellRef OR3 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_1_XLXI_10_XLXI_2 "XLXI_1/XLXI_10/XLXI_2")
+ (viewRef view_1 (cellRef AND2 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_1_XLXI_10_XLXI_6 "XLXI_1/XLXI_10/XLXI_6")
+ (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_1_XLXI_10_XLXI_7 "XLXI_1/XLXI_10/XLXI_7")
+ (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_1_XLXI_10_XLXI_8 "XLXI_1/XLXI_10/XLXI_8")
+ (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_1_XLXI_12_XLXI_7 "XLXI_1/XLXI_12/XLXI_7")
+ (viewRef view_1 (cellRef OR3 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_1_XLXI_12_XLXI_9 "XLXI_1/XLXI_12/XLXI_9")
+ (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_1_XLXI_12_XLXI_5 "XLXI_1/XLXI_12/XLXI_5")
+ (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_1_XLXI_12_XLXI_3 "XLXI_1/XLXI_12/XLXI_3")
+ (viewRef view_1 (cellRef AND2 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_1_XLXI_12_XLXI_2 "XLXI_1/XLXI_12/XLXI_2")
+ (viewRef view_1 (cellRef AND2 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_1_XLXI_12_XLXI_6 "XLXI_1/XLXI_12/XLXI_6")
+ (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_1_XLXI_12_XLXI_1 "XLXI_1/XLXI_12/XLXI_1")
+ (viewRef view_1 (cellRef AND3 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_2_XLXI_2_XLXI_4 "XLXI_2/XLXI_2/XLXI_4")
+ (viewRef view_1 (cellRef OR3 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_2_XLXI_2_XLXI_2 "XLXI_2/XLXI_2/XLXI_2")
+ (viewRef view_1 (cellRef AND3 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_2_XLXI_2_XLXI_7 "XLXI_2/XLXI_2/XLXI_7")
+ (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_2_XLXI_2_XLXI_5 "XLXI_2/XLXI_2/XLXI_5")
+ (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_2_XLXI_2_XLXI_1 "XLXI_2/XLXI_2/XLXI_1")
+ (viewRef view_1 (cellRef AND3 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_2_XLXI_2_XLXI_6 "XLXI_2/XLXI_2/XLXI_6")
+ (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_2_XLXI_2_XLXI_3 "XLXI_2/XLXI_2/XLXI_3")
+ (viewRef view_1 (cellRef AND3 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_2_XLXI_1_XLXI_4 "XLXI_2/XLXI_1/XLXI_4")
+ (viewRef view_1 (cellRef OR3 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_2_XLXI_1_XLXI_2 "XLXI_2/XLXI_1/XLXI_2")
+ (viewRef view_1 (cellRef AND3 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_2_XLXI_1_XLXI_7 "XLXI_2/XLXI_1/XLXI_7")
+ (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_2_XLXI_1_XLXI_5 "XLXI_2/XLXI_1/XLXI_5")
+ (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_2_XLXI_1_XLXI_1 "XLXI_2/XLXI_1/XLXI_1")
+ (viewRef view_1 (cellRef AND3 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_2_XLXI_1_XLXI_6 "XLXI_2/XLXI_1/XLXI_6")
+ (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_2_XLXI_1_XLXI_3 "XLXI_2/XLXI_1/XLXI_3")
+ (viewRef view_1 (cellRef AND3 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_2_XLXI_3_XLXI_22 "XLXI_2/XLXI_3/XLXI_22")
+ (viewRef view_1 (cellRef OR5 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_2_XLXI_3_XLXI_20 "XLXI_2/XLXI_3/XLXI_20")
+ (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_2_XLXI_3_XLXI_15 "XLXI_2/XLXI_3/XLXI_15")
+ (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_2_XLXI_3_XLXI_2 "XLXI_2/XLXI_3/XLXI_2")
+ (viewRef view_1 (cellRef AND3 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_2_XLXI_3_XLXI_19 "XLXI_2/XLXI_3/XLXI_19")
+ (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_2_XLXI_3_XLXI_7 "XLXI_2/XLXI_3/XLXI_7")
+ (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_2_XLXI_3_XLXI_18 "XLXI_2/XLXI_3/XLXI_18")
+ (viewRef view_1 (cellRef AND4 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_2_XLXI_3_XLXI_16 "XLXI_2/XLXI_3/XLXI_16")
+ (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_2_XLXI_3_XLXI_5 "XLXI_2/XLXI_3/XLXI_5")
+ (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_2_XLXI_3_XLXI_1 "XLXI_2/XLXI_3/XLXI_1")
+ (viewRef view_1 (cellRef AND3 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_2_XLXI_3_XLXI_21 "XLXI_2/XLXI_3/XLXI_21")
+ (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_2_XLXI_3_XLXI_11 "XLXI_2/XLXI_3/XLXI_11")
+ (viewRef view_1 (cellRef AND4 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_2_XLXI_3_XLXI_6 "XLXI_2/XLXI_3/XLXI_6")
+ (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_2_XLXI_3_XLXI_3 "XLXI_2/XLXI_3/XLXI_3")
+ (viewRef view_1 (cellRef AND3 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_3_XLXI_8_XLXI_8 "XLXI_3/XLXI_8/XLXI_8")
+ (viewRef view_1 (cellRef AND3 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_3_XLXI_8_XLXI_10 "XLXI_3/XLXI_8/XLXI_10")
+ (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_3_XLXI_8_XLXI_9 "XLXI_3/XLXI_8/XLXI_9")
+ (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_3_XLXI_8_XLXI_12 "XLXI_3/XLXI_8/XLXI_12")
+ (viewRef view_1 (cellRef OR2 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_3_XLXI_9_XLXI_4 "XLXI_3/XLXI_9/XLXI_4")
+ (viewRef view_1 (cellRef OR3 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_3_XLXI_9_XLXI_3 "XLXI_3/XLXI_9/XLXI_3")
+ (viewRef view_1 (cellRef AND3 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_3_XLXI_9_XLXI_5 "XLXI_3/XLXI_9/XLXI_5")
+ (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_3_XLXI_9_XLXI_6 "XLXI_3/XLXI_9/XLXI_6")
+ (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_3_XLXI_9_XLXI_1 "XLXI_3/XLXI_9/XLXI_1")
+ (viewRef view_1 (cellRef AND2 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_3_XLXI_9_XLXI_7 "XLXI_3/XLXI_9/XLXI_7")
+ (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_3_XLXI_9_XLXI_2 "XLXI_3/XLXI_9/XLXI_2")
+ (viewRef view_1 (cellRef AND2 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_3_XLXI_10_XLXI_8 "XLXI_3/XLXI_10/XLXI_8")
+ (viewRef view_1 (cellRef OR4 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_3_XLXI_10_XLXI_9 "XLXI_3/XLXI_10/XLXI_9")
+ (viewRef view_1 (cellRef AND2 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_3_XLXI_10_XLXI_15 "XLXI_3/XLXI_10/XLXI_15")
+ (viewRef view_1 (cellRef AND3 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_3_XLXI_10_XLXI_14 "XLXI_3/XLXI_10/XLXI_14")
+ (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_3_XLXI_10_XLXI_16 "XLXI_3/XLXI_10/XLXI_16")
+ (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_3_XLXI_10_XLXI_10 "XLXI_3/XLXI_10/XLXI_10")
+ (viewRef view_1 (cellRef AND2 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_3_XLXI_10_XLXI_17 "XLXI_3/XLXI_10/XLXI_17")
+ (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_3_XLXI_10_XLXI_11 "XLXI_3/XLXI_10/XLXI_11")
+ (viewRef view_1 (cellRef AND2 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_3_XLXI_12_XLXI_16 "XLXI_3/XLXI_12/XLXI_16")
+ (viewRef view_1 (cellRef AND2 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_3_XLXI_12_XLXI_15 "XLXI_3/XLXI_12/XLXI_15")
+ (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_3_XLXI_12_XLXI_14 "XLXI_3/XLXI_12/XLXI_14")
+ (viewRef view_1 (cellRef OR3 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_2_XLXI_4_XLXI_14 "XLXI_2/XLXI_4/XLXI_14")
+ (viewRef view_1 (cellRef OR2 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_2_XLXI_4_XLXI_4 "XLXI_2/XLXI_4/XLXI_4")
+ (viewRef view_1 (cellRef OR2 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_2_XLXI_4_XLXI_16 "XLXI_2/XLXI_4/XLXI_16")
+ (viewRef view_1 (cellRef AND2 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_2_XLXI_4_XLXI_12 "XLXI_2/XLXI_4/XLXI_12")
+ (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_2_XLXI_4_XLXI_2 "XLXI_2/XLXI_4/XLXI_2")
+ (viewRef view_1 (cellRef AND2 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_2_XLXI_4_XLXI_13 "XLXI_2/XLXI_4/XLXI_13")
+ (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_2_XLXI_4_XLXI_9 "XLXI_2/XLXI_4/XLXI_9")
+ (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_2_XLXI_4_XLXI_15 "XLXI_2/XLXI_4/XLXI_15")
+ (viewRef view_1 (cellRef AND2 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_2_XLXI_4_XLXI_11 "XLXI_2/XLXI_4/XLXI_11")
+ (viewRef view_1 (cellRef AND3 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_2_XLXI_4_XLXI_10 "XLXI_2/XLXI_4/XLXI_10")
+ (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance XLXI_7
+ (viewRef view_1 (cellRef M4_1E_HXILINX_ALU_XLXI_7 (libraryRef ALU_lib)))
+ (property HU_SET (string "XLXI_7_3") (owner "Xilinx"))
+ (property NLW_UNIQUE_ID (integer 0) (owner "Xilinx"))
+ (property NLW_MACRO_TAG (integer 1) (owner "Xilinx"))
+ (property NLW_MACRO_ALIAS (string "M4_1E_HXILINX_ALU_XLXI_7") (owner "Xilinx"))
+ )
+ (instance XLXI_6
+ (viewRef view_1 (cellRef M4_1E_HXILINX_ALU_NO1_XLXI_6 (libraryRef ALU_lib)))
+ (property HU_SET (string "XLXI_6_2") (owner "Xilinx"))
+ (property NLW_UNIQUE_ID (integer 1) (owner "Xilinx"))
+ (property NLW_MACRO_TAG (integer 2) (owner "Xilinx"))
+ (property NLW_MACRO_ALIAS (string "M4_1E_HXILINX_ALU_NO1_XLXI_6") (owner "Xilinx"))
+ )
+ (instance XLXI_5
+ (viewRef view_1 (cellRef M4_1E_HXILINX_ALU_NO2_XLXI_5 (libraryRef ALU_lib)))
+ (property HU_SET (string "XLXI_5_1") (owner "Xilinx"))
+ (property NLW_UNIQUE_ID (integer 2) (owner "Xilinx"))
+ (property NLW_MACRO_TAG (integer 3) (owner "Xilinx"))
+ (property NLW_MACRO_ALIAS (string "M4_1E_HXILINX_ALU_NO2_XLXI_5") (owner "Xilinx"))
+ )
+ (instance XLXI_4
+ (viewRef view_1 (cellRef M4_1E_HXILINX_ALU_NO3_XLXI_4 (libraryRef ALU_lib)))
+ (property HU_SET (string "XLXI_4_0") (owner "Xilinx"))
+ (property NLW_UNIQUE_ID (integer 3) (owner "Xilinx"))
+ (property NLW_MACRO_TAG (integer 4) (owner "Xilinx"))
+ (property NLW_MACRO_ALIAS (string "M4_1E_HXILINX_ALU_NO3_XLXI_4") (owner "Xilinx"))
+ )
+ (instance (rename XLXI_9_XLXI_8 "XLXI_9/XLXI_8")
+ (viewRef view_1 (cellRef BUF (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_9_XLXI_7 "XLXI_9/XLXI_7")
+ (viewRef view_1 (cellRef BUF (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_9_XLXI_6 "XLXI_9/XLXI_6")
+ (viewRef view_1 (cellRef BUF (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_9_XLXI_5 "XLXI_9/XLXI_5")
+ (viewRef view_1 (cellRef BUF (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_9_XLXI_68 "XLXI_9/XLXI_68")
+ (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_9_XLXI_69 "XLXI_9/XLXI_69")
+ (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_9_XLXI_71 "XLXI_9/XLXI_71")
+ (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_9_XLXI_70 "XLXI_9/XLXI_70")
+ (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_9_XLXI_66 "XLXI_9/XLXI_66")
+ (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_9_XLXI_73 "XLXI_9/XLXI_73")
+ (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_9_XLXI_65 "XLXI_9/XLXI_65")
+ (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_9_XLXI_67 "XLXI_9/XLXI_67")
+ (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_9_XLXI_53 "XLXI_9/XLXI_53")
+ (viewRef view_1 (cellRef OR2 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_9_XLXI_57 "XLXI_9/XLXI_57")
+ (viewRef view_1 (cellRef AND2 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_9_XLXI_43 "XLXI_9/XLXI_43")
+ (viewRef view_1 (cellRef AND2 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_9_XLXI_52 "XLXI_9/XLXI_52")
+ (viewRef view_1 (cellRef OR4 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_9_XLXI_49 "XLXI_9/XLXI_49")
+ (viewRef view_1 (cellRef AND2 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_9_XLXI_44 "XLXI_9/XLXI_44")
+ (viewRef view_1 (cellRef AND2 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_9_XLXI_32 "XLXI_9/XLXI_32")
+ (viewRef view_1 (cellRef AND2 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_9_XLXI_60 "XLXI_9/XLXI_60")
+ (viewRef view_1 (cellRef OR4 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_9_XLXI_58 "XLXI_9/XLXI_58")
+ (viewRef view_1 (cellRef OR4 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_9_XLXI_41 "XLXI_9/XLXI_41")
+ (viewRef view_1 (cellRef OR4 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_9_XLXI_72 "XLXI_9/XLXI_72")
+ (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_9_XLXI_34 "XLXI_9/XLXI_34")
+ (viewRef view_1 (cellRef OR5 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_9_XLXI_47 "XLXI_9/XLXI_47")
+ (viewRef view_1 (cellRef OR3 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_9_XLXI_40 "XLXI_9/XLXI_40")
+ (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_9_XLXI_63 "XLXI_9/XLXI_63")
+ (viewRef view_1 (cellRef AND2 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_9_XLXI_62 "XLXI_9/XLXI_62")
+ (viewRef view_1 (cellRef AND2 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_9_XLXI_50 "XLXI_9/XLXI_50")
+ (viewRef view_1 (cellRef AND2 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_9_XLXI_48 "XLXI_9/XLXI_48")
+ (viewRef view_1 (cellRef AND2 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_9_XLXI_45 "XLXI_9/XLXI_45")
+ (viewRef view_1 (cellRef AND3 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_9_XLXI_39 "XLXI_9/XLXI_39")
+ (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_9_XLXI_33 "XLXI_9/XLXI_33")
+ (viewRef view_1 (cellRef AND2 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_9_XLXI_31 "XLXI_9/XLXI_31")
+ (viewRef view_1 (cellRef AND3 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_9_XLXI_61 "XLXI_9/XLXI_61")
+ (viewRef view_1 (cellRef AND2 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_9_XLXI_56 "XLXI_9/XLXI_56")
+ (viewRef view_1 (cellRef AND3 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_9_XLXI_54 "XLXI_9/XLXI_54")
+ (viewRef view_1 (cellRef AND3 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_9_XLXI_51 "XLXI_9/XLXI_51")
+ (viewRef view_1 (cellRef AND3 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_9_XLXI_38 "XLXI_9/XLXI_38")
+ (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_9_XLXI_30 "XLXI_9/XLXI_30")
+ (viewRef view_1 (cellRef AND3 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_9_XLXI_64 "XLXI_9/XLXI_64")
+ (viewRef view_1 (cellRef AND2 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_9_XLXI_55 "XLXI_9/XLXI_55")
+ (viewRef view_1 (cellRef AND3 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_9_XLXI_46 "XLXI_9/XLXI_46")
+ (viewRef view_1 (cellRef XOR2 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_9_XLXI_42 "XLXI_9/XLXI_42")
+ (viewRef view_1 (cellRef XNOR2 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_9_XLXI_37 "XLXI_9/XLXI_37")
+ (viewRef view_1 (cellRef INV (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename XLXI_9_XLXI_35 "XLXI_9/XLXI_35")
+ (viewRef view_1 (cellRef AND2 (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename A_IBUF_renamed_0 "A_IBUF")
+ (viewRef view_1 (cellRef IBUF (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename B_IBUF_renamed_1 "B_IBUF")
+ (viewRef view_1 (cellRef IBUF (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename C_IBUF_renamed_2 "C_IBUF")
+ (viewRef view_1 (cellRef IBUF (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename D_IBUF_renamed_3 "D_IBUF")
+ (viewRef view_1 (cellRef IBUF (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename S0_IBUF_renamed_4 "S0_IBUF")
+ (viewRef view_1 (cellRef IBUF (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename S1_IBUF_renamed_5 "S1_IBUF")
+ (viewRef view_1 (cellRef IBUF (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename AN0_OBUF_renamed_6 "AN0_OBUF")
+ (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename AN1_OBUF_renamed_7 "AN1_OBUF")
+ (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename AN2_OBUF_renamed_8 "AN2_OBUF")
+ (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename AN3_OBUF_renamed_9 "AN3_OBUF")
+ (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename a_out_OBUF_renamed_10 "a_out_OBUF")
+ (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename b_out_OBUF_renamed_11 "b_out_OBUF")
+ (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename c_out_OBUF_renamed_12 "c_out_OBUF")
+ (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename d_out_OBUF_renamed_13 "d_out_OBUF")
+ (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename e_out_OBUF_renamed_14 "e_out_OBUF")
+ (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename f_out_OBUF_renamed_15 "f_out_OBUF")
+ (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename g_out_OBUF_renamed_16 "g_out_OBUF")
+ (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (instance (rename sign_OBUF_renamed_17 "sign_OBUF")
+ (viewRef view_1 (cellRef OBUF (libraryRef UNISIMS)))
+ (property XSTLIB (boolean (true)) (owner "Xilinx"))
+ )
+ (net A_IBUF
+ (joined
+ (portRef I (instanceRef XLXI_1_XLXI_8_XLXI_7))
+ (portRef I0 (instanceRef XLXI_1_XLXI_8_XLXI_1))
+ (portRef I1 (instanceRef XLXI_1_XLXI_9_XLXI_10))
+ (portRef I1 (instanceRef XLXI_1_XLXI_10_XLXI_2))
+ (portRef I (instanceRef XLXI_1_XLXI_12_XLXI_9))
+ (portRef I1 (instanceRef XLXI_1_XLXI_12_XLXI_1))
+ (portRef I2 (instanceRef XLXI_2_XLXI_2_XLXI_2))
+ (portRef I2 (instanceRef XLXI_2_XLXI_2_XLXI_1))
+ (portRef I2 (instanceRef XLXI_2_XLXI_2_XLXI_3))
+ (portRef I2 (instanceRef XLXI_2_XLXI_1_XLXI_2))
+ (portRef I2 (instanceRef XLXI_2_XLXI_1_XLXI_1))
+ (portRef I2 (instanceRef XLXI_2_XLXI_1_XLXI_3))
+ (portRef I (instanceRef XLXI_2_XLXI_3_XLXI_20))
+ (portRef I (instanceRef XLXI_2_XLXI_3_XLXI_15))
+ (portRef I2 (instanceRef XLXI_2_XLXI_3_XLXI_2))
+ (portRef I2 (instanceRef XLXI_2_XLXI_3_XLXI_1))
+ (portRef I2 (instanceRef XLXI_2_XLXI_3_XLXI_3))
+ (portRef I0 (instanceRef XLXI_3_XLXI_8_XLXI_8))
+ (portRef I2 (instanceRef XLXI_3_XLXI_9_XLXI_3))
+ (portRef I1 (instanceRef XLXI_3_XLXI_10_XLXI_9))
+ (portRef I (instanceRef XLXI_3_XLXI_12_XLXI_15))
+ (portRef D0 (instanceRef XLXI_4))
+ (portRef O (instanceRef A_IBUF_renamed_0))
+ )
+ )
+ (net B_IBUF
+ (joined
+ (portRef I (instanceRef XLXI_1_XLXI_8_XLXI_6))
+ (portRef I1 (instanceRef XLXI_1_XLXI_8_XLXI_4))
+ (portRef I (instanceRef XLXI_1_XLXI_9_XLXI_16))
+ (portRef I (instanceRef XLXI_1_XLXI_10_XLXI_6))
+ (portRef I (instanceRef XLXI_2_XLXI_2_XLXI_7))
+ (portRef I1 (instanceRef XLXI_2_XLXI_2_XLXI_1))
+ (portRef I (instanceRef XLXI_2_XLXI_1_XLXI_7))
+ (portRef I1 (instanceRef XLXI_2_XLXI_1_XLXI_1))
+ (portRef I (instanceRef XLXI_2_XLXI_3_XLXI_19))
+ (portRef I (instanceRef XLXI_2_XLXI_3_XLXI_7))
+ (portRef I1 (instanceRef XLXI_2_XLXI_3_XLXI_1))
+ (portRef I2 (instanceRef XLXI_2_XLXI_3_XLXI_11))
+ (portRef I (instanceRef XLXI_3_XLXI_8_XLXI_10))
+ (portRef I (instanceRef XLXI_3_XLXI_9_XLXI_5))
+ (portRef I2 (instanceRef XLXI_3_XLXI_10_XLXI_15))
+ (portRef I (instanceRef XLXI_3_XLXI_10_XLXI_14))
+ (portRef I2 (instanceRef XLXI_3_XLXI_12_XLXI_14))
+ (portRef I1 (instanceRef XLXI_2_XLXI_4_XLXI_2))
+ (portRef I (instanceRef XLXI_2_XLXI_4_XLXI_12))
+ (portRef D0 (instanceRef XLXI_5))
+ (portRef O (instanceRef B_IBUF_renamed_1))
+ )
+ )
+ (net C_IBUF
+ (joined
+ (portRef I (instanceRef XLXI_1_XLXI_8_XLXI_8))
+ (portRef I1 (instanceRef XLXI_1_XLXI_8_XLXI_3))
+ (portRef I1 (instanceRef XLXI_1_XLXI_8_XLXI_1))
+ (portRef I (instanceRef XLXI_1_XLXI_9_XLXI_15))
+ (portRef I (instanceRef XLXI_1_XLXI_10_XLXI_7))
+ (portRef I (instanceRef XLXI_1_XLXI_12_XLXI_5))
+ (portRef I0 (instanceRef XLXI_1_XLXI_12_XLXI_3))
+ (portRef I0 (instanceRef XLXI_1_XLXI_12_XLXI_2))
+ (portRef I (instanceRef XLXI_2_XLXI_2_XLXI_5))
+ (portRef I0 (instanceRef XLXI_2_XLXI_2_XLXI_1))
+ (portRef I (instanceRef XLXI_2_XLXI_1_XLXI_5))
+ (portRef I0 (instanceRef XLXI_2_XLXI_1_XLXI_1))
+ (portRef I1 (instanceRef XLXI_2_XLXI_3_XLXI_18))
+ (portRef I (instanceRef XLXI_2_XLXI_3_XLXI_16))
+ (portRef I (instanceRef XLXI_2_XLXI_3_XLXI_5))
+ (portRef I0 (instanceRef XLXI_2_XLXI_3_XLXI_1))
+ (portRef I (instanceRef XLXI_3_XLXI_8_XLXI_9))
+ (portRef I (instanceRef XLXI_3_XLXI_9_XLXI_6))
+ (portRef I0 (instanceRef XLXI_3_XLXI_9_XLXI_1))
+ (portRef I (instanceRef XLXI_3_XLXI_10_XLXI_16))
+ (portRef I0 (instanceRef XLXI_3_XLXI_10_XLXI_10))
+ (portRef I1 (instanceRef XLXI_3_XLXI_12_XLXI_14))
+ (portRef I1 (instanceRef XLXI_2_XLXI_4_XLXI_15))
+ (portRef I (instanceRef XLXI_2_XLXI_4_XLXI_9))
+ (portRef I (instanceRef XLXI_2_XLXI_4_XLXI_13))
+ (portRef D0 (instanceRef XLXI_6))
+ (portRef O (instanceRef C_IBUF_renamed_2))
+ )
+ )
+ (net D_IBUF
+ (joined
+ (portRef I (instanceRef XLXI_1_XLXI_8_XLXI_9))
+ (portRef I3 (instanceRef XLXI_1_XLXI_8_XLXI_1))
+ (portRef I (instanceRef XLXI_1_XLXI_9_XLXI_13))
+ (portRef I (instanceRef XLXI_1_XLXI_10_XLXI_8))
+ (portRef I (instanceRef XLXI_1_XLXI_12_XLXI_6))
+ (portRef I0 (instanceRef XLXI_1_XLXI_12_XLXI_1))
+ (portRef I (instanceRef XLXI_2_XLXI_2_XLXI_6))
+ (portRef I0 (instanceRef XLXI_2_XLXI_2_XLXI_3))
+ (portRef I (instanceRef XLXI_2_XLXI_1_XLXI_6))
+ (portRef I0 (instanceRef XLXI_2_XLXI_1_XLXI_3))
+ (portRef I (instanceRef XLXI_2_XLXI_3_XLXI_21))
+ (portRef I0 (instanceRef XLXI_2_XLXI_3_XLXI_11))
+ (portRef I (instanceRef XLXI_2_XLXI_3_XLXI_6))
+ (portRef I0 (instanceRef XLXI_2_XLXI_3_XLXI_3))
+ (portRef I1 (instanceRef XLXI_3_XLXI_8_XLXI_12))
+ (portRef I (instanceRef XLXI_3_XLXI_9_XLXI_7))
+ (portRef I1 (instanceRef XLXI_3_XLXI_9_XLXI_2))
+ (portRef I (instanceRef XLXI_3_XLXI_10_XLXI_17))
+ (portRef I0 (instanceRef XLXI_3_XLXI_10_XLXI_11))
+ (portRef I0 (instanceRef XLXI_3_XLXI_12_XLXI_14))
+ (portRef I (instanceRef XLXI_2_XLXI_4_XLXI_10))
+ (portRef I0 (instanceRef XLXI_2_XLXI_4_XLXI_11))
+ (portRef I0 (instanceRef XLXI_2_XLXI_4_XLXI_15))
+ (portRef D0 (instanceRef XLXI_7))
+ (portRef O (instanceRef D_IBUF_renamed_3))
+ )
+ )
+ (net S0_IBUF
+ (joined
+ (portRef S0 (instanceRef XLXI_7))
+ (portRef S0 (instanceRef XLXI_6))
+ (portRef S0 (instanceRef XLXI_5))
+ (portRef S0 (instanceRef XLXI_4))
+ (portRef O (instanceRef S0_IBUF_renamed_4))
+ )
+ )
+ (net S1_IBUF
+ (joined
+ (portRef S1 (instanceRef XLXI_7))
+ (portRef S1 (instanceRef XLXI_6))
+ (portRef S1 (instanceRef XLXI_5))
+ (portRef S1 (instanceRef XLXI_4))
+ (portRef O (instanceRef S1_IBUF_renamed_5))
+ )
+ )
+ (net XLXN_36
+ (joined
+ (portRef O (instanceRef XLXI_1_XLXI_12_XLXI_7))
+ (portRef D2 (instanceRef XLXI_7))
+ )
+ )
+ (net XLXN_35
+ (joined
+ (portRef O (instanceRef XLXI_1_XLXI_8_XLXI_5))
+ (portRef D2 (instanceRef XLXI_6))
+ )
+ )
+ (net XLXN_34
+ (joined
+ (portRef O (instanceRef XLXI_1_XLXI_9_XLXI_10))
+ (portRef D2 (instanceRef XLXI_5))
+ )
+ )
+ (net XLXN_33
+ (joined
+ (portRef O (instanceRef XLXI_1_XLXI_10_XLXI_2))
+ (portRef D2 (instanceRef XLXI_4))
+ )
+ )
+ (net XLXN_37
+ (joined
+ (portRef O (instanceRef XLXI_2_XLXI_4_XLXI_4))
+ (portRef D3 (instanceRef XLXI_7))
+ )
+ )
+ (net XLXN_38
+ (joined
+ (portRef O (instanceRef XLXI_2_XLXI_3_XLXI_22))
+ (portRef D3 (instanceRef XLXI_6))
+ )
+ )
+ (net XLXN_39
+ (joined
+ (portRef O (instanceRef XLXI_2_XLXI_2_XLXI_4))
+ (portRef D3 (instanceRef XLXI_5))
+ )
+ )
+ (net XLXN_41
+ (joined
+ (portRef O (instanceRef XLXI_2_XLXI_1_XLXI_4))
+ (portRef D3 (instanceRef XLXI_4))
+ )
+ )
+ (net XLXN_42
+ (joined
+ (portRef O (instanceRef XLXI_3_XLXI_8_XLXI_12))
+ (portRef D1 (instanceRef XLXI_7))
+ )
+ )
+ (net XLXN_43
+ (joined
+ (portRef O (instanceRef XLXI_3_XLXI_9_XLXI_4))
+ (portRef D1 (instanceRef XLXI_6))
+ )
+ )
+ (net XLXN_44
+ (joined
+ (portRef O (instanceRef XLXI_3_XLXI_10_XLXI_8))
+ (portRef D1 (instanceRef XLXI_5))
+ )
+ )
+ (net XLXN_45
+ (joined
+ (portRef O (instanceRef XLXI_3_XLXI_12_XLXI_16))
+ (portRef D1 (instanceRef XLXI_4))
+ )
+ )
+ (net XLXN_22
+ (joined
+ (portRef O (instanceRef XLXI_4))
+ (portRef I1 (instanceRef XLXI_9_XLXI_35))
+ (portRef I (instanceRef XLXI_9_XLXI_37))
+ (portRef I1 (instanceRef XLXI_9_XLXI_42))
+ (portRef I1 (instanceRef XLXI_9_XLXI_46))
+ (portRef I2 (instanceRef XLXI_9_XLXI_55))
+ (portRef I1 (instanceRef XLXI_9_XLXI_64))
+ )
+ )
+ (net XLXN_23
+ (joined
+ (portRef O (instanceRef XLXI_5))
+ (portRef I0 (instanceRef XLXI_9_XLXI_42))
+ (portRef I0 (instanceRef XLXI_9_XLXI_46))
+ (portRef I0 (instanceRef XLXI_9_XLXI_30))
+ (portRef I (instanceRef XLXI_9_XLXI_38))
+ (portRef I2 (instanceRef XLXI_9_XLXI_51))
+ (portRef I1 (instanceRef XLXI_9_XLXI_54))
+ (portRef I1 (instanceRef XLXI_9_XLXI_56))
+ (portRef I1 (instanceRef XLXI_9_XLXI_61))
+ )
+ )
+ (net XLXN_24
+ (joined
+ (portRef O (instanceRef XLXI_6))
+ (portRef I0 (instanceRef XLXI_9_XLXI_55))
+ (portRef I2 (instanceRef XLXI_9_XLXI_31))
+ (portRef I0 (instanceRef XLXI_9_XLXI_33))
+ (portRef I (instanceRef XLXI_9_XLXI_39))
+ (portRef I2 (instanceRef XLXI_9_XLXI_45))
+ (portRef I1 (instanceRef XLXI_9_XLXI_48))
+ (portRef I0 (instanceRef XLXI_9_XLXI_50))
+ (portRef I1 (instanceRef XLXI_9_XLXI_62))
+ (portRef I1 (instanceRef XLXI_9_XLXI_63))
+ )
+ )
+ (net XLXN_25
+ (joined
+ (portRef O (instanceRef XLXI_7))
+ (portRef I2 (instanceRef XLXI_9_XLXI_30))
+ (portRef I1 (instanceRef XLXI_9_XLXI_51))
+ (portRef I1 (instanceRef XLXI_9_XLXI_31))
+ (portRef I1 (instanceRef XLXI_9_XLXI_45))
+ (portRef I (instanceRef XLXI_9_XLXI_40))
+ (portRef I0 (instanceRef XLXI_9_XLXI_47))
+ )
+ )
+ (net AN0_OBUF
+ (joined
+ (portRef O (instanceRef XLXI_9_XLXI_5))
+ (portRef I (instanceRef AN0_OBUF_renamed_6))
+ )
+ )
+ (net AN1_OBUF
+ (joined
+ (portRef O (instanceRef XLXI_9_XLXI_6))
+ (portRef I (instanceRef AN1_OBUF_renamed_7))
+ )
+ )
+ (net AN2_OBUF
+ (joined
+ (portRef O (instanceRef XLXI_9_XLXI_7))
+ (portRef I (instanceRef AN2_OBUF_renamed_8))
+ )
+ )
+ (net AN3_OBUF
+ (joined
+ (portRef O (instanceRef XLXI_9_XLXI_8))
+ (portRef I (instanceRef AN3_OBUF_renamed_9))
+ )
+ )
+ (net a_out_OBUF
+ (joined
+ (portRef O (instanceRef XLXI_9_XLXI_65))
+ (portRef I (instanceRef a_out_OBUF_renamed_10))
+ )
+ )
+ (net b_out_OBUF
+ (joined
+ (portRef O (instanceRef XLXI_9_XLXI_66))
+ (portRef I (instanceRef b_out_OBUF_renamed_11))
+ )
+ )
+ (net c_out_OBUF
+ (joined
+ (portRef O (instanceRef XLXI_9_XLXI_67))
+ (portRef I (instanceRef c_out_OBUF_renamed_12))
+ )
+ )
+ (net d_out_OBUF
+ (joined
+ (portRef O (instanceRef XLXI_9_XLXI_69))
+ (portRef I (instanceRef d_out_OBUF_renamed_13))
+ )
+ )
+ (net e_out_OBUF
+ (joined
+ (portRef O (instanceRef XLXI_9_XLXI_68))
+ (portRef I (instanceRef e_out_OBUF_renamed_14))
+ )
+ )
+ (net f_out_OBUF
+ (joined
+ (portRef O (instanceRef XLXI_9_XLXI_70))
+ (portRef I (instanceRef f_out_OBUF_renamed_15))
+ )
+ )
+ (net g_out_OBUF
+ (joined
+ (portRef O (instanceRef XLXI_9_XLXI_71))
+ (portRef I (instanceRef g_out_OBUF_renamed_16))
+ )
+ )
+ (net sign_OBUF
+ (joined
+ (portRef O (instanceRef XLXI_9_XLXI_73))
+ (portRef I (instanceRef sign_OBUF_renamed_17))
+ )
+ )
+ (net XLXN_12
+ (joined
+ (portRef P (instanceRef XLXI_8))
+ (portRef E (instanceRef XLXI_7))
+ (portRef E (instanceRef XLXI_6))
+ (portRef E (instanceRef XLXI_5))
+ (portRef E (instanceRef XLXI_4))
+ (portRef I (instanceRef XLXI_9_XLXI_5))
+ (portRef I (instanceRef XLXI_9_XLXI_6))
+ (portRef I (instanceRef XLXI_9_XLXI_7))
+ )
+ )
+ (net N0
+ (joined
+ (portRef G (instanceRef XST_GND))
+ (portRef I (instanceRef XLXI_9_XLXI_8))
+ )
+ )
+ (net (rename XLXI_1_XLXI_8_XLXN_2 "XLXI_1/XLXI_8/XLXN_2")
+ (joined
+ (portRef O (instanceRef XLXI_1_XLXI_8_XLXI_2))
+ (portRef I0 (instanceRef XLXI_1_XLXI_8_XLXI_4))
+ )
+ )
+ (net (rename XLXI_1_XLXI_8_XLXN_13 "XLXI_1/XLXI_8/XLXN_13")
+ (joined
+ (portRef I2 (instanceRef XLXI_1_XLXI_8_XLXI_2))
+ (portRef O (instanceRef XLXI_1_XLXI_8_XLXI_7))
+ )
+ )
+ (net (rename XLXI_1_XLXI_8_XLXN_8 "XLXI_1/XLXI_8/XLXN_8")
+ (joined
+ (portRef O (instanceRef XLXI_1_XLXI_8_XLXI_6))
+ (portRef I2 (instanceRef XLXI_1_XLXI_8_XLXI_1))
+ )
+ )
+ (net (rename XLXI_1_XLXI_8_XLXN_4 "XLXI_1/XLXI_8/XLXN_4")
+ (joined
+ (portRef I1 (instanceRef XLXI_1_XLXI_8_XLXI_5))
+ (portRef O (instanceRef XLXI_1_XLXI_8_XLXI_4))
+ )
+ )
+ (net (rename XLXI_1_XLXI_8_XLXN_16 "XLXI_1/XLXI_8/XLXN_16")
+ (joined
+ (portRef I0 (instanceRef XLXI_1_XLXI_8_XLXI_2))
+ (portRef O (instanceRef XLXI_1_XLXI_8_XLXI_8))
+ )
+ )
+ (net (rename XLXI_1_XLXI_8_XLXN_1 "XLXI_1/XLXI_8/XLXN_1")
+ (joined
+ (portRef I1 (instanceRef XLXI_1_XLXI_8_XLXI_2))
+ (portRef O (instanceRef XLXI_1_XLXI_8_XLXI_3))
+ )
+ )
+ (net (rename XLXI_1_XLXI_8_XLXN_17 "XLXI_1/XLXI_8/XLXN_17")
+ (joined
+ (portRef I0 (instanceRef XLXI_1_XLXI_8_XLXI_3))
+ (portRef O (instanceRef XLXI_1_XLXI_8_XLXI_9))
+ )
+ )
+ (net (rename XLXI_1_XLXI_8_XLXN_5 "XLXI_1/XLXI_8/XLXN_5")
+ (joined
+ (portRef I0 (instanceRef XLXI_1_XLXI_8_XLXI_5))
+ (portRef O (instanceRef XLXI_1_XLXI_8_XLXI_1))
+ )
+ )
+ (net (rename XLXI_1_XLXI_9_XLXN_9 "XLXI_1/XLXI_9/XLXN_9")
+ (joined
+ (portRef O (instanceRef XLXI_1_XLXI_9_XLXI_12))
+ (portRef I0 (instanceRef XLXI_1_XLXI_9_XLXI_10))
+ )
+ )
+ (net (rename XLXI_1_XLXI_9_XLXN_15 "XLXI_1/XLXI_9/XLXN_15")
+ (joined
+ (portRef I0 (instanceRef XLXI_1_XLXI_9_XLXI_12))
+ (portRef O (instanceRef XLXI_1_XLXI_9_XLXI_16))
+ )
+ )
+ (net (rename XLXI_1_XLXI_9_XLXN_14 "XLXI_1/XLXI_9/XLXN_14")
+ (joined
+ (portRef I1 (instanceRef XLXI_1_XLXI_9_XLXI_12))
+ (portRef O (instanceRef XLXI_1_XLXI_9_XLXI_15))
+ )
+ )
+ (net (rename XLXI_1_XLXI_9_XLXN_13 "XLXI_1/XLXI_9/XLXN_13")
+ (joined
+ (portRef I2 (instanceRef XLXI_1_XLXI_9_XLXI_12))
+ (portRef O (instanceRef XLXI_1_XLXI_9_XLXI_13))
+ )
+ )
+ (net (rename XLXI_1_XLXI_10_XLXN_2 "XLXI_1/XLXI_10/XLXN_2")
+ (joined
+ (portRef O (instanceRef XLXI_1_XLXI_10_XLXI_4))
+ (portRef I0 (instanceRef XLXI_1_XLXI_10_XLXI_2))
+ )
+ )
+ (net (rename XLXI_1_XLXI_10_XLXN_13 "XLXI_1/XLXI_10/XLXN_13")
+ (joined
+ (portRef I2 (instanceRef XLXI_1_XLXI_10_XLXI_4))
+ (portRef O (instanceRef XLXI_1_XLXI_10_XLXI_6))
+ )
+ )
+ (net (rename XLXI_1_XLXI_10_XLXN_14 "XLXI_1/XLXI_10/XLXN_14")
+ (joined
+ (portRef I1 (instanceRef XLXI_1_XLXI_10_XLXI_4))
+ (portRef O (instanceRef XLXI_1_XLXI_10_XLXI_7))
+ )
+ )
+ (net (rename XLXI_1_XLXI_10_XLXN_15 "XLXI_1/XLXI_10/XLXN_15")
+ (joined
+ (portRef I0 (instanceRef XLXI_1_XLXI_10_XLXI_4))
+ (portRef O (instanceRef XLXI_1_XLXI_10_XLXI_8))
+ )
+ )
+ (net (rename XLXI_1_XLXI_12_XLXN_12 "XLXI_1/XLXI_12/XLXN_12")
+ (joined
+ (portRef O (instanceRef XLXI_1_XLXI_12_XLXI_9))
+ (portRef I1 (instanceRef XLXI_1_XLXI_12_XLXI_2))
+ )
+ )
+ (net (rename XLXI_1_XLXI_12_XLXN_2 "XLXI_1/XLXI_12/XLXN_2")
+ (joined
+ (portRef O (instanceRef XLXI_1_XLXI_12_XLXI_5))
+ (portRef I2 (instanceRef XLXI_1_XLXI_12_XLXI_1))
+ )
+ )
+ (net (rename XLXI_1_XLXI_12_XLXN_6 "XLXI_1/XLXI_12/XLXN_6")
+ (joined
+ (portRef I0 (instanceRef XLXI_1_XLXI_12_XLXI_7))
+ (portRef O (instanceRef XLXI_1_XLXI_12_XLXI_3))
+ )
+ )
+ (net (rename XLXI_1_XLXI_12_XLXN_4 "XLXI_1/XLXI_12/XLXN_4")
+ (joined
+ (portRef I2 (instanceRef XLXI_1_XLXI_12_XLXI_7))
+ (portRef O (instanceRef XLXI_1_XLXI_12_XLXI_2))
+ )
+ )
+ (net (rename XLXI_1_XLXI_12_XLXN_3 "XLXI_1/XLXI_12/XLXN_3")
+ (joined
+ (portRef I1 (instanceRef XLXI_1_XLXI_12_XLXI_3))
+ (portRef O (instanceRef XLXI_1_XLXI_12_XLXI_6))
+ )
+ )
+ (net (rename XLXI_1_XLXI_12_XLXN_5 "XLXI_1/XLXI_12/XLXN_5")
+ (joined
+ (portRef I1 (instanceRef XLXI_1_XLXI_12_XLXI_7))
+ (portRef O (instanceRef XLXI_1_XLXI_12_XLXI_1))
+ )
+ )
+ (net (rename XLXI_2_XLXI_2_XLXN_2 "XLXI_2/XLXI_2/XLXN_2")
+ (joined
+ (portRef I1 (instanceRef XLXI_2_XLXI_2_XLXI_4))
+ (portRef O (instanceRef XLXI_2_XLXI_2_XLXI_2))
+ )
+ )
+ (net (rename XLXI_2_XLXI_2_XLXN_7 "XLXI_2/XLXI_2/XLXN_7")
+ (joined
+ (portRef O (instanceRef XLXI_2_XLXI_2_XLXI_7))
+ (portRef I1 (instanceRef XLXI_2_XLXI_2_XLXI_3))
+ )
+ )
+ (net (rename XLXI_2_XLXI_2_XLXN_5 "XLXI_2/XLXI_2/XLXN_5")
+ (joined
+ (portRef I1 (instanceRef XLXI_2_XLXI_2_XLXI_2))
+ (portRef O (instanceRef XLXI_2_XLXI_2_XLXI_5))
+ )
+ )
+ (net (rename XLXI_2_XLXI_2_XLXN_1 "XLXI_2/XLXI_2/XLXN_1")
+ (joined
+ (portRef I2 (instanceRef XLXI_2_XLXI_2_XLXI_4))
+ (portRef O (instanceRef XLXI_2_XLXI_2_XLXI_1))
+ )
+ )
+ (net (rename XLXI_2_XLXI_2_XLXN_6 "XLXI_2/XLXI_2/XLXN_6")
+ (joined
+ (portRef I0 (instanceRef XLXI_2_XLXI_2_XLXI_2))
+ (portRef O (instanceRef XLXI_2_XLXI_2_XLXI_6))
+ )
+ )
+ (net (rename XLXI_2_XLXI_2_XLXN_3 "XLXI_2/XLXI_2/XLXN_3")
+ (joined
+ (portRef I0 (instanceRef XLXI_2_XLXI_2_XLXI_4))
+ (portRef O (instanceRef XLXI_2_XLXI_2_XLXI_3))
+ )
+ )
+ (net (rename XLXI_2_XLXI_1_XLXN_2 "XLXI_2/XLXI_1/XLXN_2")
+ (joined
+ (portRef I1 (instanceRef XLXI_2_XLXI_1_XLXI_4))
+ (portRef O (instanceRef XLXI_2_XLXI_1_XLXI_2))
+ )
+ )
+ (net (rename XLXI_2_XLXI_1_XLXN_7 "XLXI_2/XLXI_1/XLXN_7")
+ (joined
+ (portRef O (instanceRef XLXI_2_XLXI_1_XLXI_7))
+ (portRef I1 (instanceRef XLXI_2_XLXI_1_XLXI_3))
+ )
+ )
+ (net (rename XLXI_2_XLXI_1_XLXN_5 "XLXI_2/XLXI_1/XLXN_5")
+ (joined
+ (portRef I1 (instanceRef XLXI_2_XLXI_1_XLXI_2))
+ (portRef O (instanceRef XLXI_2_XLXI_1_XLXI_5))
+ )
+ )
+ (net (rename XLXI_2_XLXI_1_XLXN_1 "XLXI_2/XLXI_1/XLXN_1")
+ (joined
+ (portRef I2 (instanceRef XLXI_2_XLXI_1_XLXI_4))
+ (portRef O (instanceRef XLXI_2_XLXI_1_XLXI_1))
+ )
+ )
+ (net (rename XLXI_2_XLXI_1_XLXN_6 "XLXI_2/XLXI_1/XLXN_6")
+ (joined
+ (portRef I0 (instanceRef XLXI_2_XLXI_1_XLXI_2))
+ (portRef O (instanceRef XLXI_2_XLXI_1_XLXI_6))
+ )
+ )
+ (net (rename XLXI_2_XLXI_1_XLXN_3 "XLXI_2/XLXI_1/XLXN_3")
+ (joined
+ (portRef I0 (instanceRef XLXI_2_XLXI_1_XLXI_4))
+ (portRef O (instanceRef XLXI_2_XLXI_1_XLXI_3))
+ )
+ )
+ (net (rename XLXI_2_XLXI_3_XLXN_51 "XLXI_2/XLXI_3/XLXN_51")
+ (joined
+ (portRef O (instanceRef XLXI_2_XLXI_3_XLXI_20))
+ (portRef I3 (instanceRef XLXI_2_XLXI_3_XLXI_18))
+ )
+ )
+ (net (rename XLXI_2_XLXI_3_XLXN_23 "XLXI_2/XLXI_3/XLXN_23")
+ (joined
+ (portRef O (instanceRef XLXI_2_XLXI_3_XLXI_15))
+ (portRef I3 (instanceRef XLXI_2_XLXI_3_XLXI_11))
+ )
+ )
+ (net (rename XLXI_2_XLXI_3_XLXN_2 "XLXI_2/XLXI_3/XLXN_2")
+ (joined
+ (portRef I3 (instanceRef XLXI_2_XLXI_3_XLXI_22))
+ (portRef O (instanceRef XLXI_2_XLXI_3_XLXI_2))
+ )
+ )
+ (net (rename XLXI_2_XLXI_3_XLXN_50 "XLXI_2/XLXI_3/XLXN_50")
+ (joined
+ (portRef O (instanceRef XLXI_2_XLXI_3_XLXI_19))
+ (portRef I2 (instanceRef XLXI_2_XLXI_3_XLXI_18))
+ )
+ )
+ (net (rename XLXI_2_XLXI_3_XLXN_7 "XLXI_2/XLXI_3/XLXN_7")
+ (joined
+ (portRef O (instanceRef XLXI_2_XLXI_3_XLXI_7))
+ (portRef I1 (instanceRef XLXI_2_XLXI_3_XLXI_3))
+ )
+ )
+ (net (rename XLXI_2_XLXI_3_XLXN_56 "XLXI_2/XLXI_3/XLXN_56")
+ (joined
+ (portRef I1 (instanceRef XLXI_2_XLXI_3_XLXI_22))
+ (portRef O (instanceRef XLXI_2_XLXI_3_XLXI_18))
+ )
+ )
+ (net (rename XLXI_2_XLXI_3_XLXN_24 "XLXI_2/XLXI_3/XLXN_24")
+ (joined
+ (portRef O (instanceRef XLXI_2_XLXI_3_XLXI_16))
+ (portRef I1 (instanceRef XLXI_2_XLXI_3_XLXI_11))
+ )
+ )
+ (net (rename XLXI_2_XLXI_3_XLXN_5 "XLXI_2/XLXI_3/XLXN_5")
+ (joined
+ (portRef I1 (instanceRef XLXI_2_XLXI_3_XLXI_2))
+ (portRef O (instanceRef XLXI_2_XLXI_3_XLXI_5))
+ )
+ )
+ (net (rename XLXI_2_XLXI_3_XLXN_55 "XLXI_2/XLXI_3/XLXN_55")
+ (joined
+ (portRef I4 (instanceRef XLXI_2_XLXI_3_XLXI_22))
+ (portRef O (instanceRef XLXI_2_XLXI_3_XLXI_1))
+ )
+ )
+ (net (rename XLXI_2_XLXI_3_XLXN_54 "XLXI_2/XLXI_3/XLXN_54")
+ (joined
+ (portRef I0 (instanceRef XLXI_2_XLXI_3_XLXI_18))
+ (portRef O (instanceRef XLXI_2_XLXI_3_XLXI_21))
+ )
+ )
+ (net (rename XLXI_2_XLXI_3_XLXN_57 "XLXI_2/XLXI_3/XLXN_57")
+ (joined
+ (portRef I0 (instanceRef XLXI_2_XLXI_3_XLXI_22))
+ (portRef O (instanceRef XLXI_2_XLXI_3_XLXI_11))
+ )
+ )
+ (net (rename XLXI_2_XLXI_3_XLXN_6 "XLXI_2/XLXI_3/XLXN_6")
+ (joined
+ (portRef I0 (instanceRef XLXI_2_XLXI_3_XLXI_2))
+ (portRef O (instanceRef XLXI_2_XLXI_3_XLXI_6))
+ )
+ )
+ (net (rename XLXI_2_XLXI_3_XLXN_3 "XLXI_2/XLXI_3/XLXN_3")
+ (joined
+ (portRef I2 (instanceRef XLXI_2_XLXI_3_XLXI_22))
+ (portRef O (instanceRef XLXI_2_XLXI_3_XLXI_3))
+ )
+ )
+ (net (rename XLXI_3_XLXI_8_XLXN_17 "XLXI_3/XLXI_8/XLXN_17")
+ (joined
+ (portRef O (instanceRef XLXI_3_XLXI_8_XLXI_8))
+ (portRef I0 (instanceRef XLXI_3_XLXI_8_XLXI_12))
+ )
+ )
+ (net (rename XLXI_3_XLXI_8_XLXN_15 "XLXI_3/XLXI_8/XLXN_15")
+ (joined
+ (portRef I1 (instanceRef XLXI_3_XLXI_8_XLXI_8))
+ (portRef O (instanceRef XLXI_3_XLXI_8_XLXI_10))
+ )
+ )
+ (net (rename XLXI_3_XLXI_8_XLXN_14 "XLXI_3/XLXI_8/XLXN_14")
+ (joined
+ (portRef I2 (instanceRef XLXI_3_XLXI_8_XLXI_8))
+ (portRef O (instanceRef XLXI_3_XLXI_8_XLXI_9))
+ )
+ )
+ (net (rename XLXI_3_XLXI_9_XLXN_3 "XLXI_3/XLXI_9/XLXN_3")
+ (joined
+ (portRef I0 (instanceRef XLXI_3_XLXI_9_XLXI_4))
+ (portRef O (instanceRef XLXI_3_XLXI_9_XLXI_3))
+ )
+ )
+ (net (rename XLXI_3_XLXI_9_XLXN_4 "XLXI_3/XLXI_9/XLXN_4")
+ (joined
+ (portRef I0 (instanceRef XLXI_3_XLXI_9_XLXI_3))
+ (portRef O (instanceRef XLXI_3_XLXI_9_XLXI_5))
+ )
+ )
+ (net (rename XLXI_3_XLXI_9_XLXN_5 "XLXI_3/XLXI_9/XLXN_5")
+ (joined
+ (portRef I1 (instanceRef XLXI_3_XLXI_9_XLXI_3))
+ (portRef O (instanceRef XLXI_3_XLXI_9_XLXI_6))
+ (portRef I0 (instanceRef XLXI_3_XLXI_9_XLXI_2))
+ )
+ )
+ (net (rename XLXI_3_XLXI_9_XLXN_2 "XLXI_3/XLXI_9/XLXN_2")
+ (joined
+ (portRef I2 (instanceRef XLXI_3_XLXI_9_XLXI_4))
+ (portRef O (instanceRef XLXI_3_XLXI_9_XLXI_1))
+ )
+ )
+ (net (rename XLXI_3_XLXI_9_XLXN_6 "XLXI_3/XLXI_9/XLXN_6")
+ (joined
+ (portRef I1 (instanceRef XLXI_3_XLXI_9_XLXI_1))
+ (portRef O (instanceRef XLXI_3_XLXI_9_XLXI_7))
+ )
+ )
+ (net (rename XLXI_3_XLXI_9_XLXN_1 "XLXI_3/XLXI_9/XLXN_1")
+ (joined
+ (portRef I1 (instanceRef XLXI_3_XLXI_9_XLXI_4))
+ (portRef O (instanceRef XLXI_3_XLXI_9_XLXI_2))
+ )
+ )
+ (net (rename XLXI_3_XLXI_10_XLXN_35 "XLXI_3/XLXI_10/XLXN_35")
+ (joined
+ (portRef I3 (instanceRef XLXI_3_XLXI_10_XLXI_8))
+ (portRef O (instanceRef XLXI_3_XLXI_10_XLXI_9))
+ )
+ )
+ (net (rename XLXI_3_XLXI_10_XLXN_37 "XLXI_3/XLXI_10/XLXN_37")
+ (joined
+ (portRef I0 (instanceRef XLXI_3_XLXI_10_XLXI_8))
+ (portRef O (instanceRef XLXI_3_XLXI_10_XLXI_15))
+ )
+ )
+ (net (rename XLXI_3_XLXI_10_XLXN_44 "XLXI_3/XLXI_10/XLXN_44")
+ (joined
+ (portRef I0 (instanceRef XLXI_3_XLXI_10_XLXI_9))
+ (portRef O (instanceRef XLXI_3_XLXI_10_XLXI_14))
+ (portRef I1 (instanceRef XLXI_3_XLXI_10_XLXI_10))
+ (portRef I1 (instanceRef XLXI_3_XLXI_10_XLXI_11))
+ )
+ )
+ (net (rename XLXI_3_XLXI_10_XLXN_49 "XLXI_3/XLXI_10/XLXN_49")
+ (joined
+ (portRef I1 (instanceRef XLXI_3_XLXI_10_XLXI_15))
+ (portRef O (instanceRef XLXI_3_XLXI_10_XLXI_16))
+ )
+ )
+ (net (rename XLXI_3_XLXI_10_XLXN_41 "XLXI_3/XLXI_10/XLXN_41")
+ (joined
+ (portRef I1 (instanceRef XLXI_3_XLXI_10_XLXI_8))
+ (portRef O (instanceRef XLXI_3_XLXI_10_XLXI_10))
+ )
+ )
+ (net (rename XLXI_3_XLXI_10_XLXN_47 "XLXI_3/XLXI_10/XLXN_47")
+ (joined
+ (portRef I0 (instanceRef XLXI_3_XLXI_10_XLXI_15))
+ (portRef O (instanceRef XLXI_3_XLXI_10_XLXI_17))
+ )
+ )
+ (net (rename XLXI_3_XLXI_10_XLXN_40 "XLXI_3/XLXI_10/XLXN_40")
+ (joined
+ (portRef I2 (instanceRef XLXI_3_XLXI_10_XLXI_8))
+ (portRef O (instanceRef XLXI_3_XLXI_10_XLXI_11))
+ )
+ )
+ (net (rename XLXI_3_XLXI_12_XLXN_10 "XLXI_3/XLXI_12/XLXN_10")
+ (joined
+ (portRef I1 (instanceRef XLXI_3_XLXI_12_XLXI_16))
+ (portRef O (instanceRef XLXI_3_XLXI_12_XLXI_15))
+ )
+ )
+ (net (rename XLXI_3_XLXI_12_XLXN_8 "XLXI_3/XLXI_12/XLXN_8")
+ (joined
+ (portRef I0 (instanceRef XLXI_3_XLXI_12_XLXI_16))
+ (portRef O (instanceRef XLXI_3_XLXI_12_XLXI_14))
+ )
+ )
+ (net (rename XLXI_2_XLXI_4_XLXN_1 "XLXI_2/XLXI_4/XLXN_1")
+ (joined
+ (portRef I0 (instanceRef XLXI_2_XLXI_4_XLXI_2))
+ (portRef O (instanceRef XLXI_2_XLXI_4_XLXI_14))
+ )
+ )
+ (net (rename XLXI_2_XLXI_4_XLXN_14 "XLXI_2/XLXI_4/XLXN_14")
+ (joined
+ (portRef O (instanceRef XLXI_2_XLXI_4_XLXI_16))
+ (portRef I0 (instanceRef XLXI_2_XLXI_4_XLXI_14))
+ )
+ )
+ (net (rename XLXI_2_XLXI_4_XLXN_27 "XLXI_2/XLXI_4/XLXN_27")
+ (joined
+ (portRef I2 (instanceRef XLXI_2_XLXI_4_XLXI_11))
+ (portRef O (instanceRef XLXI_2_XLXI_4_XLXI_12))
+ )
+ )
+ (net (rename XLXI_2_XLXI_4_XLXN_4 "XLXI_2/XLXI_4/XLXN_4")
+ (joined
+ (portRef O (instanceRef XLXI_2_XLXI_4_XLXI_2))
+ (portRef I0 (instanceRef XLXI_2_XLXI_4_XLXI_4))
+ )
+ )
+ (net (rename XLXI_2_XLXI_4_XLXN_28 "XLXI_2/XLXI_4/XLXN_28")
+ (joined
+ (portRef I1 (instanceRef XLXI_2_XLXI_4_XLXI_11))
+ (portRef O (instanceRef XLXI_2_XLXI_4_XLXI_13))
+ )
+ )
+ (net (rename XLXI_2_XLXI_4_XLXN_15 "XLXI_2/XLXI_4/XLXN_15")
+ (joined
+ (portRef O (instanceRef XLXI_2_XLXI_4_XLXI_9))
+ (portRef I1 (instanceRef XLXI_2_XLXI_4_XLXI_16))
+ )
+ )
+ (net (rename XLXI_2_XLXI_4_XLXN_12 "XLXI_2/XLXI_4/XLXN_12")
+ (joined
+ (portRef O (instanceRef XLXI_2_XLXI_4_XLXI_15))
+ (portRef I1 (instanceRef XLXI_2_XLXI_4_XLXI_14))
+ )
+ )
+ (net (rename XLXI_2_XLXI_4_XLXN_3 "XLXI_2/XLXI_4/XLXN_3")
+ (joined
+ (portRef O (instanceRef XLXI_2_XLXI_4_XLXI_11))
+ (portRef I1 (instanceRef XLXI_2_XLXI_4_XLXI_4))
+ )
+ )
+ (net (rename XLXI_2_XLXI_4_XLXN_16 "XLXI_2/XLXI_4/XLXN_16")
+ (joined
+ (portRef O (instanceRef XLXI_2_XLXI_4_XLXI_10))
+ (portRef I0 (instanceRef XLXI_2_XLXI_4_XLXI_16))
+ )
+ )
+ (net (rename XLXI_9_XLXN_158 "XLXI_9/XLXN_158")
+ (joined
+ (portRef O (instanceRef XLXI_9_XLXI_53))
+ (portRef I (instanceRef XLXI_9_XLXI_68))
+ )
+ )
+ (net (rename XLXI_9_XLXN_131 "XLXI_9/XLXN_131")
+ (joined
+ (portRef I0 (instanceRef XLXI_9_XLXI_58))
+ (portRef O (instanceRef XLXI_9_XLXI_57))
+ )
+ )
+ (net (rename XLXI_9_XLXN_92 "XLXI_9/XLXN_92")
+ (joined
+ (portRef I2 (instanceRef XLXI_9_XLXI_41))
+ (portRef O (instanceRef XLXI_9_XLXI_43))
+ )
+ )
+ (net (rename XLXI_9_XLXN_156 "XLXI_9/XLXN_156")
+ (joined
+ (portRef O (instanceRef XLXI_9_XLXI_52))
+ (portRef I (instanceRef XLXI_9_XLXI_69))
+ )
+ )
+ (net (rename XLXI_9_XLXN_126 "XLXI_9/XLXN_126")
+ (joined
+ (portRef O (instanceRef XLXI_9_XLXI_49))
+ (portRef I2 (instanceRef XLXI_9_XLXI_52))
+ (portRef I0 (instanceRef XLXI_9_XLXI_53))
+ )
+ )
+ (net (rename XLXI_9_XLXN_93 "XLXI_9/XLXN_93")
+ (joined
+ (portRef I1 (instanceRef XLXI_9_XLXI_41))
+ (portRef O (instanceRef XLXI_9_XLXI_44))
+ )
+ )
+ (net (rename XLXI_9_XLXN_63 "XLXI_9/XLXN_63")
+ (joined
+ (portRef I2 (instanceRef XLXI_9_XLXI_34))
+ (portRef O (instanceRef XLXI_9_XLXI_32))
+ )
+ )
+ (net (rename XLXI_9_XLXN_162 "XLXI_9/XLXN_162")
+ (joined
+ (portRef O (instanceRef XLXI_9_XLXI_60))
+ (portRef I (instanceRef XLXI_9_XLXI_71))
+ )
+ )
+ (net (rename XLXI_9_XLXN_160 "XLXI_9/XLXN_160")
+ (joined
+ (portRef O (instanceRef XLXI_9_XLXI_58))
+ (portRef I (instanceRef XLXI_9_XLXI_70))
+ )
+ )
+ (net (rename XLXI_9_XLXN_151 "XLXI_9/XLXN_151")
+ (joined
+ (portRef O (instanceRef XLXI_9_XLXI_41))
+ (portRef I (instanceRef XLXI_9_XLXI_66))
+ )
+ )
+ (net (rename XLXI_9_XLXN_165 "XLXI_9/XLXN_165")
+ (joined
+ (portRef O (instanceRef XLXI_9_XLXI_72))
+ (portRef I (instanceRef XLXI_9_XLXI_73))
+ )
+ )
+ (net (rename XLXI_9_XLXN_149 "XLXI_9/XLXN_149")
+ (joined
+ (portRef O (instanceRef XLXI_9_XLXI_34))
+ (portRef I (instanceRef XLXI_9_XLXI_65))
+ )
+ )
+ (net (rename XLXI_9_XLXN_155 "XLXI_9/XLXN_155")
+ (joined
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+ (portRef I (instanceRef XLXI_9_XLXI_67))
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+ (joined
+ (portRef I0 (instanceRef XLXI_9_XLXI_64))
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+ (portRef I0 (instanceRef XLXI_9_XLXI_43))
+ (portRef I0 (instanceRef XLXI_9_XLXI_57))
+ )
+ )
+ (net (rename XLXI_9_XLXN_147 "XLXI_9/XLXN_147")
+ (joined
+ (portRef O (instanceRef XLXI_9_XLXI_63))
+ (portRef I1 (instanceRef XLXI_9_XLXI_60))
+ )
+ )
+ (net (rename XLXI_9_XLXN_146 "XLXI_9/XLXN_146")
+ (joined
+ (portRef O (instanceRef XLXI_9_XLXI_62))
+ (portRef I2 (instanceRef XLXI_9_XLXI_60))
+ )
+ )
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+ (joined
+ (portRef O (instanceRef XLXI_9_XLXI_50))
+ (portRef I1 (instanceRef XLXI_9_XLXI_52))
+ )
+ )
+ (net (rename XLXI_9_XLXN_125 "XLXI_9/XLXN_125")
+ (joined
+ (portRef O (instanceRef XLXI_9_XLXI_48))
+ (portRef I3 (instanceRef XLXI_9_XLXI_52))
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+ )
+ )
+ (net (rename XLXI_9_XLXN_94 "XLXI_9/XLXN_94")
+ (joined
+ (portRef O (instanceRef XLXI_9_XLXI_45))
+ (portRef I0 (instanceRef XLXI_9_XLXI_41))
+ )
+ )
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+ (joined
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+ (portRef I1 (instanceRef XLXI_9_XLXI_44))
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+ )
+ )
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+ (joined
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+ )
+ )
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+ (joined
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+ )
+ )
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+ (joined
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+ )
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+ )
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+ )
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+ (portRef I0 (instanceRef XLXI_9_XLXI_44))
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+ )
+ )
+ (net (rename XLXI_9_XLXN_61 "XLXI_9/XLXN_61")
+ (joined
+ (portRef O (instanceRef XLXI_9_XLXI_30))
+ (portRef I4 (instanceRef XLXI_9_XLXI_34))
+ )
+ )
+ (net (rename XLXI_9_XLXN_148 "XLXI_9/XLXN_148")
+ (joined
+ (portRef O (instanceRef XLXI_9_XLXI_64))
+ (portRef I0 (instanceRef XLXI_9_XLXI_60))
+ )
+ )
+ (net (rename XLXI_9_XLXN_129 "XLXI_9/XLXN_129")
+ (joined
+ (portRef O (instanceRef XLXI_9_XLXI_55))
+ (portRef I2 (instanceRef XLXI_9_XLXI_58))
+ )
+ )
+ (net (rename XLXI_9_XLXN_105 "XLXI_9/XLXN_105")
+ (joined
+ (portRef O (instanceRef XLXI_9_XLXI_46))
+ (portRef I2 (instanceRef XLXI_9_XLXI_47))
+ )
+ )
+ (net (rename XLXI_9_XLXN_91 "XLXI_9/XLXN_91")
+ (joined
+ (portRef O (instanceRef XLXI_9_XLXI_42))
+ (portRef I3 (instanceRef XLXI_9_XLXI_41))
+ )
+ )
+ (net (rename XLXI_9_A_BAR "XLXI_9/A_BAR")
+ (joined
+ (portRef O (instanceRef XLXI_9_XLXI_37))
+ (portRef I2 (instanceRef XLXI_9_XLXI_54))
+ (portRef I2 (instanceRef XLXI_9_XLXI_56))
+ (portRef I0 (instanceRef XLXI_9_XLXI_31))
+ (portRef I0 (instanceRef XLXI_9_XLXI_45))
+ (portRef I (instanceRef XLXI_9_XLXI_72))
+ )
+ )
+ (net (rename XLXI_9_XLXN_65 "XLXI_9/XLXN_65")
+ (joined
+ (portRef O (instanceRef XLXI_9_XLXI_35))
+ (portRef I0 (instanceRef XLXI_9_XLXI_34))
+ )
+ )
+ (net A
+ (joined
+ (portRef A)
+ (portRef I (instanceRef A_IBUF_renamed_0))
+ )
+ )
+ (net B
+ (joined
+ (portRef B)
+ (portRef I (instanceRef B_IBUF_renamed_1))
+ )
+ )
+ (net C
+ (joined
+ (portRef C)
+ (portRef I (instanceRef C_IBUF_renamed_2))
+ )
+ )
+ (net D
+ (joined
+ (portRef D)
+ (portRef I (instanceRef D_IBUF_renamed_3))
+ )
+ )
+ (net S0
+ (joined
+ (portRef S0)
+ (portRef I (instanceRef S0_IBUF_renamed_4))
+ )
+ )
+ (net S1
+ (joined
+ (portRef S1)
+ (portRef I (instanceRef S1_IBUF_renamed_5))
+ )
+ )
+ (net AN0
+ (joined
+ (portRef AN0)
+ (portRef O (instanceRef AN0_OBUF_renamed_6))
+ )
+ )
+ (net AN1
+ (joined
+ (portRef AN1)
+ (portRef O (instanceRef AN1_OBUF_renamed_7))
+ )
+ )
+ (net AN2
+ (joined
+ (portRef AN2)
+ (portRef O (instanceRef AN2_OBUF_renamed_8))
+ )
+ )
+ (net AN3
+ (joined
+ (portRef AN3)
+ (portRef O (instanceRef AN3_OBUF_renamed_9))
+ )
+ )
+ (net a_out
+ (joined
+ (portRef a_out)
+ (portRef O (instanceRef a_out_OBUF_renamed_10))
+ )
+ )
+ (net b_out
+ (joined
+ (portRef b_out)
+ (portRef O (instanceRef b_out_OBUF_renamed_11))
+ )
+ )
+ (net c_out
+ (joined
+ (portRef c_out)
+ (portRef O (instanceRef c_out_OBUF_renamed_12))
+ )
+ )
+ (net d_out
+ (joined
+ (portRef d_out)
+ (portRef O (instanceRef d_out_OBUF_renamed_13))
+ )
+ )
+ (net e_out
+ (joined
+ (portRef e_out)
+ (portRef O (instanceRef e_out_OBUF_renamed_14))
+ )
+ )
+ (net f_out
+ (joined
+ (portRef f_out)
+ (portRef O (instanceRef f_out_OBUF_renamed_15))
+ )
+ )
+ (net g_out
+ (joined
+ (portRef g_out)
+ (portRef O (instanceRef g_out_OBUF_renamed_16))
+ )
+ )
+ (net sign
+ (joined
+ (portRef sign)
+ (portRef O (instanceRef sign_OBUF_renamed_17))
+ )
+ )
+ )
+ )
+ )
+ )
+
+ (design ALU
+ (cellRef ALU
+ (libraryRef ALU_lib)
+ )
+ (property PART (string "xc6slx16-3-csg324") (owner "Xilinx"))
+ )
+)
+
diff --git a/planAhead_run_2/lab1.data/constrs_1/fileset.xml b/planAhead_run_2/lab1.data/constrs_1/fileset.xml
new file mode 100755
index 0000000..80984cf
--- /dev/null
+++ b/planAhead_run_2/lab1.data/constrs_1/fileset.xml
@@ -0,0 +1,25 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<DARoots Version="1"
+ Minor="19">
+ <FileSet Name="constrs_1"
+ Type="Constrs"
+ RelSrcDir="$PSRCDIR/constrs_1">
+ <Filter Type="Constrs"/>
+ <File Path="$PPRDIR/../ALU.ucf">
+ <FileInfo>
+ <Attr Name="UsedInSynthesis"
+ Val="1"/>
+ <Attr Name="UsedInImplementation"
+ Val="1"/>
+ <Attr Name="UsedInSimulation"
+ Val="1"/>
+ </FileInfo>
+ </File>
+ <Config>
+ <Option Name="TargetConstrsFile"
+ Val="$PPRDIR/../ALU.ucf"/>
+ <Option Name="ConstrsType"
+ Val="UCF"/>
+ </Config>
+ </FileSet>
+</DARoots>
diff --git a/planAhead_run_2/lab1.data/runs/impl_1.psg b/planAhead_run_2/lab1.data/runs/impl_1.psg
new file mode 100755
index 0000000..43196a2
--- /dev/null
+++ b/planAhead_run_2/lab1.data/runs/impl_1.psg
@@ -0,0 +1,18 @@
+<?xml version="1.0"?>
+<Strategy Version="1" Minor="2">
+ <StratHandle Name="ISE Defaults" Flow="ISE13">
+ <Desc>ISE Defaults, including packing registers in IOs off</Desc>
+ </StratHandle>
+ <Step Id="ngdbuild">
+ </Step>
+ <Step Id="map">
+ <Option Id="FFPackEnum">3</Option>
+ </Step>
+ <Step Id="par">
+ </Step>
+ <Step Id="trce">
+ </Step>
+ <Step Id="xdl">
+ </Step>
+</Strategy>
+
diff --git a/planAhead_run_2/lab1.data/runs/runs.xml b/planAhead_run_2/lab1.data/runs/runs.xml
new file mode 100755
index 0000000..2651a01
--- /dev/null
+++ b/planAhead_run_2/lab1.data/runs/runs.xml
@@ -0,0 +1,5 @@
+<?xml version="1.0"?>
+<Runs Version="1" Minor="8">
+ <Run Id="impl_1" Type="Ft2:EntireDesign" SrcSet="sources_1" Part="xc6slx16csg324-3" ConstrsSet="constrs_1" State="current"/>
+</Runs>
+
diff --git a/planAhead_run_2/lab1.data/sources_1/fileset.xml b/planAhead_run_2/lab1.data/sources_1/fileset.xml
new file mode 100755
index 0000000..ff57e87
--- /dev/null
+++ b/planAhead_run_2/lab1.data/sources_1/fileset.xml
@@ -0,0 +1,29 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<DARoots Version="1"
+ Minor="19">
+ <FileSet Name="sources_1"
+ Type="DesignSrcs"
+ RelSrcDir="$PSRCDIR/sources_1">
+ <Filter Type="EDIFSrcs"/>
+ <File Path="$PPRDIR/../ALU.ngc">
+ <FileInfo>
+ <Attr Name="UsedInSynthesis"
+ Val="1"/>
+ <Attr Name="UsedInImplementation"
+ Val="1"/>
+ <Attr Name="UsedInSimulation"
+ Val="1"/>
+ </FileInfo>
+ </File>
+ <Config>
+ <Option Name="DesignMode"
+ Val="GateLvl"/>
+ <Option Name="GateLvlMode"
+ Val="EDIF"/>
+ <Option Name="TopModule"
+ Val="ALU"/>
+ <Option Name="TopFile"
+ Val="$PPRDIR/../ALU.ngc"/>
+ </Config>
+ </FileSet>
+</DARoots>
diff --git a/planAhead_run_2/lab1.data/wt/webtalk_pa.xml b/planAhead_run_2/lab1.data/wt/webtalk_pa.xml
new file mode 100755
index 0000000..2bed019
--- /dev/null
+++ b/planAhead_run_2/lab1.data/wt/webtalk_pa.xml
@@ -0,0 +1,26 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<document>
+<!--The data in this file is primarily intended for consumption by Xilinx tools.
+The structure and the elements are likely to change over the next few releases.
+This means code written to parse this file will need to be revisited each subsequent release.-->
+<application name="pa" timeStamp="Thu Feb 16 20:00:26 2012">
+<section name="Project Information" visible="false">
+<property name="ProjectID" value="98952ffb65684da08e4e1169ac26bbac" type="ProjectID"/>
+<property name="ProjectIteration" value="1" type="ProjectIteration"/>
+</section>
+<section name="PlanAhead Usage" visible="true">
+<item name="Project Data">
+<property name="SrcSetCount" value="1" type="SrcSetCount"/>
+<property name="ConstraintSetCount" value="1" type="ConstraintSetCount"/>
+<property name="DesignMode" value="GateLvl" type="DesignMode"/>
+<property name="ImplStrategy" value="ISE Defaults" type="ImplStrategy"/>
+</item>
+<item name="Other">
+<property name="GuiMode" value="0" type="GuiMode"/>
+<property name="BatchMode" value="0" type="BatchMode"/>
+<property name="TclMode" value="0" type="TclMode"/>
+<property name="ISEMode" value="14" type="ISEMode"/>
+</item>
+</section>
+</application>
+</document>
diff --git a/planAhead_run_2/lab1.ppr b/planAhead_run_2/lab1.ppr
new file mode 100755
index 0000000..6081e20
--- /dev/null
+++ b/planAhead_run_2/lab1.ppr
@@ -0,0 +1,14 @@
+<?xml version="1.0"?>
+<Project Version="4" Minor="27">
+ <FileSet Dir="sources_1" File="fileset.xml"/>
+ <FileSet Dir="constrs_1" File="fileset.xml"/>
+ <RunSet Dir="runs" File="runs.xml"/>
+ <DefaultLaunch Dir="$PRUNDIR"/>
+ <DefaultPromote Dir="$PROMOTEDIR"/>
+ <Config>
+ <Option Name="Part" Val="xc6slx16csg324-3"/>
+ <Option Name="TargetLanguage" Val="Verilog"/>
+ <Option Name="SourceMgmtMode" Val="All"/>
+ </Config>
+</Project>
+
diff --git a/planAhead_run_2/planAhead.jou b/planAhead_run_2/planAhead.jou
new file mode 100755
index 0000000..2ada6d2
--- /dev/null
+++ b/planAhead_run_2/planAhead.jou
@@ -0,0 +1,18 @@
+#-----------------------------------------------------------
+# PlanAhead v13.3 (64-bit)
+# Build 147507 by hdbuild on Tue Oct 4 19:13:50 MDT 2011
+# Start of session at: Thu Feb 16 18:59:46 2012
+# Process ID: 3164
+# Log file: X:/My Documents/ec311/ec311-lab1/planAhead_run_2/planAhead.log
+# Journal file: X:/My Documents/ec311/ec311-lab1/planAhead_run_2/planAhead.jou
+#-----------------------------------------------------------
+start_gui
+source {X:/My Documents/ec311/ec311-lab1/pa.fromNetlist.tcl}
+refresh_design
+refresh_design
+refresh_design
+refresh_design
+refresh_design
+refresh_design
+exit
+stop_gui
diff --git a/planAhead_run_2/planAhead.log b/planAhead_run_2/planAhead.log
new file mode 100755
index 0000000..4c49347
--- /dev/null
+++ b/planAhead_run_2/planAhead.log
@@ -0,0 +1,198 @@
+#-----------------------------------------------------------
+# PlanAhead v13.3 (64-bit)
+# Build 147507 by hdbuild on Tue Oct 4 19:13:50 MDT 2011
+# Start of session at: Thu Feb 16 18:59:46 2012
+# Process ID: 3164
+# Log file: X:/My Documents/ec311/ec311-lab1/planAhead_run_2/planAhead.log
+# Journal file: X:/My Documents/ec311/ec311-lab1/planAhead_run_2/planAhead.jou
+#-----------------------------------------------------------
+INFO: [Common-78] Attempting to get a license: PlanAhead
+INFO: [Common-82] Got a license: PlanAhead
+INFO: [Device-25] Loading parts and site information from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts\arch.xmlParsing RTL primitives file [C:/Xilinx/13.3/ISE_DS/PlanAhead\parts\xilinx\rtl\prims\rtl_prims.xml]
+Finished parsing RTL primitives file [C:/Xilinx/13.3/ISE_DS/PlanAhead\parts\xilinx\rtl\prims\rtl_prims.xml]
+start_gui
+source {X:/My Documents/ec311/ec311-lab1/pa.fromNetlist.tcl}
+# create_project -name lab1 -dir "X:/My Documents/ec311/ec311-lab1/planAhead_run_2" -part xc6slx16csg324-3
+Parsing template File [C:/Xilinx/13.3/ISE_DS/ISE\data\projnav\templates\verilog.xml].
+Finished parsing template File [C:/Xilinx/13.3/ISE_DS/ISE\data\projnav\templates\verilog.xml].
+Parsing template File [C:/Xilinx/13.3/ISE_DS/ISE\data\projnav\templates\vhdl.xml].
+Finished parsing template File [C:/Xilinx/13.3/ISE_DS/ISE\data\projnav\templates\vhdl.xml].
+Parsing template File [C:/Xilinx/13.3/ISE_DS/ISE\data\projnav\templates\ucf.xml].
+Finished parsing template File [C:/Xilinx/13.3/ISE_DS/ISE\data\projnav\templates\ucf.xml].
+# set_property design_mode GateLvl [get_property srcset [current_run -impl]]
+# set_property edif_top_file "X:/My Documents/ec311/ec311-lab1/ALU.ngc" [ get_property srcset [ current_run ] ]
+# add_files -norecurse { {X:/My Documents/ec311/ec311-lab1} }
+# set_param project.pinAheadLayout yes
+# set_property target_constrs_file "ALU.ucf" [current_fileset -constrset]
+Adding file 'X:\My Documents\ec311\ec311-lab1\ALU.ucf' to fileset 'constrs_1'
+# add_files [list {ALU.ucf}] -fileset [get_property constrset [current_run]]
+# open_netlist_design
+Design is defaulting to srcset: sources_1
+Design is defaulting to constrset: constrs_1
+Design is defaulting to part: xc6slx16csg324-3
+Release 13.3 - ngc2edif O.76xd (nt64)
+Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
+Reading design ALU.ngc ...
+WARNING:NetListWriters:298 - No output is written to ALU.xncf, ignored.
+Processing design ...
+ Preping design's networks ...
+ Preping design's macros ...
+ finished :Prep
+Writing EDIF netlist file ALU.edif ...
+ngc2edif: Total memory usage is 91624 kilobytes
+
+Parsing EDIF File [.\planAhead_run_2\lab1.data\cache\ALU_ngc_c04f956c.edif]
+Finished Parsing EDIF File [.\planAhead_run_2\lab1.data\cache\ALU_ngc_c04f956c.edif]
+Loading clock regions from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts/xilinx/spartan6/spartan6lx/xc6slx16/ClockRegion.xml
+Loading clock buffers from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts/xilinx/spartan6/spartan6lx/xc6slx16/ClockBuffers.xml
+Loading package pin functions from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts\xilinx\spartan6/PinFunctions.xml...
+Loading package from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts/xilinx/spartan6/spartan6lx/xc6slx16/csg324/Package.xml
+Loading io standards from C:/Xilinx/13.3/ISE_DS/PlanAhead\./parts/xilinx/spartan6/IOStandards.xml
+Loading device configuration modes from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts\xilinx\spartan6/ConfigModes.xml
+Loading list of drcs for the architecture : C:/Xilinx/13.3/ISE_DS/PlanAhead\./parts/xilinx/spartan6/drc.xml
+Parsing UCF File [X:\My Documents\ec311\ec311-lab1\ALU.ucf]
+Finished Parsing UCF File [X:\My Documents\ec311\ec311-lab1\ALU.ucf]
+INFO: [PlanAhead-566] Unisim Transformation Summary:
+No Unisim elements were transformed.open_netlist_design: Time (s): 13.385w. Memory (MB): 744.074p 196.641g
+refresh_design
+Release 13.3 - ngc2edif O.76xd (nt64)
+Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
+Reading design ALU.ngc ...
+WARNING:NetListWriters:298 - No output is written to ALU.xncf, ignored.
+Processing design ...
+ Preping design's networks ...
+ Preping design's macros ...
+ finished :Prep
+Writing EDIF netlist file ALU.edif ...
+ngc2edif: Total memory usage is 91432 kilobytes
+
+Parsing EDIF File [.\planAhead_run_2\lab1.data\cache\ALU_ngc_c04f956c.edif]
+Finished Parsing EDIF File [.\planAhead_run_2\lab1.data\cache\ALU_ngc_c04f956c.edif]
+Loading clock regions from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts/xilinx/spartan6/spartan6lx/xc6slx16/ClockRegion.xml
+Loading clock buffers from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts/xilinx/spartan6/spartan6lx/xc6slx16/ClockBuffers.xml
+Loading package pin functions from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts\xilinx\spartan6/PinFunctions.xml...
+Loading package from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts/xilinx/spartan6/spartan6lx/xc6slx16/csg324/Package.xml
+Loading io standards from C:/Xilinx/13.3/ISE_DS/PlanAhead\./parts/xilinx/spartan6/IOStandards.xml
+Loading list of drcs for the architecture : C:/Xilinx/13.3/ISE_DS/PlanAhead\./parts/xilinx/spartan6/drc.xml
+Parsing UCF File [X:\My Documents\ec311\ec311-lab1\ALU.ucf]
+Finished Parsing UCF File [X:\My Documents\ec311\ec311-lab1\ALU.ucf]
+refresh_design: Time (s): 9.017w. Memory (MB): 778.047p 27.094g
+refresh_design
+Release 13.3 - ngc2edif O.76xd (nt64)
+Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
+Reading design ALU.ngc ...
+WARNING:NetListWriters:298 - No output is written to ALU.xncf, ignored.
+Processing design ...
+ Preping design's networks ...
+ Preping design's macros ...
+ finished :Prep
+Writing EDIF netlist file ALU.edif ...
+ngc2edif: Total memory usage is 91752 kilobytes
+
+Parsing EDIF File [.\planAhead_run_2\lab1.data\cache\ALU_ngc_c04f956c.edif]
+Finished Parsing EDIF File [.\planAhead_run_2\lab1.data\cache\ALU_ngc_c04f956c.edif]
+Loading clock regions from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts/xilinx/spartan6/spartan6lx/xc6slx16/ClockRegion.xml
+Loading clock buffers from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts/xilinx/spartan6/spartan6lx/xc6slx16/ClockBuffers.xml
+Loading package pin functions from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts\xilinx\spartan6/PinFunctions.xml...
+Loading package from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts/xilinx/spartan6/spartan6lx/xc6slx16/csg324/Package.xml
+Loading io standards from C:/Xilinx/13.3/ISE_DS/PlanAhead\./parts/xilinx/spartan6/IOStandards.xml
+Loading list of drcs for the architecture : C:/Xilinx/13.3/ISE_DS/PlanAhead\./parts/xilinx/spartan6/drc.xml
+Parsing UCF File [X:\My Documents\ec311\ec311-lab1\ALU.ucf]
+Finished Parsing UCF File [X:\My Documents\ec311\ec311-lab1\ALU.ucf]
+refresh_design: Time (s): 7.317w. Memory (MB): 783.742p 5.559g
+refresh_design
+Release 13.3 - ngc2edif O.76xd (nt64)
+Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
+Reading design ALU.ngc ...
+WARNING:NetListWriters:298 - No output is written to ALU.xncf, ignored.
+Processing design ...
+ Preping design's networks ...
+ Preping design's macros ...
+ finished :Prep
+Writing EDIF netlist file ALU.edif ...
+ngc2edif: Total memory usage is 91560 kilobytes
+
+Parsing EDIF File [.\planAhead_run_2\lab1.data\cache\ALU_ngc_c04f956c.edif]
+Finished Parsing EDIF File [.\planAhead_run_2\lab1.data\cache\ALU_ngc_c04f956c.edif]
+Loading clock regions from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts/xilinx/spartan6/spartan6lx/xc6slx16/ClockRegion.xml
+Loading clock buffers from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts/xilinx/spartan6/spartan6lx/xc6slx16/ClockBuffers.xml
+Loading package pin functions from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts\xilinx\spartan6/PinFunctions.xml...
+Loading package from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts/xilinx/spartan6/spartan6lx/xc6slx16/csg324/Package.xml
+Loading io standards from C:/Xilinx/13.3/ISE_DS/PlanAhead\./parts/xilinx/spartan6/IOStandards.xml
+Loading list of drcs for the architecture : C:/Xilinx/13.3/ISE_DS/PlanAhead\./parts/xilinx/spartan6/drc.xml
+Parsing UCF File [X:\My Documents\ec311\ec311-lab1\ALU.ucf]
+Finished Parsing UCF File [X:\My Documents\ec311\ec311-lab1\ALU.ucf]
+refresh_design: Time (s): 7.364w. Memory (MB): 786.453p 2.711g
+refresh_design
+Release 13.3 - ngc2edif O.76xd (nt64)
+Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
+Reading design ALU.ngc ...
+WARNING:NetListWriters:298 - No output is written to ALU.xncf, ignored.
+Processing design ...
+ Preping design's networks ...
+ Preping design's macros ...
+ finished :Prep
+Writing EDIF netlist file ALU.edif ...
+ngc2edif: Total memory usage is 91880 kilobytes
+
+Parsing EDIF File [.\planAhead_run_2\lab1.data\cache\ALU_ngc_c04f956c.edif]
+Finished Parsing EDIF File [.\planAhead_run_2\lab1.data\cache\ALU_ngc_c04f956c.edif]
+Loading clock regions from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts/xilinx/spartan6/spartan6lx/xc6slx16/ClockRegion.xml
+Loading clock buffers from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts/xilinx/spartan6/spartan6lx/xc6slx16/ClockBuffers.xml
+Loading package pin functions from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts\xilinx\spartan6/PinFunctions.xml...
+Loading package from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts/xilinx/spartan6/spartan6lx/xc6slx16/csg324/Package.xml
+Loading io standards from C:/Xilinx/13.3/ISE_DS/PlanAhead\./parts/xilinx/spartan6/IOStandards.xml
+Loading list of drcs for the architecture : C:/Xilinx/13.3/ISE_DS/PlanAhead\./parts/xilinx/spartan6/drc.xml
+Parsing UCF File [X:\My Documents\ec311\ec311-lab1\ALU.ucf]
+Finished Parsing UCF File [X:\My Documents\ec311\ec311-lab1\ALU.ucf]
+refresh_design: Time (s): 7.628w. Memory (MB): 805.910p 19.457g
+refresh_design
+Release 13.3 - ngc2edif O.76xd (nt64)
+Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
+Reading design ALU.ngc ...
+WARNING:NetListWriters:298 - No output is written to ALU.xncf, ignored.
+Processing design ...
+ Preping design's networks ...
+ Preping design's macros ...
+ finished :Prep
+Writing EDIF netlist file ALU.edif ...
+ngc2edif: Total memory usage is 91368 kilobytes
+
+Parsing EDIF File [.\planAhead_run_2\lab1.data\cache\ALU_ngc_c04f956c.edif]
+Finished Parsing EDIF File [.\planAhead_run_2\lab1.data\cache\ALU_ngc_c04f956c.edif]
+Loading clock regions from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts/xilinx/spartan6/spartan6lx/xc6slx16/ClockRegion.xml
+Loading clock buffers from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts/xilinx/spartan6/spartan6lx/xc6slx16/ClockBuffers.xml
+Loading package pin functions from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts\xilinx\spartan6/PinFunctions.xml...
+Loading package from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts/xilinx/spartan6/spartan6lx/xc6slx16/csg324/Package.xml
+Loading io standards from C:/Xilinx/13.3/ISE_DS/PlanAhead\./parts/xilinx/spartan6/IOStandards.xml
+Loading list of drcs for the architecture : C:/Xilinx/13.3/ISE_DS/PlanAhead\./parts/xilinx/spartan6/drc.xml
+Parsing UCF File [X:\My Documents\ec311\ec311-lab1\ALU.ucf]
+Finished Parsing UCF File [X:\My Documents\ec311\ec311-lab1\ALU.ucf]
+refresh_design: Time (s): 7.425w. Memory (MB): 807.293p 0.000g
+refresh_design
+Release 13.3 - ngc2edif O.76xd (nt64)
+Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
+Reading design ALU.ngc ...
+WARNING:NetListWriters:298 - No output is written to ALU.xncf, ignored.
+Processing design ...
+ Preping design's networks ...
+ Preping design's macros ...
+ finished :Prep
+Writing EDIF netlist file ALU.edif ...
+ngc2edif: Total memory usage is 91304 kilobytes
+
+Parsing EDIF File [.\planAhead_run_2\lab1.data\cache\ALU_ngc_c04f956c.edif]
+Finished Parsing EDIF File [.\planAhead_run_2\lab1.data\cache\ALU_ngc_c04f956c.edif]
+Loading clock regions from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts/xilinx/spartan6/spartan6lx/xc6slx16/ClockRegion.xml
+Loading clock buffers from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts/xilinx/spartan6/spartan6lx/xc6slx16/ClockBuffers.xml
+Loading package pin functions from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts\xilinx\spartan6/PinFunctions.xml...
+Loading package from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts/xilinx/spartan6/spartan6lx/xc6slx16/csg324/Package.xml
+Loading io standards from C:/Xilinx/13.3/ISE_DS/PlanAhead\./parts/xilinx/spartan6/IOStandards.xml
+Loading list of drcs for the architecture : C:/Xilinx/13.3/ISE_DS/PlanAhead\./parts/xilinx/spartan6/drc.xml
+Parsing UCF File [X:\My Documents\ec311\ec311-lab1\ALU.ucf]
+Finished Parsing UCF File [X:\My Documents\ec311\ec311-lab1\ALU.ucf]
+refresh_design: Time (s): 7.566w. Memory (MB): 807.293p 0.000g
+exit
+stop_gui
+INFO: [PlanAhead-261] Exiting PlanAhead...
+INFO: [Common-83] Releasing license: PlanAhead
diff --git a/planAhead_run_2/planAhead_run.log b/planAhead_run_2/planAhead_run.log
new file mode 100755
index 0000000..3809618
--- /dev/null
+++ b/planAhead_run_2/planAhead_run.log
@@ -0,0 +1,196 @@
+
+****** PlanAhead v13.3 (64-bit)
+ **** Build 147507 by hdbuild on Tue Oct 4 19:13:50 MDT 2011
+ ** Copyright 1986-1999, 2001-2011 Xilinx, Inc. All Rights Reserved.
+
+INFO: [Common-78] Attempting to get a license: PlanAhead
+INFO: [Common-82] Got a license: PlanAhead
+INFO: [Device-25] Loading parts and site information from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts\arch.xmlParsing RTL primitives file [C:/Xilinx/13.3/ISE_DS/PlanAhead\parts\xilinx\rtl\prims\rtl_prims.xml]
+Finished parsing RTL primitives file [C:/Xilinx/13.3/ISE_DS/PlanAhead\parts\xilinx\rtl\prims\rtl_prims.xml]
+start_gui
+starting gui ...
+source {X:/My Documents/ec311/ec311-lab1/pa.fromNetlist.tcl}
+# create_project -name lab1 -dir "X:/My Documents/ec311/ec311-lab1/planAhead_run_2" -part xc6slx16csg324-3
+Parsing template File [C:/Xilinx/13.3/ISE_DS/ISE\data\projnav\templates\verilog.xml].
+Finished parsing template File [C:/Xilinx/13.3/ISE_DS/ISE\data\projnav\templates\verilog.xml].
+Parsing template File [C:/Xilinx/13.3/ISE_DS/ISE\data\projnav\templates\vhdl.xml].
+Finished parsing template File [C:/Xilinx/13.3/ISE_DS/ISE\data\projnav\templates\vhdl.xml].
+Parsing template File [C:/Xilinx/13.3/ISE_DS/ISE\data\projnav\templates\ucf.xml].
+Finished parsing template File [C:/Xilinx/13.3/ISE_DS/ISE\data\projnav\templates\ucf.xml].
+# set_property design_mode GateLvl [get_property srcset [current_run -impl]]
+# set_property edif_top_file "X:/My Documents/ec311/ec311-lab1/ALU.ngc" [ get_property srcset [ current_run ] ]
+# add_files -norecurse { {X:/My Documents/ec311/ec311-lab1} }
+# set_param project.pinAheadLayout yes
+# set_property target_constrs_file "ALU.ucf" [current_fileset -constrset]
+Adding file 'X:\My Documents\ec311\ec311-lab1\ALU.ucf' to fileset 'constrs_1'
+# add_files [list {ALU.ucf}] -fileset [get_property constrset [current_run]]
+# open_netlist_design
+Design is defaulting to srcset: sources_1
+Design is defaulting to constrset: constrs_1
+Design is defaulting to part: xc6slx16csg324-3
+Release 13.3 - ngc2edif O.76xd (nt64)
+Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
+Reading design ALU.ngc ...
+WARNING:NetListWriters:298 - No output is written to ALU.xncf, ignored.
+Processing design ...
+ Preping design's networks ...
+ Preping design's macros ...
+ finished :Prep
+Writing EDIF netlist file ALU.edif ...
+ngc2edif: Total memory usage is 91624 kilobytes
+
+Parsing EDIF File [.\planAhead_run_2\lab1.data\cache\ALU_ngc_c04f956c.edif]
+Finished Parsing EDIF File [.\planAhead_run_2\lab1.data\cache\ALU_ngc_c04f956c.edif]
+Loading clock regions from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts/xilinx/spartan6/spartan6lx/xc6slx16/ClockRegion.xml
+Loading clock buffers from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts/xilinx/spartan6/spartan6lx/xc6slx16/ClockBuffers.xml
+Loading package pin functions from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts\xilinx\spartan6/PinFunctions.xml...
+Loading package from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts/xilinx/spartan6/spartan6lx/xc6slx16/csg324/Package.xml
+Loading io standards from C:/Xilinx/13.3/ISE_DS/PlanAhead\./parts/xilinx/spartan6/IOStandards.xml
+Loading device configuration modes from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts\xilinx\spartan6/ConfigModes.xml
+Loading list of drcs for the architecture : C:/Xilinx/13.3/ISE_DS/PlanAhead\./parts/xilinx/spartan6/drc.xml
+Parsing UCF File [X:\My Documents\ec311\ec311-lab1\ALU.ucf]
+Finished Parsing UCF File [X:\My Documents\ec311\ec311-lab1\ALU.ucf]
+INFO: [PlanAhead-566] Unisim Transformation Summary:
+No Unisim elements were transformed.open_netlist_design: Time (s): 13.385w. Memory (MB): 744.074p 196.641g
+refresh_design
+Release 13.3 - ngc2edif O.76xd (nt64)
+Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
+Reading design ALU.ngc ...
+WARNING:NetListWriters:298 - No output is written to ALU.xncf, ignored.
+Processing design ...
+ Preping design's networks ...
+ Preping design's macros ...
+ finished :Prep
+Writing EDIF netlist file ALU.edif ...
+ngc2edif: Total memory usage is 91432 kilobytes
+
+Parsing EDIF File [.\planAhead_run_2\lab1.data\cache\ALU_ngc_c04f956c.edif]
+Finished Parsing EDIF File [.\planAhead_run_2\lab1.data\cache\ALU_ngc_c04f956c.edif]
+Loading clock regions from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts/xilinx/spartan6/spartan6lx/xc6slx16/ClockRegion.xml
+Loading clock buffers from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts/xilinx/spartan6/spartan6lx/xc6slx16/ClockBuffers.xml
+Loading package pin functions from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts\xilinx\spartan6/PinFunctions.xml...
+Loading package from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts/xilinx/spartan6/spartan6lx/xc6slx16/csg324/Package.xml
+Loading io standards from C:/Xilinx/13.3/ISE_DS/PlanAhead\./parts/xilinx/spartan6/IOStandards.xml
+Loading list of drcs for the architecture : C:/Xilinx/13.3/ISE_DS/PlanAhead\./parts/xilinx/spartan6/drc.xml
+Parsing UCF File [X:\My Documents\ec311\ec311-lab1\ALU.ucf]
+Finished Parsing UCF File [X:\My Documents\ec311\ec311-lab1\ALU.ucf]
+refresh_design: Time (s): 9.017w. Memory (MB): 778.047p 27.094g
+refresh_design
+Release 13.3 - ngc2edif O.76xd (nt64)
+Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
+Reading design ALU.ngc ...
+WARNING:NetListWriters:298 - No output is written to ALU.xncf, ignored.
+Processing design ...
+ Preping design's networks ...
+ Preping design's macros ...
+ finished :Prep
+Writing EDIF netlist file ALU.edif ...
+ngc2edif: Total memory usage is 91752 kilobytes
+
+Parsing EDIF File [.\planAhead_run_2\lab1.data\cache\ALU_ngc_c04f956c.edif]
+Finished Parsing EDIF File [.\planAhead_run_2\lab1.data\cache\ALU_ngc_c04f956c.edif]
+Loading clock regions from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts/xilinx/spartan6/spartan6lx/xc6slx16/ClockRegion.xml
+Loading clock buffers from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts/xilinx/spartan6/spartan6lx/xc6slx16/ClockBuffers.xml
+Loading package pin functions from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts\xilinx\spartan6/PinFunctions.xml...
+Loading package from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts/xilinx/spartan6/spartan6lx/xc6slx16/csg324/Package.xml
+Loading io standards from C:/Xilinx/13.3/ISE_DS/PlanAhead\./parts/xilinx/spartan6/IOStandards.xml
+Loading list of drcs for the architecture : C:/Xilinx/13.3/ISE_DS/PlanAhead\./parts/xilinx/spartan6/drc.xml
+Parsing UCF File [X:\My Documents\ec311\ec311-lab1\ALU.ucf]
+Finished Parsing UCF File [X:\My Documents\ec311\ec311-lab1\ALU.ucf]
+refresh_design: Time (s): 7.317w. Memory (MB): 783.742p 5.559g
+refresh_design
+Release 13.3 - ngc2edif O.76xd (nt64)
+Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
+Reading design ALU.ngc ...
+WARNING:NetListWriters:298 - No output is written to ALU.xncf, ignored.
+Processing design ...
+ Preping design's networks ...
+ Preping design's macros ...
+ finished :Prep
+Writing EDIF netlist file ALU.edif ...
+ngc2edif: Total memory usage is 91560 kilobytes
+
+Parsing EDIF File [.\planAhead_run_2\lab1.data\cache\ALU_ngc_c04f956c.edif]
+Finished Parsing EDIF File [.\planAhead_run_2\lab1.data\cache\ALU_ngc_c04f956c.edif]
+Loading clock regions from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts/xilinx/spartan6/spartan6lx/xc6slx16/ClockRegion.xml
+Loading clock buffers from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts/xilinx/spartan6/spartan6lx/xc6slx16/ClockBuffers.xml
+Loading package pin functions from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts\xilinx\spartan6/PinFunctions.xml...
+Loading package from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts/xilinx/spartan6/spartan6lx/xc6slx16/csg324/Package.xml
+Loading io standards from C:/Xilinx/13.3/ISE_DS/PlanAhead\./parts/xilinx/spartan6/IOStandards.xml
+Loading list of drcs for the architecture : C:/Xilinx/13.3/ISE_DS/PlanAhead\./parts/xilinx/spartan6/drc.xml
+Parsing UCF File [X:\My Documents\ec311\ec311-lab1\ALU.ucf]
+Finished Parsing UCF File [X:\My Documents\ec311\ec311-lab1\ALU.ucf]
+refresh_design: Time (s): 7.364w. Memory (MB): 786.453p 2.711g
+refresh_design
+Release 13.3 - ngc2edif O.76xd (nt64)
+Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
+Reading design ALU.ngc ...
+WARNING:NetListWriters:298 - No output is written to ALU.xncf, ignored.
+Processing design ...
+ Preping design's networks ...
+ Preping design's macros ...
+ finished :Prep
+Writing EDIF netlist file ALU.edif ...
+ngc2edif: Total memory usage is 91880 kilobytes
+
+Parsing EDIF File [.\planAhead_run_2\lab1.data\cache\ALU_ngc_c04f956c.edif]
+Finished Parsing EDIF File [.\planAhead_run_2\lab1.data\cache\ALU_ngc_c04f956c.edif]
+Loading clock regions from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts/xilinx/spartan6/spartan6lx/xc6slx16/ClockRegion.xml
+Loading clock buffers from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts/xilinx/spartan6/spartan6lx/xc6slx16/ClockBuffers.xml
+Loading package pin functions from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts\xilinx\spartan6/PinFunctions.xml...
+Loading package from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts/xilinx/spartan6/spartan6lx/xc6slx16/csg324/Package.xml
+Loading io standards from C:/Xilinx/13.3/ISE_DS/PlanAhead\./parts/xilinx/spartan6/IOStandards.xml
+Loading list of drcs for the architecture : C:/Xilinx/13.3/ISE_DS/PlanAhead\./parts/xilinx/spartan6/drc.xml
+Parsing UCF File [X:\My Documents\ec311\ec311-lab1\ALU.ucf]
+Finished Parsing UCF File [X:\My Documents\ec311\ec311-lab1\ALU.ucf]
+refresh_design: Time (s): 7.628w. Memory (MB): 805.910p 19.457g
+refresh_design
+Release 13.3 - ngc2edif O.76xd (nt64)
+Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
+Reading design ALU.ngc ...
+WARNING:NetListWriters:298 - No output is written to ALU.xncf, ignored.
+Processing design ...
+ Preping design's networks ...
+ Preping design's macros ...
+ finished :Prep
+Writing EDIF netlist file ALU.edif ...
+ngc2edif: Total memory usage is 91368 kilobytes
+
+Parsing EDIF File [.\planAhead_run_2\lab1.data\cache\ALU_ngc_c04f956c.edif]
+Finished Parsing EDIF File [.\planAhead_run_2\lab1.data\cache\ALU_ngc_c04f956c.edif]
+Loading clock regions from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts/xilinx/spartan6/spartan6lx/xc6slx16/ClockRegion.xml
+Loading clock buffers from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts/xilinx/spartan6/spartan6lx/xc6slx16/ClockBuffers.xml
+Loading package pin functions from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts\xilinx\spartan6/PinFunctions.xml...
+Loading package from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts/xilinx/spartan6/spartan6lx/xc6slx16/csg324/Package.xml
+Loading io standards from C:/Xilinx/13.3/ISE_DS/PlanAhead\./parts/xilinx/spartan6/IOStandards.xml
+Loading list of drcs for the architecture : C:/Xilinx/13.3/ISE_DS/PlanAhead\./parts/xilinx/spartan6/drc.xml
+Parsing UCF File [X:\My Documents\ec311\ec311-lab1\ALU.ucf]
+Finished Parsing UCF File [X:\My Documents\ec311\ec311-lab1\ALU.ucf]
+refresh_design: Time (s): 7.425w. Memory (MB): 807.293p 0.000g
+refresh_design
+Release 13.3 - ngc2edif O.76xd (nt64)
+Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
+Reading design ALU.ngc ...
+WARNING:NetListWriters:298 - No output is written to ALU.xncf, ignored.
+Processing design ...
+ Preping design's networks ...
+ Preping design's macros ...
+ finished :Prep
+Writing EDIF netlist file ALU.edif ...
+ngc2edif: Total memory usage is 91304 kilobytes
+
+Parsing EDIF File [.\planAhead_run_2\lab1.data\cache\ALU_ngc_c04f956c.edif]
+Finished Parsing EDIF File [.\planAhead_run_2\lab1.data\cache\ALU_ngc_c04f956c.edif]
+Loading clock regions from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts/xilinx/spartan6/spartan6lx/xc6slx16/ClockRegion.xml
+Loading clock buffers from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts/xilinx/spartan6/spartan6lx/xc6slx16/ClockBuffers.xml
+Loading package pin functions from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts\xilinx\spartan6/PinFunctions.xml...
+Loading package from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts/xilinx/spartan6/spartan6lx/xc6slx16/csg324/Package.xml
+Loading io standards from C:/Xilinx/13.3/ISE_DS/PlanAhead\./parts/xilinx/spartan6/IOStandards.xml
+Loading list of drcs for the architecture : C:/Xilinx/13.3/ISE_DS/PlanAhead\./parts/xilinx/spartan6/drc.xml
+Parsing UCF File [X:\My Documents\ec311\ec311-lab1\ALU.ucf]
+Finished Parsing UCF File [X:\My Documents\ec311\ec311-lab1\ALU.ucf]
+refresh_design: Time (s): 7.566w. Memory (MB): 807.293p 0.000g
+exit
+stop_gui
+INFO: [PlanAhead-261] Exiting PlanAhead...
+INFO: [Common-83] Releasing license: PlanAhead