From 70b77304f37d9681aa3bfa0eb57df0bcfd1aef81 Mon Sep 17 00:00:00 2001 From: Michael Abed Date: Fri, 17 Feb 2012 12:08:05 -0500 Subject: make it work --- ALU.bld | 4 +- ALU.cmd_log | 67 + ALU.jhd | 18 +- ALU.ncd | 2 +- ALU.ngc | 2 +- ALU.ngd | 2 +- ALU.ngr | 2 +- ALU.pad | 10 +- ALU.par | 12 +- ALU.pcf | 8 +- ALU.sch | 930 ++++---- ALU.schlog | 0 ALU.sym | 63 + ALU.syr | 169 +- ALU.twr | 100 +- ALU.twx | 4 +- ALU.ucf | 7 +- ALU.unroutes | 2 +- ALU.vf | 258 +- ALU_bitgen.xwbt | 6 +- ALU_envsettings.html | 100 +- ALU_guide.ncd | 2 +- ALU_map.map | 40 +- ALU_map.mrp | 8 +- ALU_map.ncd | 2 +- ALU_map.ngm | 2 +- ALU_map.xrpt | 14 +- ALU_ngdbuild.xrpt | 46 +- ALU_pad.csv | 10 +- ALU_pad.txt | 10 +- ALU_par.xrpt | 42 +- ALU_summary.html | 62 +- ALU_summary.xml | 2 +- ALU_usage.xml | 256 +- ALU_xst.xrpt | 32 +- Divide.cmd_log | 9 + Divide.jhd | 18 +- Divide.sch | 339 ++- Divide.schlog | 0 Divide.sym | 66 +- Divide.vf | 72 +- Divide_0.cmd_log | 7 + Divide_0.jhd | 2 +- Divide_0.sch | 337 ++- Divide_0.sym | 48 +- Divide_0.vf | 14 +- Divide_1.cmd_log | 1 + Divide_1.jhd | 2 +- Divide_1.sch | 416 ++-- Divide_1.sym | 48 +- Divide_1.vf | 4 +- Divide_2.cmd_log | 2 + Divide_2.jhd | 2 +- Divide_2.sch | 202 +- Divide_2.sym | 48 +- Divide_2.vf | 39 +- Divide_3.cmd_log | 2 + Divide_3.sch | 79 +- Divide_3.sym | 48 +- Divide_3.vf | 21 +- Modulo.cmd_log | 5 + Modulo.sch | 6 +- Modulo.schlog | 0 Modulo.sym | 66 +- Modulo.vf | 91 +- Modulo_0.cmd_log | 4 + Modulo_0.sch | 174 +- Modulo_0.sym | 48 +- Modulo_0.vf | 41 +- Modulo_1.cmd_log | 3 + Modulo_1.jhd | 2 +- Modulo_1.sch | 593 ++--- Modulo_1.sym | 48 +- Modulo_1.vf | 54 +- Modulo_3.cmd_log | 2 + Modulo_3.schlog | 2 + Modulo_3.sym | 48 +- Modulo_3.vf | 4 +- Negate.cmd_log | 4 + Negate.jhd | 18 +- Negate.sch | 338 +-- Negate.schlog | 0 Negate.sym | 66 +- Negate.vf | 77 +- Negate_0.cmd_log | 2 + Negate_0.sym | 48 +- Negate_0.vf | 4 +- Negate_1.cmd_log | 2 + Negate_1.sym | 48 +- Negate_1.vf | 4 +- Negate_2.cmd_log | 4 + Negate_2.jhd | 2 +- Negate_2.sch | 369 +-- Negate_2.sym | 48 +- Negate_2.vf | 59 +- Negate_3.cmd_log | 2 + Negate_3.jhd | 2 +- Negate_3.sch | 192 +- Negate_3.sym | 48 +- Negate_3.vf | 22 +- _ngo/netlist.lst | 2 +- _xmsgs/bitgen.xmsgs | 2 +- _xmsgs/map.xmsgs | 12 +- _xmsgs/par.xmsgs | 4 +- _xmsgs/pn_parser.xmsgs | 24 +- _xmsgs/trce.xmsgs | 6 +- alu.bgn | 2 +- alu.bit | Bin 464285 -> 464285 bytes alu.drc | 2 +- alu.msd | 2 +- alu.msk | Bin 464285 -> 464285 bytes alu.rbb | Bin 464117 -> 464117 bytes alu.rbd | 636 ++--- impact_impact.xwbt | 6 +- iseconfig/ALU.xreport | 8 +- iseconfig/lab1.projectmgr | 156 +- lab1.gise | 43 +- lab1.xise | 5 +- pa.fromHdl.tcl | 2 +- pa.fromNetlist.tcl | 6 +- par_usage_statistics.html | 18 +- planAhead.ngc2edif.log | 88 + .../lab1.data/cache/ALU_ngc_c04f956c.edif | 2404 +++++++++++++++++++ .../lab1.data/constrs_1/designprops.xml | 29 + planAhead_run_1/lab1.data/constrs_1/fileset.xml | 20 + planAhead_run_1/lab1.data/constrs_1/usercols.xml | 4 + planAhead_run_1/lab1.data/runs/impl_1.psg | 18 + planAhead_run_1/lab1.data/runs/runs.xml | 5 + planAhead_run_1/lab1.data/sources_1/chipscope.xml | 6 + planAhead_run_1/lab1.data/sources_1/fileset.xml | 156 +- planAhead_run_1/lab1.data/sources_1/ports.xml | 24 + planAhead_run_1/lab1.ppr | 1 + planAhead_run_1/planAhead.jou | 22 +- planAhead_run_1/planAhead.log | 139 +- planAhead_run_1/planAhead_run.log | 112 +- .../lab1.data/cache/ALU_ngc_c04f956c.edif | 2476 ++++++++++++++++++++ planAhead_run_2/lab1.data/constrs_1/fileset.xml | 25 + planAhead_run_2/lab1.data/runs/impl_1.psg | 18 + planAhead_run_2/lab1.data/runs/runs.xml | 5 + planAhead_run_2/lab1.data/sources_1/fileset.xml | 29 + planAhead_run_2/lab1.data/wt/webtalk_pa.xml | 26 + planAhead_run_2/lab1.ppr | 14 + planAhead_run_2/planAhead.jou | 18 + planAhead_run_2/planAhead.log | 198 ++ planAhead_run_2/planAhead_run.log | 196 ++ sch2HdlBatchFile | 3 + sev_seg_disp.vf | 4 +- usage_statistics_webtalk.html | 18 +- webtalk.log | 4 +- webtalk_impact.xml | 26 +- webtalk_pn.xml | 9 +- xlnx_auto_0_xdb/cst.xbcd | Bin 1631 -> 1549 bytes xst/work/work.sdbl | Bin 131898 -> 139419 bytes xst/work/work.sdbx | Bin 1035 -> 1035 bytes 154 files changed, 9769 insertions(+), 3934 deletions(-) create mode 100755 ALU.schlog create mode 100755 ALU.sym create mode 100755 Divide.schlog create mode 100755 Modulo.schlog create mode 100755 Modulo_3.schlog create mode 100755 Negate.schlog create mode 100755 planAhead_run_1/lab1.data/cache/ALU_ngc_c04f956c.edif create mode 100755 planAhead_run_1/lab1.data/constrs_1/designprops.xml create mode 100755 planAhead_run_1/lab1.data/constrs_1/usercols.xml create mode 100755 planAhead_run_1/lab1.data/runs/impl_1.psg create mode 100755 planAhead_run_1/lab1.data/runs/runs.xml create mode 100755 planAhead_run_1/lab1.data/sources_1/chipscope.xml create mode 100755 planAhead_run_1/lab1.data/sources_1/ports.xml create mode 100755 planAhead_run_2/lab1.data/cache/ALU_ngc_c04f956c.edif create mode 100755 planAhead_run_2/lab1.data/constrs_1/fileset.xml create mode 100755 planAhead_run_2/lab1.data/runs/impl_1.psg create mode 100755 planAhead_run_2/lab1.data/runs/runs.xml create mode 100755 planAhead_run_2/lab1.data/sources_1/fileset.xml create mode 100755 planAhead_run_2/lab1.data/wt/webtalk_pa.xml create mode 100755 planAhead_run_2/lab1.ppr create mode 100755 planAhead_run_2/planAhead.jou create mode 100755 planAhead_run_2/planAhead.log create mode 100755 planAhead_run_2/planAhead_run.log diff --git a/ALU.bld b/ALU.bld index 6186a2d..2e3d732 100755 --- a/ALU.bld +++ b/ALU.bld @@ -5,7 +5,7 @@ Command Line: C:\Xilinx\13.3\ISE_DS\ISE\bin\nt64\unwrapped\ngdbuild.exe -intstyle ise -dd _ngo -nt timestamp -uc ALU.ucf -p xc6slx16-csg324-3 ALU.ngc ALU.ngd -Reading NGO file "X:/My Documents/ec311/lab1/ALU.ngc" ... +Reading NGO file "X:/My Documents/ec311/ec311-lab1/ALU.ngc" ... Gathering constraint information from source properties... Done. @@ -27,7 +27,7 @@ NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0 -Total memory usage is 156564 kilobytes +Total memory usage is 154784 kilobytes Writing NGD file "ALU.ngd" ... Total REAL time to NGDBUILD completion: 4 sec diff --git a/ALU.cmd_log b/ALU.cmd_log index de0ed5a..4963564 100755 --- a/ALU.cmd_log +++ b/ALU.cmd_log @@ -8,3 +8,70 @@ map -intstyle ise -p xc6slx16-csg324-3 -w -logic_opt off -ol high -t 1 -xt 0 -re par -w -intstyle ise -ol high -mt off ALU_map.ncd ALU.ncd ALU.pcf trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml ALU.twx ALU.ncd -o ALU.twr ALU.pcf -ucf ALU.ucf bitgen -intstyle ise -f ALU.ut ALU.ncd +sch2sym -intstyle ise -family spartan6 -w -refsym ALU {X:/My Documents/ec311/ec311-lab1/ALU.sch} {X:/My Documents/ec311/ec311-lab1/ALU.sym} +xst -intstyle ise -ifn "X:/My Documents/ec311/ec311-lab1/ALU.xst" -ofn "X:/My Documents/ec311/ec311-lab1/ALU.syr" +ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc ALU.ucf -p xc6slx16-csg324-3 "ALU.ngc" ALU.ngd +map -intstyle ise -p xc6slx16-csg324-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o ALU_map.ncd ALU.ngd ALU.pcf +par -w -intstyle ise -ol high -mt off ALU_map.ncd ALU.ncd ALU.pcf +trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml ALU.twx ALU.ncd -o ALU.twr ALU.pcf -ucf ALU.ucf +bitgen -intstyle ise -f ALU.ut ALU.ncd +sch2sym -intstyle ise -family spartan6 -w -refsym ALU {X:/My Documents/ec311/ec311-lab1/ALU.sch} {X:/My Documents/ec311/ec311-lab1/ALU.sym} +xst -intstyle ise -ifn "X:/My Documents/ec311/ec311-lab1/ALU.xst" -ofn "X:/My Documents/ec311/ec311-lab1/ALU.syr" +ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc ALU.ucf -p xc6slx16-csg324-3 "ALU.ngc" ALU.ngd +map -intstyle ise -p xc6slx16-csg324-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o ALU_map.ncd ALU.ngd ALU.pcf +sch2sym -intstyle ise -family spartan6 -w -refsym ALU {X:/My Documents/ec311/ec311-lab1/ALU.sch} {X:/My Documents/ec311/ec311-lab1/ALU.sym} +sch2sym -intstyle ise -family spartan6 -w -refsym ALU {X:/My Documents/ec311/ec311-lab1/ALU.sch} {X:/My Documents/ec311/ec311-lab1/ALU.sym} +xst -intstyle ise -ifn "X:/My Documents/ec311/ec311-lab1/ALU.xst" -ofn "X:/My Documents/ec311/ec311-lab1/ALU.syr" +ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc ALU.ucf -p xc6slx16-csg324-3 "ALU.ngc" ALU.ngd +map -intstyle ise -p xc6slx16-csg324-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o ALU_map.ncd ALU.ngd ALU.pcf +par -w -intstyle ise -ol high -mt off ALU_map.ncd ALU.ncd ALU.pcf +trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml ALU.twx ALU.ncd -o ALU.twr ALU.pcf -ucf ALU.ucf +bitgen -intstyle ise -f ALU.ut ALU.ncd +xst -intstyle ise -ifn "X:/My Documents/ec311/ec311-lab1/ALU.xst" -ofn "X:/My Documents/ec311/ec311-lab1/ALU.syr" +ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc ALU.ucf -p xc6slx16-csg324-3 "ALU.ngc" ALU.ngd +map -intstyle ise -p xc6slx16-csg324-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o ALU_map.ncd ALU.ngd ALU.pcf +par -w -intstyle ise -ol high -mt off ALU_map.ncd ALU.ncd ALU.pcf +trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml ALU.twx ALU.ncd -o ALU.twr ALU.pcf -ucf ALU.ucf +bitgen -intstyle ise -f ALU.ut ALU.ncd +xst -intstyle ise -ifn "X:/My Documents/ec311/ec311-lab1/ALU.xst" -ofn "X:/My Documents/ec311/ec311-lab1/ALU.syr" +ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc ALU.ucf -p xc6slx16-csg324-3 "ALU.ngc" ALU.ngd +map -intstyle ise -p xc6slx16-csg324-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o ALU_map.ncd ALU.ngd ALU.pcf +par -w -intstyle ise -ol high -mt off ALU_map.ncd ALU.ncd ALU.pcf +trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml ALU.twx ALU.ncd -o ALU.twr ALU.pcf -ucf ALU.ucf +bitgen -intstyle ise -f ALU.ut ALU.ncd +xst -intstyle ise -ifn "X:/My Documents/ec311/ec311-lab1/ALU.xst" -ofn "X:/My Documents/ec311/ec311-lab1/ALU.syr" +ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc ALU.ucf -p xc6slx16-csg324-3 "ALU.ngc" ALU.ngd +map -intstyle ise -p xc6slx16-csg324-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o ALU_map.ncd ALU.ngd ALU.pcf +par -w -intstyle ise -ol high -mt off ALU_map.ncd ALU.ncd ALU.pcf +trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml ALU.twx ALU.ncd -o ALU.twr ALU.pcf -ucf ALU.ucf +bitgen -intstyle ise -f ALU.ut ALU.ncd +xst -intstyle ise -ifn "X:/My Documents/ec311/ec311-lab1/ALU.xst" -ofn "X:/My Documents/ec311/ec311-lab1/ALU.syr" +ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc ALU.ucf -p xc6slx16-csg324-3 "ALU.ngc" ALU.ngd +map -intstyle ise -p xc6slx16-csg324-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o ALU_map.ncd ALU.ngd ALU.pcf +par -w -intstyle ise -ol high -mt off ALU_map.ncd ALU.ncd ALU.pcf +trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml ALU.twx ALU.ncd -o ALU.twr ALU.pcf -ucf ALU.ucf +bitgen -intstyle ise -f ALU.ut ALU.ncd +xst -intstyle ise -ifn "X:/My Documents/ec311/ec311-lab1/ALU.xst" -ofn "X:/My Documents/ec311/ec311-lab1/ALU.syr" +ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc ALU.ucf -p xc6slx16-csg324-3 "ALU.ngc" ALU.ngd +map -intstyle ise -p xc6slx16-csg324-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o ALU_map.ncd ALU.ngd ALU.pcf +par -w -intstyle ise -ol high -mt off ALU_map.ncd ALU.ncd ALU.pcf +trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml ALU.twx ALU.ncd -o ALU.twr ALU.pcf -ucf ALU.ucf +bitgen -intstyle ise -f ALU.ut ALU.ncd +xst -intstyle ise -ifn "X:/My Documents/ec311/ec311-lab1/ALU.xst" -ofn "X:/My Documents/ec311/ec311-lab1/ALU.syr" +ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc ALU.ucf -p xc6slx16-csg324-3 "ALU.ngc" ALU.ngd +map -intstyle ise -p xc6slx16-csg324-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o ALU_map.ncd ALU.ngd ALU.pcf +par -w -intstyle ise -ol high -mt off ALU_map.ncd ALU.ncd ALU.pcf +trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml ALU.twx ALU.ncd -o ALU.twr ALU.pcf -ucf ALU.ucf +bitgen -intstyle ise -f ALU.ut ALU.ncd +xst -intstyle ise -ifn "X:/My Documents/ec311/ec311-lab1/ALU.xst" -ofn "X:/My Documents/ec311/ec311-lab1/ALU.syr" +ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc ALU.ucf -p xc6slx16-csg324-3 "ALU.ngc" ALU.ngd +map -intstyle ise -p xc6slx16-csg324-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o ALU_map.ncd ALU.ngd ALU.pcf +par -w -intstyle ise -ol high -mt off ALU_map.ncd ALU.ncd ALU.pcf +trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml ALU.twx ALU.ncd -o ALU.twr ALU.pcf -ucf ALU.ucf +bitgen -intstyle ise -f ALU.ut ALU.ncd +xst -intstyle ise -ifn "X:/My Documents/ec311/ec311-lab1/ALU.xst" -ofn "X:/My Documents/ec311/ec311-lab1/ALU.syr" +ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc ALU.ucf -p xc6slx16-csg324-3 "ALU.ngc" ALU.ngd +map -intstyle ise -p xc6slx16-csg324-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o ALU_map.ncd ALU.ngd ALU.pcf +par -w -intstyle ise -ol high -mt off ALU_map.ncd ALU.ncd ALU.pcf +trce -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml ALU.twx ALU.ncd -o ALU.twr ALU.pcf -ucf ALU.ucf +bitgen -intstyle ise -f ALU.ut ALU.ncd diff --git a/ALU.jhd b/ALU.jhd index 7beadb5..1b290b6 100755 --- a/ALU.jhd +++ b/ALU.jhd @@ -1,9 +1,9 @@ -MODULE ALU - SUBMODULE Divide - INSTANCE XLXI_1 - SUBMODULE Modulo - INSTANCE XLXI_2 - SUBMODULE Negate - INSTANCE XLXI_3 - SUBMODULE sev_seg_disp - INSTANCE XLXI_9 +MODULE ALU + SUBMODULE Divide + INSTANCE XLXI_1 + SUBMODULE Modulo + INSTANCE XLXI_2 + SUBMODULE Negate + INSTANCE XLXI_3 + SUBMODULE sev_seg_disp + INSTANCE XLXI_9 diff --git a/ALU.ncd b/ALU.ncd index be0b713..ca10a31 100755 --- a/ALU.ncd +++ b/ALU.ncd @@ -1,3 +1,3 @@ XILINX-XDB 0.1 STUB 0.1 ASCII XILINX-XDM V1.6 -###6396:XlxV32DM 3fff 18e4eNqlWtlyGzmy/RU+6KFth+zCWlVEOMLcrGY0RWpEyu2+D2LUquGMLGksecYTkvztN7GjFpryvd0tAjiVSJxMJBIoVB8hlDyiSBydV//e3e9ub4YD9JYOjrA4Jrk4vrq+zbPr7e3dQyqOdzcP9w//va4K7OuD3X01OL4bfC/4/fV3xI+L+yuC6TEZHP9ncHx9e7UrZO/BbV0Pjm+vB3/fXf19cPwwQIPj7w+DaHD8tbra3T9UX7flt7vrXZE9AAct/XVABwEBDX4x5e6rLu9MeV2Y9u1/KgPdDkaLi+2X7O7tTVHK+tubK13eFfWAgA1f4ee6yITnCcAX+XN7zYXWBY27r4iJXqLgiAdSCWlq0yHOUsO3w6TwTGLx7mw0RVFqKiiyFWQr2FaIrVBbYbbCbSW2lcRWrGZsNTPbnaVcVXBsysSUBidRKd6tF/PJbPsZ479w3GwmQZM0miT6C8XNZoIEIoK8VT8YiREWIwR/GP4I/FH4Y/DHiQDX5ML57OoLIMsokT/b1fjio2wi2USuiWUTuyaRTaKaXIy2cyhLU27vsuKf26TZTJEYYzEGOmOgMwY6Y6AzBjpjDqtjfDFfTLeb0fnJDH4mv3MxNjrHgRLWbMaFGFfX94PoLYFwX5WqNZyvQOb04nMVNJfQp/bt1cUGgFQDi4sNT3RVTpiYYPgP/oDiBChOgOJEUpyMpttP89mf20+z8/V8tUzFZHV6Ot9sZtMMqusN0B8vZrGYnM9GAHIxMSZMAs682QQvTW6/3DkbUt2ULAtTVRP8GYkpFhBgUMAfcJsCtylwm3IupmagaXOgadNXs48fV+eb7WL2abYoxcliNR4ttovVyXwSNZsIiTkW82UigMY76ctU16QbM1XVHoxVHbzGxWI1ms6msZDefDdCtoJthdgKtRVmKxzi9XR0tp2cThfz5Wy7OtuAe9eZAk9X04vFrFT1zfx0tt6MTs9y1TTzAJ2zu1gsZ5s/V+d/ILHiYvU25t9LDFUigGkqzsj2bDGazCAJuLodh4uz0eSP2ZQIOf3y97xNBbLT2XS9HS9Wkz+2J8vpdjxfTufLE5T249vz2UepyT1TA57Olps6AC/Wo5NZQ/WnyaRXdYAr1e0+cujTk3OUK3y6Wm62Ogi3F8uL9Wy6PZsv13pocNP2HHwCqgoHbP46m2W6dQJBM9WiZ9NT62OIO4XMl9vRej0/WW5hAgwNCc4+b2ZLmH+lCWnFaq2ETvk0myj2yD+Ww63/Wk7CLqGxtgsLHmtGW5kljI8b+DlE6NkfW1ibZ5vRCaKyMZ0pzsuT0+16dXE+mdUShaaLKAC+3j7cyhWH3sqIlyybyFvUg+EejPRgtAdjkn4Lg5nBYg27yDpSi7eyFb2KSasNOWANa22NrDAKH7baLBU6l8D69FXsq8RXWeGqfCFXkGmNfc+x7zn2PcfUV/2AY174aqhv4vVNvL6J1zfxTCaNnlPfc+p7Tn3PqWcy9UymnslU6qvExi0lGby1apuAUdFM2wgs3Nk5rAgNf5Lbr8wgsJjrJna+KRvAKWSfoL0+m6mEtDGLaH56BsTmG61l01h9GxvmisBiPl6jUnyeQ5L6fPx5OobtAw3WmwtdGa0n83ktPi8+z7f03emXb9+3K4QMwNoAbwOxAwoNpO9G2/HoHMI1bJog60XTyoKqILTZpqjVjlvtpNVu6WO41Satdqs/j+qgvdwizBBvI5o5akvCqU/VMKltxUhGVRPArTaxPal9QMMxgnbUEsC2J7MPWKunbaOWAAGzynw7L3Mov2zHu5tyd3MFQSZbp9k/br9+qr7KtxAL7W4cxES2vf32kOlCHe2YyDWUB1ChocJBsSi+lNe7m4oL/XLCRKllyqBbpaEqgGoN1QF0paErB1Ehz/lEwKmfCDjpE3GXfaXifnd1k6pfJZWIe4Afshs4ytk3JVKKp+n5/BNshJvz8erzEGE4TM3+hJ8V/FzA+ltOhwTy/2b29AQHuNFyOjqfDhefJqerNWZpIgDm73/77ccIvZa/+PWIvHrzG5SyRV7DD30DP+zNiL96JZ8YDKBX6h+AbFff5bWUfiNFjK5AmXzKnC4lLZW9GVEAVUf45ynFh6iBfKDitxHTg0r9ivAPo6qXoyYpR+WGyQ9rIMiMyBtvuNfzBJn1paQO+MgY7cYPBnW9nuDlpzPcDzfeD9lBOdRMTmsgOxXSCGNd2NN57UfDba+9154gH7jxjc/eOOavnee8M53v7SySrKEhnKjO/P8W8pGdcdLXOQxEG0p9op6e7vdBq33CuRH9YVxhA8jNtQ/RV08ocdItTU+Ve6IMeqqDttTzBGe6p6eneWfVPX/4cIcxFR8+fCfR8OOQDdHjmsXDuBjG9RAREuE0HhJEGH68qaMhEjc1GnJxVFXDohLPa8a6svBmvI7REEVsGDVwODuBfBcv+nF4zy+BFWD7WYmjgg0LIEQpKEjETZwNaU0KJK8AjuJUgUdxDh3FUZpDJ/HvTUK10iEuf6K3GMLO8DcA0OPz31LpmeejFA9hfo8Ylc+OCqO+SKBMoYyHtSwy6ae0sERS8d80HZIqgTJR5SIhQ/x4xGU/LG4Yhw7PvydYLOJkmD8e1cmQiiMMT6EgUBBxxHUr1gXTRaGLTBe5LlKl9agcYg5aUy7+p4D6I8uHNBnCMBWMz4dEDVM58UR1fs61x2HsGGx8/BdMzr+SRPwO7847nMKj34tcfEvBAZEQO1K2EVq1EdZBMtpBkhZyS3AHoR2Ed5COnrqjp+7oqTt66qyDFB2kbdctiqIu1Nadq9Gw/PfxJs2GPALfwxwwmE06hAP4LpaKxZtELgcQj5U4aH6UcryG0ILYzaCXnPZMdaO52HHJUNwmSBbPehjk+sWR6ocLLV9a/c/3SpA8voeBYOW+h2bCxCX8wSM1tnoE+80lHByfn3M1e3hIoI/ijzT/wvK/5XnIPy2b/EtNIAXCeYNwxpqClTYUa0NRrPtltsPO8Nd8uobSjqFKEAyFgcC699B0huqxH98DWZ4LJYEkTBwM7Ut4JO1PmvZjbX++z/7qpfanvfaTg/Ynvfazrv2JsT/V9ieB/akxtNL2py37q8B+tTaC+CXafr4vfvPe+M0Pxm/Wa1bZjd/MxG+u4zcL4jc38ZsH8atWcsCfav7xPv5lL//iIP+il3/V5V8Y/qXmXwT8S8O/DPjrlBIYwLQB2R4DUNSfQepDFuiBOibAFto2QUuCDXIsaYQEnBWliSL5MJiGqmkF11Yk+6ah7jWiPDgNVe801N1pqMw01HoaqmAaajMNdcBfbVAB/1jzx3v4E9LLnx7ir4bp8ucd/koQ+MNAkj80HX+eaf7wKOBPm/wTzR/t4896+bOD/Puzc9zlb7IzYZo/7eHPQv6tVZBq/tE+/v2LgB/k37+NJl3+ZgkQvQII7+Efxj9Jmvwzxb/eRz/tpR8fpN+/OaRd+mZzIKmmH2wO3GwO8MjTx2lzF8wVfRzt2wXrF+6CJOvbBatDm6Ci07Uz6tipBKWdapt4j1NvJzHTBFzlJiglGptgHWyCpGyaX+joK/eYn0UvNJ/2HoLqQ+YrOl3zu5laCYL5VJ+BoOnMp+YMBFyl+bR1BgLYm0+rpvmlNr/aZz56ofks6T0DRYfsp/1ZHnfspybLMxXf72mQ5fXYYChS9kuJhv0osJ+17K+0/fU++/EL7ef9Z2B0yH7Wbz/p2M+M/VzPPwvs53b+sbKft+cfB/brN50ge9XaAeneMwjqzV/V4TNI1HsGiXrOIJE9gyBzBom8cYaAfhocQpqbeGzexci+Q0j/Jp4cPIT0b+JZ9xBiNvFab+J1sInXZh7qcBOvm5t4bN7F6D7+/Zt4epB//yaed/mbTbzWm3gdbOK1Ca863MTVAZcDJa7453oTNHmLleJWrVexY5L0UUqkBLSIbeXwis20CHdgBSKcmlaB4JW7VEnf8c8Lxd+cHc2bNwVv4cr0iinowLVtcRgmibQvyqKhqyBKlzkHmbegpi6yT5c734POJBKXrJKn5dphcEq9hNeT5/sKeawCjEgsMliq+lLZt+IOk32Zkss8Bn0Zln5XIEqHFH60583+jZ3n1UYJxAtDPCukGaVtlSIwMatCE7Na3sSUqjuxIjmT10VWJOfyqiiyLSxbyLakv6ibcDkT1M0tzKaNCVoHUbBjkQ4U1IqX1MaLCxRWB6Gx445ELVuOhLSP40ZIWRJFZAMMIkseK5mPLL0yzOWMeRlQ0WDdGOPQjTo2XhJ1kljsx4n1CjQLt/DjZEHvHc5tKxYhB9LgQBscWIMDDjnkarG2VpE5QZucqTjkDQ6FjiMdDz2rIhgAN4w0S8tsflF50EgqXupo1hn8virMOsF+LRKPubXIMo/ZtUhjj5WAYbmdco9BvuNqL809lgMWSSzom8G4dXBvAR73a7t0mF/b1GNmbd9XsceAC0NhTskVFxaFOSVXXKgctzJHIIg2OS4pg2NBqd6aLykJTsqlutC4pDg4PpbqkuaSouBIVaqLx0saBVdNpdpALkkdXL+ValO8JFWwX8AKk1zglSXIb7Higuswv8WKC66CGweJARcs7aiwx4AL/Mk8qDZmLvOg2YH0Qd6cnHrzYNnIg1UjDxa/mgfRi/Mgb+RBKnr2xmR/rtMZrD/X6TyIm7togcNdVKbDvKz6cp05/JiLg2au+1mewXtzXVH35Tp7U1IdTAP4xbkubnBgYa7L+k4M8U92edyTz6K+fGYudKO8xxDyk3zGRU8Wjfdl6/vKroEoyGe5w1w+47HHbD5jqcdsPqPcYy6fZR5z+SyQs/nM5ZosyGfUYT6f5R6z+aw0eQCiwuUk6jGXk2yukZjNSTyQsznJ5i6JtXOSxNo5SWI2J7m3CFgKLim5ZFP1JKXKJyWXgKogKXGPuaSkvrqAB4aZTkn65dp80HhBSqp/cjQrggMzaix13Dj5dM86/jDN+9KAuc83928/SwP8J0eexnEjaYxjVo+5dzevOM1x4sY4+CfHmsYh3C6AJDiEU4f5QzjzmDuEpx6zC8UFceIXin15A99144b3xA0P4oZ7rLOZ8TBuauUweBnRcaMvJcyHIBk37YnXmwJubAq9h9yybybsW2P9i4m/5+xlL9hhIDcFzhWlnwLnsjKYAuwxNwXcY2YKzM0ffpTON9d+5joMMMgq5i7MXBEBBlnK3A+ZaxPAgJm5MzGfEwHLqP2WaD6xSSyx39fMxbwcA9tbeXPZLTFqb7rNBbLEuL09NreyEkvslay5IwCsxvaCwLx3S4zal27zXVdi3H7UNd/KJJbZD2Xm+5PECvvxyXwMkVhlv4TYCxYAoeJuV+y3HwVz9+En+HTMh7FUEg/VrKqsyh6lw+QlE0wyJFZZwD7xHqZStfBQ7RoqK0vZxMnWqoB9RsnqLmrXcV/6MjUcCKlNxn1AKzSLUrNQcRQ/KrZGHGJHKsOGRqkoy5b89i29Wg9VuLlvQZXWWGuN3HyEhAmWMMypKpR6c4OOHuUUqrbag8AyCENjGWxXyjKqhqfaQBXz1HiMlE4WaVmsZYmWdedtkKWVk420rBaiugt3eyPIMi9LtCzSsrpQRge3Z5F2GB6qHOYupbCdZQ3bux7q3OuO74n6nMn0WFhPqHS3jAE9JC60Jj0H0kzpfGTXOiiQPQvdRVtkZo9pM5mhovVI26UCbJNKqhloj2MTfpoPM7aZKMRaj1Yn/SL1uAsZ/c2W655UBw51Vzj6KdVRp+YV1EOoPt+gQq8u83n/WwoNIeHaw9TDZeRhFsDIwzyAsYfjACYeTgKYejgLYObhIoC5h6sAjh2MowBOPIwCOPUwDuDMw4FPytzDoU8KD4c+KT0c+sT7G4c+8f7GgU8qfY9s/ucTDV8kNXi5fCSIYJJRQgvKWEJLVrNE/p9qLIXfOIokQimUgQTUahrTFLCaMUZBAywjaFeMdvr3y4IgoRQT0ugHbddPSzApwQgU+6W9xGHptC0LJXayNU3BurAPhT6Jk/P6cY9+Kcvdc6u/IOiAfubkVJ/AY1Kylr2lzxi2GsKeTmujl+1DKUHwLHgKvUGCgf17Nf60D8zir2t8YR9VYikJbrA4bnkK75OSbZDVcwIRJPOSympcRX4UBD5J+COojCHww6BlMARWhCtaqRCJVD2cwrY0dxJ68qw07pWOA2kpAURVKLWlqZJOnISW7gYG6iy8bs+otyff269ftotqj4STBGxASxSiUGJY9bw5NX3PHWqWCPzLWKgX7ZNo6KCqHQQa/FKKINSQYS41gBjIgNYXjfrrOjs9ggX0fxgv6M1hTKyC3iTU/9dIv6Ktkb6M59vJ/WWz+FJN3dTWfRbGsNXfJ1+ZDSdqxb3cFIh7zn4qy0w6a8pWe2XTTibZL4sMi5b0/wIgR/Rh###2448:XlxV32DM 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\ No newline at end of file diff --git a/ALU.pad b/ALU.pad index 5481d6b..04e328a 100755 --- a/ALU.pad +++ b/ALU.pad @@ -1,7 +1,7 @@ Release 13.3 - par O.76xd (nt64) Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. -Wed Feb 15 15:16:15 2012 +Thu Feb 16 19:53:19 2012 # NOTE: This file is designed to be imported into a spreadsheet program @@ -26,7 +26,7 @@ A4||IOBS|IO_L5N_0|UNUSED||0||||||||| A5||IOBS|IO_L6N_0|UNUSED||0||||||||| A6||IOBS|IO_L8N_VREF_0|UNUSED||0||||||||| A7||IOBS|IO_L10N_0|UNUSED||0||||||||| -A8|C|IOB|IO_L33N_0|INPUT|LVCMOS25*|0||||NONE||LOCATED|NO|NONE| +A8||IOBS|IO_L33N_0|UNUSED||0||||||||| A9||IOBS|IO_L35N_GCLK16_0|UNUSED||0||||||||| A10||IOBS|IO_L37N_GCLK12_0|UNUSED||0||||||||| A11||IOBS|IO_L39N_0|UNUSED||0||||||||| @@ -58,12 +58,12 @@ B18|||TMS|||||||||||| C1||IOBS|IO_L83N_VREF_3|UNUSED||3||||||||| C2||IOBM|IO_L83P_3|UNUSED||3||||||||| C3|||GND|||||||||||| -C4||IOBS|IO_L1N_VREF_0|UNUSED||0||||||||| +C4|A|IOB|IO_L1N_VREF_0|INPUT|LVCMOS25*|0||||NONE||LOCATED|NO|NONE| C5||IOBM|IO_L6P_0|UNUSED||0||||||||| C6||IOBS|IO_L3N_0|UNUSED||0||||||||| C7||IOBM|IO_L10P_0|UNUSED||0||||||||| C8||IOBS|IO_L11N_0|UNUSED||0||||||||| -C9|A|IOB|IO_L34N_GCLK18_0|INPUT|LVCMOS25*|0||||NONE||LOCATED|NO|NONE| +C9|D|IOB|IO_L34N_GCLK18_0|INPUT|LVCMOS25*|0||||NONE||LOCATED|NO|NONE| C10||IOBM|IO_L37P_GCLK13_0|UNUSED||0||||||||| C11||IOBS|IO_L36N_GCLK14_0|UNUSED||0||||||||| C12||IOBS|IO_L47N_0|UNUSED||0||||||||| @@ -81,7 +81,7 @@ D5|||GND|||||||||||| D6||IOBM|IO_L3P_0|UNUSED||0||||||||| D7|||VCCO_0|||0|||||any******|||| D8||IOBM|IO_L11P_0|UNUSED||0||||||||| -D9|D|IOB|IO_L34P_GCLK19_0|INPUT|LVCMOS25*|0||||NONE||LOCATED|NO|NONE| +D9|C|IOB|IO_L34P_GCLK19_0|INPUT|LVCMOS25*|0||||NONE||LOCATED|NO|NONE| D10|||GND|||||||||||| D11||IOBM|IO_L36P_GCLK15_0|UNUSED||0||||||||| D12||IOBM|IO_L47P_0|UNUSED||0||||||||| diff --git a/ALU.par b/ALU.par index 4b07d80..3adecd5 100755 --- a/ALU.par +++ b/ALU.par @@ -1,7 +1,7 @@ Release 13.3 par O.76xd (nt64) Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. -ECE-PHO115-09:: Wed Feb 15 15:16:04 2012 +ECE-PHO115-08:: Thu Feb 16 19:53:08 2012 par -w -intstyle ise -ol high -mt off ALU_map.ncd ALU.ncd ALU.pcf @@ -36,7 +36,7 @@ Slice Logic Utilization: Number used as Memory: 0 out of 2,176 0% Slice Logic Distribution: - Number of occupied Slices: 5 out of 2,278 1% + Number of occupied Slices: 6 out of 2,278 1% Nummber of MUXCYs used: 0 out of 4,556 0% Number of LUT Flip Flop pairs used: 13 Number with an unused Flip Flop: 13 out of 13 100% @@ -92,9 +92,9 @@ Phase 1 : 67 unrouted; REAL time: 5 secs Phase 2 : 67 unrouted; REAL time: 5 secs -Phase 3 : 49 unrouted; REAL time: 6 secs +Phase 3 : 25 unrouted; REAL time: 6 secs -Phase 4 : 49 unrouted; (Par is working to improve performance) REAL time: 7 secs +Phase 4 : 25 unrouted; (Par is working to improve performance) REAL time: 7 secs Updating file: ALU.ncd with current fully routed design. @@ -129,10 +129,10 @@ Generating Pad Report. All signals are completely routed. -Total REAL time to PAR completion: 19 secs +Total REAL time to PAR completion: 16 secs Total CPU time to PAR completion: 7 secs -Peak Memory Usage: 307 MB +Peak Memory Usage: 308 MB Placer: Placement generated during map. Routing: Completed - No errors found. diff --git a/ALU.pcf b/ALU.pcf index 174c14a..4c41ef8 100755 --- a/ALU.pcf +++ b/ALU.pcf @@ -1,5 +1,5 @@ //! ************************************************************************** -// Written by: Map O.76xd on Wed Feb 15 15:15:59 2012 +// Written by: Map O.76xd on Thu Feb 16 19:53:03 2012 //! ************************************************************************** SCHEMATIC START; @@ -14,10 +14,10 @@ COMP "AN0" LOCATE = SITE "N16" LEVEL 1; COMP "AN1" LOCATE = SITE "N15" LEVEL 1; COMP "AN2" LOCATE = SITE "P18" LEVEL 1; COMP "AN3" LOCATE = SITE "P17" LEVEL 1; -COMP "A" LOCATE = SITE "C9" LEVEL 1; +COMP "A" LOCATE = SITE "C4" LEVEL 1; COMP "B" LOCATE = SITE "B8" LEVEL 1; -COMP "C" LOCATE = SITE "A8" LEVEL 1; -COMP "D" LOCATE = SITE "D9" LEVEL 1; +COMP "C" LOCATE = SITE "D9" LEVEL 1; +COMP "D" LOCATE = SITE "C9" LEVEL 1; COMP "g_out" LOCATE = SITE "L14" LEVEL 1; COMP "a_out" LOCATE = SITE "T17" LEVEL 1; COMP "b_out" LOCATE = SITE "T18" LEVEL 1; diff --git a/ALU.sch b/ALU.sch index 78bc8e1..abd63bb 100755 --- a/ALU.sch +++ b/ALU.sch @@ -1,466 +1,466 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 2012-2-16T0:25:40 - - - - - - - - - - - - 2012-2-16T0:29:51 - - - - - - - - - - - - 2012-2-16T0:44:17 - - - - - - - - - - - - 2000-1-1T10:10:10 - - - - - - - - - - - - - - - - - - - - - 2000-1-1T10:10:10 - - - - - - 2012-2-14T0:35:26 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2012-2-17T0:27:58 + + + + + + + + + + + + 2012-2-17T0:52:15 + + + + + + + + + + + + 2012-2-16T23:54:10 + + + + + + + + + + + + 2000-1-1T10:10:10 + + + + + + + + + + + + + + + + + + + + + 2000-1-1T10:10:10 + + + + + + 2012-2-14T0:35:26 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/ALU.schlog b/ALU.schlog new file mode 100755 index 0000000..e69de29 diff --git a/ALU.sym b/ALU.sym new file mode 100755 index 0000000..3887c25 --- /dev/null +++ b/ALU.sym @@ -0,0 +1,63 @@ + + + BLOCK + 2012-2-16T23:42:30 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ALU.syr b/ALU.syr index 35acf74..c498b8a 100755 --- a/ALU.syr +++ b/ALU.syr @@ -4,13 +4,13 @@ Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. Total REAL time to Xst completion: 0.00 secs -Total CPU time to Xst completion: 0.12 secs +Total CPU time to Xst completion: 0.11 secs --> Parameter xsthdpdir set to xst Total REAL time to Xst completion: 0.00 secs -Total CPU time to Xst completion: 0.13 secs +Total CPU time to Xst completion: 0.11 secs --> Reading design: ALU.prj @@ -105,48 +105,48 @@ Slice Utilization Ratio Delta : 5 ========================================================================= * HDL Parsing * ========================================================================= -Analyzing Verilog file "\\ad\eng\users\m\g\mgabed\My Documents\ec311\lab1\Negate_3.vf" into library work +Analyzing Verilog file "\\ad\eng\users\m\g\mgabed\My Documents\ec311\ec311-lab1\Negate_3.vf" into library work Parsing module . -Analyzing Verilog file "\\ad\eng\users\m\g\mgabed\My Documents\ec311\lab1\Negate_2.vf" into library work +Analyzing Verilog file "\\ad\eng\users\m\g\mgabed\My Documents\ec311\ec311-lab1\Negate_2.vf" into library work Parsing module . -Analyzing Verilog file "\\ad\eng\users\m\g\mgabed\My Documents\ec311\lab1\Negate_1.vf" into library work +Analyzing Verilog file "\\ad\eng\users\m\g\mgabed\My Documents\ec311\ec311-lab1\Negate_1.vf" into library work Parsing module . -Analyzing Verilog file "\\ad\eng\users\m\g\mgabed\My Documents\ec311\lab1\Negate_0.vf" into library work +Analyzing Verilog file "\\ad\eng\users\m\g\mgabed\My Documents\ec311\ec311-lab1\Negate_0.vf" into library work Parsing module . -Analyzing Verilog file "\\ad\eng\users\m\g\mgabed\My Documents\ec311\lab1\Modulo_3.vf" into library work +Analyzing Verilog file "\\ad\eng\users\m\g\mgabed\My Documents\ec311\ec311-lab1\Modulo_3.vf" into library work Parsing module . -Analyzing Verilog file "\\ad\eng\users\m\g\mgabed\My Documents\ec311\lab1\Modulo_1.vf" into library work +Analyzing Verilog file "\\ad\eng\users\m\g\mgabed\My Documents\ec311\ec311-lab1\Modulo_1.vf" into library work Parsing module . -Analyzing Verilog file "\\ad\eng\users\m\g\mgabed\My Documents\ec311\lab1\Modulo_0.vf" into library work +Analyzing Verilog file "\\ad\eng\users\m\g\mgabed\My Documents\ec311\ec311-lab1\Modulo_0.vf" into library work Parsing module . -Analyzing Verilog file "\\ad\eng\users\m\g\mgabed\My Documents\ec311\lab1\Divide_3.vf" into library work +Analyzing Verilog file "\\ad\eng\users\m\g\mgabed\My Documents\ec311\ec311-lab1\Divide_3.vf" into library work Parsing module . -Analyzing Verilog file "\\ad\eng\users\m\g\mgabed\My Documents\ec311\lab1\Divide_2.vf" into library work +Analyzing Verilog file "\\ad\eng\users\m\g\mgabed\My Documents\ec311\ec311-lab1\Divide_2.vf" into library work Parsing module . -Analyzing Verilog file "\\ad\eng\users\m\g\mgabed\My Documents\ec311\lab1\Divide_1.vf" into library work +Analyzing Verilog file "\\ad\eng\users\m\g\mgabed\My Documents\ec311\ec311-lab1\Divide_1.vf" into library work Parsing module . -Analyzing Verilog file "\\ad\eng\users\m\g\mgabed\My Documents\ec311\lab1\Divide_0.vf" into library work +Analyzing Verilog file "\\ad\eng\users\m\g\mgabed\My Documents\ec311\ec311-lab1\Divide_0.vf" into library work Parsing module . -Analyzing Verilog file "\\ad\eng\users\m\g\mgabed\My Documents\ec311\lab1\sev_seg_disp.vf" into library work +Analyzing Verilog file "\\ad\eng\users\m\g\mgabed\My Documents\ec311\ec311-lab1\sev_seg_disp.vf" into library work Parsing module . -Analyzing Verilog file "\\ad\eng\users\m\g\mgabed\My Documents\ec311\lab1\Negate.vf" into library work +Analyzing Verilog file "\\ad\eng\users\m\g\mgabed\My Documents\ec311\ec311-lab1\Negate.vf" into library work Parsing module . Parsing module . Parsing module . Parsing module . Parsing module . -Analyzing Verilog file "\\ad\eng\users\m\g\mgabed\My Documents\ec311\lab1\Modulo.vf" into library work +Analyzing Verilog file "\\ad\eng\users\m\g\mgabed\My Documents\ec311\ec311-lab1\Modulo.vf" into library work Parsing module . Parsing module . Parsing module . Parsing module . -Analyzing Verilog file "\\ad\eng\users\m\g\mgabed\My Documents\ec311\lab1\Divide.vf" into library work +Analyzing Verilog file "\\ad\eng\users\m\g\mgabed\My Documents\ec311\ec311-lab1\Divide.vf" into library work Parsing module . Parsing module . Parsing module . Parsing module . Parsing module . -Analyzing Verilog file "\\ad\eng\users\m\g\mgabed\My Documents\ec311\lab1\ALU.vf" into library work +Analyzing Verilog file "\\ad\eng\users\m\g\mgabed\My Documents\ec311\ec311-lab1\ALU.vf" into library work Parsing module . Parsing module . Parsing module . @@ -187,28 +187,22 @@ Elaborating module . Elaborating module . -Elaborating module . - Elaborating module . -Elaborating module . - Elaborating module . +Elaborating module . + Elaborating module . Elaborating module . Elaborating module . -Elaborating module . +Elaborating module . Elaborating module . -Elaborating module . - -Elaborating module . - Elaborating module . Elaborating module . @@ -217,9 +211,9 @@ Elaborating module . Elaborating module . -Elaborating module . +Elaborating module . -Elaborating module . +Elaborating module . Elaborating module . @@ -231,9 +225,7 @@ Elaborating module . Elaborating module . -Elaborating module . - -Elaborating module . +Elaborating module . Elaborating module . @@ -242,7 +234,7 @@ Elaborating module . ========================================================================= Synthesizing Unit . - Related source file is "//ad/eng/users/m/g/mgabed/my documents/ec311/lab1/alu.vf". + Related source file is "//ad/eng/users/m/g/mgabed/my documents/ec311/ec311-lab1/alu.vf". Set property "HU_SET = XLXI_4_0" for instance . Set property "HU_SET = XLXI_5_1" for instance . Set property "HU_SET = XLXI_6_2" for instance . @@ -252,100 +244,100 @@ Synthesizing Unit . Unit synthesized. Synthesizing Unit . - Related source file is "//ad/eng/users/m/g/mgabed/my documents/ec311/lab1/alu.vf". + Related source file is "//ad/eng/users/m/g/mgabed/my documents/ec311/ec311-lab1/alu.vf". Summary: no macro. Unit synthesized. Synthesizing Unit . - Related source file is "//ad/eng/users/m/g/mgabed/my documents/ec311/lab1/alu.vf". + Related source file is "//ad/eng/users/m/g/mgabed/my documents/ec311/ec311-lab1/alu.vf". Summary: no macro. Unit synthesized. Synthesizing Unit . - Related source file is "//ad/eng/users/m/g/mgabed/my documents/ec311/lab1/alu.vf". + Related source file is "//ad/eng/users/m/g/mgabed/my documents/ec311/ec311-lab1/alu.vf". Summary: no macro. Unit synthesized. Synthesizing Unit . - Related source file is "//ad/eng/users/m/g/mgabed/my documents/ec311/lab1/alu.vf". + Related source file is "//ad/eng/users/m/g/mgabed/my documents/ec311/ec311-lab1/alu.vf". Summary: no macro. Unit synthesized. Synthesizing Unit . - Related source file is "//ad/eng/users/m/g/mgabed/my documents/ec311/lab1/alu.vf". + Related source file is "//ad/eng/users/m/g/mgabed/my documents/ec311/ec311-lab1/alu.vf". WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. Summary: no macro. Unit synthesized. Synthesizing Unit . - Related source file is "//ad/eng/users/m/g/mgabed/my documents/ec311/lab1/alu.vf". + Related source file is "//ad/eng/users/m/g/mgabed/my documents/ec311/ec311-lab1/alu.vf". Summary: no macro. Unit synthesized. Synthesizing Unit . - Related source file is "//ad/eng/users/m/g/mgabed/my documents/ec311/lab1/alu.vf". + Related source file is "//ad/eng/users/m/g/mgabed/my documents/ec311/ec311-lab1/alu.vf". Summary: no macro. Unit synthesized. Synthesizing Unit . - Related source file is "//ad/eng/users/m/g/mgabed/my documents/ec311/lab1/alu.vf". + Related source file is "//ad/eng/users/m/g/mgabed/my documents/ec311/ec311-lab1/alu.vf". Summary: no macro. Unit synthesized. Synthesizing Unit . - Related source file is "//ad/eng/users/m/g/mgabed/my documents/ec311/lab1/alu.vf". + Related source file is "//ad/eng/users/m/g/mgabed/my documents/ec311/ec311-lab1/alu.vf". WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. Summary: no macro. Unit synthesized. Synthesizing Unit . - Related source file is "//ad/eng/users/m/g/mgabed/my documents/ec311/lab1/alu.vf". + Related source file is "//ad/eng/users/m/g/mgabed/my documents/ec311/ec311-lab1/alu.vf". Summary: no macro. Unit synthesized. Synthesizing Unit . - Related source file is "//ad/eng/users/m/g/mgabed/my documents/ec311/lab1/alu.vf". + Related source file is "//ad/eng/users/m/g/mgabed/my documents/ec311/ec311-lab1/alu.vf". Summary: no macro. Unit synthesized. Synthesizing Unit . - Related source file is "//ad/eng/users/m/g/mgabed/my documents/ec311/lab1/alu.vf". + Related source file is "//ad/eng/users/m/g/mgabed/my documents/ec311/ec311-lab1/alu.vf". Summary: no macro. Unit synthesized. Synthesizing Unit . - Related source file is "//ad/eng/users/m/g/mgabed/my documents/ec311/lab1/alu.vf". + Related source file is "//ad/eng/users/m/g/mgabed/my documents/ec311/ec311-lab1/alu.vf". Summary: no macro. Unit synthesized. Synthesizing Unit . - Related source file is "//ad/eng/users/m/g/mgabed/my documents/ec311/lab1/alu.vf". + Related source file is "//ad/eng/users/m/g/mgabed/my documents/ec311/ec311-lab1/alu.vf". Summary: no macro. Unit synthesized. Synthesizing Unit . - Related source file is "//ad/eng/users/m/g/mgabed/my documents/ec311/lab1/alu.vf". + Related source file is "//ad/eng/users/m/g/mgabed/my documents/ec311/ec311-lab1/alu.vf". Found 1-bit 4-to-1 multiplexer for signal created at line 44. Summary: inferred 2 Multiplexer(s). Unit synthesized. Synthesizing Unit . - Related source file is "//ad/eng/users/m/g/mgabed/my documents/ec311/lab1/alu.vf". + Related source file is "//ad/eng/users/m/g/mgabed/my documents/ec311/ec311-lab1/alu.vf". Summary: no macro. Unit synthesized. @@ -381,6 +373,8 @@ Macro Statistics Optimizing unit ... +Optimizing unit ... + Optimizing unit ... Optimizing unit ... @@ -416,29 +410,24 @@ Top Level Output File Name : ALU.ngc Primitive and Black Box Usage: ------------------------------ -# BELS : 125 -# AND2 : 22 +# BELS : 138 +# AND2 : 28 # AND3 : 21 -# AND4 : 2 +# AND4 : 3 # BUF : 4 # GND : 1 -# INV : 45 +# INV : 53 # LUT6 : 4 -# OR2 : 7 -# OR3 : 10 -# OR4 : 4 -# OR5 : 1 +# OR2 : 5 +# OR3 : 9 +# OR4 : 5 +# OR5 : 2 # VCC : 1 -# XNOR2 : 2 +# XNOR2 : 1 # XOR2 : 1 # IO Buffers : 18 # IBUF : 6 # OBUF : 12 -# Logical : 4 -# NAND2 : 1 -# NAND3 : 1 -# NAND4 : 1 -# NOR3 : 1 Device utilization summary: --------------------------- @@ -447,14 +436,14 @@ Selected Device : 6slx16csg324-3 Slice Logic Utilization: - Number of Slice LUTs: 49 out of 9112 0% - Number used as Logic: 49 out of 9112 0% + Number of Slice LUTs: 57 out of 9112 0% + Number used as Logic: 57 out of 9112 0% Slice Logic Distribution: - Number of LUT Flip Flop pairs used: 49 - Number with an unused Flip Flop: 49 out of 49 100% - Number with an unused LUT: 0 out of 49 0% - Number of fully used LUT-FF pairs: 0 out of 49 0% + Number of LUT Flip Flop pairs used: 57 + Number with an unused Flip Flop: 57 out of 57 100% + Number with an unused LUT: 0 out of 57 0% + Number of fully used LUT-FF pairs: 0 out of 57 0% Number of unique control sets: 0 IO Utilization: @@ -494,7 +483,7 @@ Speed Grade: -3 Minimum period: No path found Minimum input arrival time before clock: No path found Maximum output required time after clock: No path found - Maximum combinational path delay: 16.544ns + Maximum combinational path delay: 16.900ns Timing Details: --------------- @@ -502,33 +491,33 @@ All values displayed in nanoseconds (ns) ========================================================================= Timing constraint: Default path analysis - Total number of paths / destination ports: 1495 / 8 + Total number of paths / destination ports: 1539 / 8 ------------------------------------------------------------------------- -Delay: 16.544ns (Levels of Logic = 13) - Source: D (PAD) +Delay: 16.900ns (Levels of Logic = 13) + Source: C (PAD) Destination: d_out (PAD) - Data Path: D to d_out + Data Path: C to d_out Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ - IBUF:I->O 24 1.222 1.172 D_IBUF (D_IBUF) - INV:I->O 1 0.568 0.944 XLXI_1/XLXI_8/XLXI_9 (XLXI_1/XLXI_8/XLXN_17) - AND2:I0->O 1 0.203 0.924 XLXI_1/XLXI_8/XLXI_3 (XLXI_1/XLXI_8/XLXN_1) - OR3:I1->O 1 0.223 0.944 XLXI_1/XLXI_8/XLXI_2 (XLXI_1/XLXI_8/XLXN_2) - AND2:I0->O 1 0.203 0.924 XLXI_1/XLXI_8/XLXI_4 (XLXI_1/XLXI_8/XLXN_4) - OR2:I1->O 1 0.223 0.580 XLXI_1/XLXI_8/XLXI_5 (XLXN_35) - begin scope: 'XLXI_6:D2' - LUT6:I5->O 9 0.205 0.829 Mmux_O11 (O) - end scope: 'XLXI_6:O' - INV:I->O 8 0.568 1.167 XLXI_9/XLXI_39 (XLXI_9/C_BAR) - AND3:I0->O 1 0.203 0.944 XLXI_9/XLXI_51 (XLXI_9/XLXN_114) - OR4:I0->O 1 0.203 0.579 XLXI_9/XLXI_52 (XLXI_9/XLXN_156) + IBUF:I->O 26 1.222 1.206 C_IBUF (C_IBUF) + INV:I->O 1 0.568 0.924 XLXI_2/XLXI_4/XLXI_9 (XLXI_2/XLXI_4/XLXN_15) + AND2:I1->O 1 0.223 0.944 XLXI_2/XLXI_4/XLXI_16 (XLXI_2/XLXI_4/XLXN_14) + OR2:I0->O 1 0.203 0.944 XLXI_2/XLXI_4/XLXI_14 (XLXI_2/XLXI_4/XLXN_1) + AND2:I0->O 1 0.203 0.944 XLXI_2/XLXI_4/XLXI_2 (XLXI_2/XLXI_4/XLXN_4) + OR2:I0->O 1 0.203 0.924 XLXI_2/XLXI_4/XLXI_4 (XLXN_37) + begin scope: 'XLXI_7:D3' + LUT6:I1->O 6 0.203 0.744 Mmux_O11 (O) + end scope: 'XLXI_7:O' + INV:I->O 9 0.568 1.194 XLXI_9/XLXI_40 (XLXI_9/D_BAR) + AND2:I0->O 2 0.203 0.845 XLXI_9/XLXI_48 (XLXI_9/XLXN_125) + OR4:I3->O 1 0.339 0.579 XLXI_9/XLXI_52 (XLXI_9/XLXN_156) INV:I->O 1 0.568 0.579 XLXI_9/XLXI_69 (d_out_OBUF) OBUF:I->O 2.571 d_out_OBUF (d_out) ---------------------------------------- - Total 16.544ns (6.960ns logic, 9.584ns route) - (42.1% logic, 57.9% route) + Total 16.900ns (7.074ns logic, 9.826ns route) + (41.9% logic, 58.1% route) ========================================================================= @@ -539,11 +528,11 @@ Cross Clock Domains Report: Total REAL time to Xst completion: 8.00 secs -Total CPU time to Xst completion: 7.97 secs +Total CPU time to Xst completion: 7.36 secs --> -Total memory usage is 253940 kilobytes +Total memory usage is 252544 kilobytes Number of errors : 0 ( 0 filtered) Number of warnings : 2 ( 0 filtered) diff --git a/ALU.twr b/ALU.twr index 75bdc43..8a0ecd1 100755 --- a/ALU.twr +++ b/ALU.twr @@ -34,65 +34,65 @@ Pad to Pad ---------------+---------------+---------+ Source Pad |Destination Pad| Delay | ---------------+---------------+---------+ -A |a_out | 11.660| -A |b_out | 11.371| -A |c_out | 11.727| -A |d_out | 11.840| -A |e_out | 11.906| -A |f_out | 11.587| -A |g_out | 11.574| -A |sign | 11.406| -B |a_out | 11.326| -B |b_out | 10.895| -B |c_out | 11.387| -B |d_out | 11.931| -B |e_out | 11.927| -B |f_out | 11.342| -B |g_out | 11.489| -B |sign | 11.072| -C |a_out | 11.426| -C |b_out | 11.174| -C |c_out | 11.560| -C |d_out | 11.886| -C |e_out | 11.818| -C |f_out | 11.515| -C |g_out | 11.620| -C |sign | 10.949| -D |a_out | 11.570| -D |b_out | 11.214| -D |c_out | 11.759| -D |d_out | 12.390| -D |e_out | 12.386| -D |f_out | 11.767| -D |g_out | 11.948| -D |sign | 11.316| -S0 |a_out | 11.110| -S0 |b_out | 10.858| -S0 |c_out | 11.214| -S0 |d_out | 11.410| -S0 |e_out | 11.406| -S0 |f_out | 11.074| -S0 |g_out | 11.014| -S0 |sign | 10.662| -S1 |a_out | 10.677| -S1 |b_out | 10.260| -S1 |c_out | 10.664| -S1 |d_out | 11.023| -S1 |e_out | 11.019| -S1 |f_out | 10.545| -S1 |g_out | 10.581| -S1 |sign | 10.423| +A |a_out | 12.121| +A |b_out | 12.114| +A |c_out | 12.193| +A |d_out | 12.977| +A |e_out | 12.603| +A |f_out | 12.193| +A |g_out | 12.222| +A |sign | 11.976| +B |a_out | 11.205| +B |b_out | 11.242| +B |c_out | 11.297| +B |d_out | 11.960| +B |e_out | 11.586| +B |f_out | 11.229| +B |g_out | 11.350| +B |sign | 11.012| +C |a_out | 11.203| +C |b_out | 10.960| +C |c_out | 11.269| +C |d_out | 12.059| +C |e_out | 11.685| +C |f_out | 10.983| +C |g_out | 11.068| +C |sign | 10.766| +D |a_out | 11.544| +D |b_out | 11.218| +D |c_out | 11.615| +D |d_out | 12.400| +D |e_out | 12.026| +D |f_out | 11.410| +D |g_out | 11.394| +D |sign | 11.193| +S0 |a_out | 10.816| +S0 |b_out | 10.961| +S0 |c_out | 10.908| +S0 |d_out | 11.499| +S0 |e_out | 11.125| +S0 |f_out | 10.838| +S0 |g_out | 11.069| +S0 |sign | 10.498| +S1 |a_out | 10.737| +S1 |b_out | 10.588| +S1 |c_out | 10.829| +S1 |d_out | 11.247| +S1 |e_out | 10.873| +S1 |f_out | 10.465| +S1 |g_out | 10.696| +S1 |sign | 10.233| ---------------+---------------+---------+ -Analysis completed Wed Feb 15 15:16:31 2012 +Analysis completed Thu Feb 16 19:53:32 2012 -------------------------------------------------------------------------------- Trace Settings: ------------------------- Trace Settings -Peak Memory Usage: 217 MB +Peak Memory Usage: 230 MB diff --git a/ALU.twx b/ALU.twx index b395950..b90cdc4 100755 --- a/ALU.twx +++ b/ALU.twx @@ -332,7 +332,7 @@ Release 13.3 Trace (nt64)Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.C:\Xilinx\13.3\ISE_DS\ISE\bin\nt64\unwrapped\trce.exe -intstyle ise -v 3 -s 3 -n 3 -fastpaths -xml ALU.twx ALU.ncd -o ALU.twr ALU.pcf -ucf ALU.ucf -ALU.ncdALU.ncdALU.pcfALU.pcfxc6slx16C-3PRODUCTION 1.20 2011-10-0313INFO:Timing:2698 - No timing constraints found, doing default enumeration.INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report.INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet.Aa_out11.660Ab_out11.371Ac_out11.727Ad_out11.840Ae_out11.906Af_out11.587Ag_out11.574Asign11.406Ba_out11.326Bb_out10.895Bc_out11.387Bd_out11.931Be_out11.927Bf_out11.342Bg_out11.489Bsign11.072Ca_out11.426Cb_out11.174Cc_out11.560Cd_out11.886Ce_out11.818Cf_out11.515Cg_out11.620Csign10.949Da_out11.570Db_out11.214Dc_out11.759Dd_out12.390De_out12.386Df_out11.767Dg_out11.948Dsign11.316S0a_out11.110S0b_out10.858S0c_out11.214S0d_out11.410S0e_out11.406S0f_out11.074S0g_out11.014S0sign10.662S1a_out10.677S1b_out10.260S1c_out10.664S1d_out11.023S1e_out11.019S1f_out10.545S1g_out10.581S1sign10.423Wed Feb 15 15:16:31 2012 TraceTrace Settings +ALU.ncdALU.ncdALU.pcfALU.pcfxc6slx16C-3PRODUCTION 1.20 2011-10-0313INFO:Timing:2698 - No timing constraints found, doing default enumeration.INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report.INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet.Aa_out12.121Ab_out12.114Ac_out12.193Ad_out12.977Ae_out12.603Af_out12.193Ag_out12.222Asign11.976Ba_out11.205Bb_out11.242Bc_out11.297Bd_out11.960Be_out11.586Bf_out11.229Bg_out11.350Bsign11.012Ca_out11.203Cb_out10.960Cc_out11.269Cd_out12.059Ce_out11.685Cf_out10.983Cg_out11.068Csign10.766Da_out11.544Db_out11.218Dc_out11.615Dd_out12.400De_out12.026Df_out11.410Dg_out11.394Dsign11.193S0a_out10.816S0b_out10.961S0c_out10.908S0d_out11.499S0e_out11.125S0f_out10.838S0g_out11.069S0sign10.498S1a_out10.737S1b_out10.588S1c_out10.829S1d_out11.247S1e_out10.873S1f_out10.465S1g_out10.696S1sign10.233Thu Feb 16 19:53:32 2012 TraceTrace Settings -Peak Memory Usage: 217 MB +Peak Memory Usage: 230 MB diff --git a/ALU.ucf b/ALU.ucf index 20b494d..0393728 100755 --- a/ALU.ucf +++ b/ALU.ucf @@ -1,14 +1,13 @@ -# PlanAhead Generated physical constraints -NET "A" LOC = C9; +NET "A" LOC = C4; NET "AN0" LOC = N16; NET "AN1" LOC = N15; NET "AN2" LOC = P18; NET "AN3" LOC = P17; NET "B" LOC = B8; -NET "C" LOC = A8; -NET "D" LOC = D9; +NET "C" LOC = D9; +NET "D" LOC = C9; NET "S0" LOC = T9; NET "S1" LOC = T10; NET "a_out" LOC = T17; diff --git a/ALU.unroutes b/ALU.unroutes index 404a047..6cfcf65 100755 --- a/ALU.unroutes +++ b/ALU.unroutes @@ -1,7 +1,7 @@ Release 13.3 - par O.76xd (nt64) Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. -Wed Feb 15 15:16:23 2012 +Thu Feb 16 19:53:25 2012 All signals are completely routed. diff --git a/ALU.vf b/ALU.vf index a99f305..d4c14ec 100755 --- a/ALU.vf +++ b/ALU.vf @@ -7,11 +7,11 @@ // \ \ \/ Version : 13.3 // \ \ Application : sch2hdl // / / Filename : ALU.vf -// /___/ /\ Timestamp : 02/15/2012 15:00:05 +// /___/ /\ Timestamp : 02/16/2012 19:52:33 // \ \ / \ // \___\/\___\ // -//Command: sch2hdl -intstyle ise -family spartan6 -verilog "X:/My Documents/ec311/lab1/ALU.vf" -w "X:/My Documents/ec311/lab1/ALU.sch" +//Command: sch2hdl -intstyle ise -family spartan6 -verilog "X:/My Documents/ec311/ec311-lab1/ALU.vf" -w "X:/My Documents/ec311/ec311-lab1/ALU.sch" //Design Name: ALU //Device: spartan6 //Purpose: @@ -282,17 +282,17 @@ module Negate_3_MUSER_ALU(b0, output result; wire XLXN_8; - wire XLXN_9; + wire XLXN_10; - OR3 XLXI_5 (.I0(b2), - .I1(b1), - .I2(b0), - .O(XLXN_9)); - NAND2 XLXI_9 (.I0(XLXN_8), - .I1(b3), - .O(result)); - INV XLXI_12 (.I(XLXN_9), + OR3 XLXI_14 (.I0(b2), + .I1(b1), + .I2(b0), .O(XLXN_8)); + INV XLXI_15 (.I(b3), + .O(XLXN_10)); + AND2 XLXI_16 (.I0(XLXN_8), + .I1(XLXN_10), + .O(result)); endmodule `timescale 1ns / 1ps @@ -350,33 +350,38 @@ module Negate_2_MUSER_ALU(b0, input b3; output result; - wire XLXN_7; - wire XLXN_9; - wire XLXN_10; - wire XLXN_12; - wire XLXN_16; - wire XLXN_17; - - AND2 XLXI_1 (.I0(XLXN_7), - .I1(b3), - .O(XLXN_9)); - AND3 XLXI_2 (.I0(b2), - .I1(XLXN_16), - .I2(XLXN_17), - .O(XLXN_10)); - OR2 XLXI_3 (.I0(XLXN_10), - .I1(XLXN_9), + wire XLXN_35; + wire XLXN_37; + wire XLXN_40; + wire XLXN_41; + wire XLXN_44; + wire XLXN_47; + wire XLXN_49; + + OR4 XLXI_8 (.I0(XLXN_37), + .I1(XLXN_41), + .I2(XLXN_40), + .I3(XLXN_35), .O(result)); - OR3 XLXI_4 (.I0(XLXN_12), - .I1(b1), - .I2(b0), - .O(XLXN_7)); - INV XLXI_5 (.I(b2), - .O(XLXN_12)); - INV XLXI_6 (.I(b1), - .O(XLXN_16)); - INV XLXI_7 (.I(b0), - .O(XLXN_17)); + AND2 XLXI_9 (.I0(XLXN_44), + .I1(b3), + .O(XLXN_35)); + AND2 XLXI_10 (.I0(b1), + .I1(XLXN_44), + .O(XLXN_41)); + AND2 XLXI_11 (.I0(b0), + .I1(XLXN_44), + .O(XLXN_40)); + INV XLXI_14 (.I(b2), + .O(XLXN_44)); + AND3 XLXI_15 (.I0(XLXN_47), + .I1(XLXN_49), + .I2(b2), + .O(XLXN_37)); + INV XLXI_16 (.I(b1), + .O(XLXN_49)); + INV XLXI_17 (.I(b0), + .O(XLXN_47)); endmodule `timescale 1ns / 1ps @@ -467,23 +472,40 @@ module Modulo_0_MUSER_ALU(b0, wire XLXN_1; wire XLXN_3; wire XLXN_4; - wire XLXN_5; + wire XLXN_12; + wire XLXN_14; + wire XLXN_15; + wire XLXN_16; + wire XLXN_27; + wire XLXN_28; - XNOR2 XLXI_1 (.I0(b0), - .I1(b1), - .O(XLXN_1)); AND2 XLXI_2 (.I0(XLXN_1), .I1(b2), .O(XLXN_4)); - NAND3 XLXI_3 (.I0(XLXN_5), - .I1(b1), - .I2(b2), - .O(XLXN_3)); OR2 XLXI_4 (.I0(XLXN_4), .I1(XLXN_3), .O(result)); - INV XLXI_5 (.I(b0), - .O(XLXN_5)); + INV XLXI_9 (.I(b1), + .O(XLXN_15)); + INV XLXI_10 (.I(b0), + .O(XLXN_16)); + AND3 XLXI_11 (.I0(b0), + .I1(XLXN_28), + .I2(XLXN_27), + .O(XLXN_3)); + INV XLXI_12 (.I(b2), + .O(XLXN_27)); + INV XLXI_13 (.I(b1), + .O(XLXN_28)); + OR2 XLXI_14 (.I0(XLXN_14), + .I1(XLXN_12), + .O(XLXN_1)); + AND2 XLXI_15 (.I0(b0), + .I1(b1), + .O(XLXN_12)); + AND2 XLXI_16 (.I0(XLXN_16), + .I1(XLXN_15), + .O(XLXN_14)); endmodule `timescale 1ns / 1ps @@ -499,24 +521,24 @@ module Modulo_1_MUSER_ALU(b0, input b3; output result; - wire XLXN_1; wire XLXN_2; wire XLXN_3; wire XLXN_5; wire XLXN_6; wire XLXN_7; - wire XLXN_18; - wire XLXN_19; - wire XLXN_20; - wire XLXN_21; - wire XLXN_22; wire XLXN_23; wire XLXN_24; + wire XLXN_50; + wire XLXN_51; + wire XLXN_54; + wire XLXN_55; + wire XLXN_56; + wire XLXN_57; AND3 XLXI_1 (.I0(b1), .I1(b2), .I2(b3), - .O(XLXN_1)); + .O(XLXN_55)); AND3 XLXI_2 (.I0(XLXN_6), .I1(XLXN_5), .I2(b3), @@ -525,38 +547,38 @@ module Modulo_1_MUSER_ALU(b0, .I1(XLXN_7), .I2(b3), .O(XLXN_3)); - OR3 XLXI_4 (.I0(XLXN_3), - .I1(XLXN_2), - .I2(XLXN_1), - .O(XLXN_21)); INV XLXI_5 (.I(b1), .O(XLXN_5)); INV XLXI_6 (.I(b0), .O(XLXN_6)); INV XLXI_7 (.I(b2), .O(XLXN_7)); - OR2 XLXI_9 (.I0(XLXN_20), - .I1(XLXN_21), - .O(result)); AND4 XLXI_11 (.I0(b0), .I1(XLXN_24), .I2(b2), .I3(XLXN_23), - .O(XLXN_19)); - OR2 XLXI_12 (.I0(XLXN_19), - .I1(XLXN_18), - .O(XLXN_20)); - NAND4 XLXI_13 (.I0(b0), - .I1(XLXN_22), - .I2(b2), - .I3(b3), - .O(XLXN_18)); - INV XLXI_14 (.I(b1), - .O(XLXN_22)); + .O(XLXN_57)); INV XLXI_15 (.I(b3), .O(XLXN_23)); INV XLXI_16 (.I(b1), .O(XLXN_24)); + AND4 XLXI_18 (.I0(XLXN_54), + .I1(b1), + .I2(XLXN_50), + .I3(XLXN_51), + .O(XLXN_56)); + INV XLXI_19 (.I(b2), + .O(XLXN_50)); + INV XLXI_20 (.I(b3), + .O(XLXN_51)); + INV XLXI_21 (.I(b0), + .O(XLXN_54)); + OR5 XLXI_22 (.I0(XLXN_57), + .I1(XLXN_56), + .I2(XLXN_3), + .I3(XLXN_2), + .I4(XLXN_55), + .O(result)); endmodule `timescale 1ns / 1ps @@ -708,25 +730,24 @@ module Divide_2_MUSER_ALU(b0, input b3; output result; - wire XLXN_1; - wire XLXN_2; - wire XLXN_3; - wire XLXN_7; + wire XLXN_9; + wire XLXN_13; + wire XLXN_14; + wire XLXN_15; - OR3 XLXI_1 (.I0(XLXN_1), - .I1(XLXN_7), - .I2(XLXN_3), - .O(result)); - AND3 XLXI_2 (.I0(XLXN_2), - .I1(b3), - .I2(b1), - .O(XLXN_1)); - INV XLXI_3 (.I(b2), - .O(XLXN_2)); - INV XLXI_4 (.I(b0), - .O(XLXN_3)); - INV XLXI_9 (.I(b1), - .O(XLXN_7)); + AND2 XLXI_10 (.I0(XLXN_9), + .I1(b3), + .O(result)); + OR3 XLXI_12 (.I0(XLXN_15), + .I1(XLXN_14), + .I2(XLXN_13), + .O(XLXN_9)); + INV XLXI_13 (.I(b0), + .O(XLXN_13)); + INV XLXI_15 (.I(b1), + .O(XLXN_14)); + INV XLXI_16 (.I(b2), + .O(XLXN_15)); endmodule `timescale 1ns / 1ps @@ -743,14 +764,23 @@ module Divide_3_MUSER_ALU(b0, output result; wire XLXN_2; + wire XLXN_13; + wire XLXN_14; + wire XLXN_15; AND2 XLXI_2 (.I0(XLXN_2), .I1(b3), .O(result)); - NOR3 XLXI_3 (.I0(b0), - .I1(b1), - .I2(b2), - .O(XLXN_2)); + OR3 XLXI_4 (.I0(XLXN_15), + .I1(XLXN_14), + .I2(XLXN_13), + .O(XLXN_2)); + INV XLXI_6 (.I(b2), + .O(XLXN_13)); + INV XLXI_7 (.I(b1), + .O(XLXN_14)); + INV XLXI_8 (.I(b0), + .O(XLXN_15)); endmodule `timescale 1ns / 1ps @@ -766,25 +796,23 @@ module Divide_0_MUSER_ALU(b0, input b3; output result; - wire XLXN_1; wire XLXN_2; wire XLXN_3; wire XLXN_4; wire XLXN_5; wire XLXN_6; + wire XLXN_12; - AND3 XLXI_1 (.I0(b3), + AND3 XLXI_1 (.I0(b0), .I1(b3), .I2(XLXN_2), .O(XLXN_5)); AND2 XLXI_2 (.I0(b1), - .I1(XLXN_1), + .I1(XLXN_12), .O(XLXN_4)); AND2 XLXI_3 (.I0(b1), .I1(XLXN_3), .O(XLXN_6)); - INV XLXI_4 (.I(b3), - .O(XLXN_1)); INV XLXI_5 (.I(b1), .O(XLXN_2)); INV XLXI_6 (.I(b0), @@ -793,6 +821,8 @@ module Divide_0_MUSER_ALU(b0, .I1(XLXN_5), .I2(XLXN_4), .O(result)); + INV XLXI_9 (.I(b3), + .O(XLXN_12)); endmodule `timescale 1ns / 1ps @@ -830,10 +860,10 @@ module Divide_MUSER_ALU(b0, .b2(b2), .b3(b3), .result(out3)); - Divide_0_MUSER_ALU XLXI_12 (.b0(b1), - .b1(b2), + Divide_0_MUSER_ALU XLXI_12 (.b0(b0), + .b1(b1), .b2(b2), - .b3(b0), + .b3(b3), .result(out0)); endmodule `timescale 1ns / 1ps @@ -881,10 +911,6 @@ module ALU(A, wire XLXN_23; wire XLXN_24; wire XLXN_25; - wire XLXN_26; - wire XLXN_27; - wire XLXN_28; - wire XLXN_31; wire XLXN_33; wire XLXN_34; wire XLXN_35; @@ -893,6 +919,10 @@ module ALU(A, wire XLXN_38; wire XLXN_39; wire XLXN_41; + wire XLXN_42; + wire XLXN_43; + wire XLXN_44; + wire XLXN_45; Divide_MUSER_ALU XLXI_1 (.b0(D), .b1(C), @@ -914,13 +944,13 @@ module ALU(A, .b1(C), .b2(B), .b3(A), - .out0(XLXN_27), - .out1(XLXN_28), - .out2(XLXN_31), - .out3(XLXN_26)); + .out0(XLXN_42), + .out1(XLXN_43), + .out2(XLXN_44), + .out3(XLXN_45)); (* HU_SET = "XLXI_4_0" *) M4_1E_HXILINX_ALU XLXI_4 (.D0(A), - .D1(XLXN_26), + .D1(XLXN_45), .D2(XLXN_33), .D3(XLXN_41), .E(XLXN_12), @@ -929,7 +959,7 @@ module ALU(A, .O(XLXN_22)); (* HU_SET = "XLXI_5_1" *) M4_1E_HXILINX_ALU XLXI_5 (.D0(B), - .D1(XLXN_27), + .D1(XLXN_44), .D2(XLXN_34), .D3(XLXN_39), .E(XLXN_12), @@ -938,7 +968,7 @@ module ALU(A, .O(XLXN_23)); (* HU_SET = "XLXI_6_2" *) M4_1E_HXILINX_ALU XLXI_6 (.D0(C), - .D1(XLXN_28), + .D1(XLXN_43), .D2(XLXN_35), .D3(XLXN_38), .E(XLXN_12), @@ -947,7 +977,7 @@ module ALU(A, .O(XLXN_24)); (* HU_SET = "XLXI_7_3" *) M4_1E_HXILINX_ALU XLXI_7 (.D0(D), - .D1(XLXN_31), + .D1(XLXN_42), .D2(XLXN_36), .D3(XLXN_37), .E(XLXN_12), diff --git a/ALU_bitgen.xwbt b/ALU_bitgen.xwbt index f3acff2..78a0bc1 100755 --- a/ALU_bitgen.xwbt +++ b/ALU_bitgen.xwbt @@ -1,8 +1,8 @@ INTSTYLE=ise -INFILE=X:\My Documents\ec311\lab1\ALU.ncd -OUTFILE=X:\My Documents\ec311\lab1\ALU.bit +INFILE=X:\My Documents\ec311\ec311-lab1\ALU.ncd +OUTFILE=X:\My Documents\ec311\ec311-lab1\ALU.bit FAMILY=Spartan6 PART=xc6slx16-3csg324 -WORKINGDIR=X:\My Documents\ec311\lab1 +WORKINGDIR=X:\My Documents\ec311\ec311-lab1 LICENSE=ISE USER_INFO=__174135685_174135686_174419191 diff --git a/ALU_envsettings.html b/ALU_envsettings.html index 2c65f7c..109e8da 100644 --- a/ALU_envsettings.html +++ b/ALU_envsettings.html @@ -14,53 +14,53 @@ par -PATH -C:
\Xilinx\13.3\ISE_DS\ISE\\lib\nt64;C:
\Xilinx\13.3\ISE_DS\ISE\\bin\nt64;C:
\Xilinx\13.3\ISE_DS\PlanAhead\bin;C:
\Xilinx\13.3\ISE_DS\ISE\bin\nt64;C:
\Xilinx\13.3\ISE_DS\ISE\lib\nt64;C:
\Xilinx\13.3\ISE_DS\EDK\bin\nt64;C:
\Xilinx\13.3\ISE_DS\EDK\lib\nt64;C:
\Xilinx\13.3\ISE_DS\EDK\gnu\microblaze\nt64\bin;C:
\Xilinx\13.3\ISE_DS\EDK\gnu\powerpc-eabi\nt64\bin;C:
\Xilinx\13.3\ISE_DS\EDK\gnuwin\bin;C:
\Xilinx\13.3\ISE_DS\common\bin\nt64;C:
\Xilinx\13.3\ISE_DS\common\lib\nt64;C:
\Windows\system32;C:
\Windows;C:
\Windows\System32\Wbem;C:
\Windows\System32\WindowsPowerShell\v1.0\;C:
\Program Files\MATLAB\R2011a\runtime\win64;C:
\Program Files\MATLAB\R2011a\bin;C:
\VXIPNP\WinNT\Bin;C:
\Program Files (x86)\Altium Designer Summer 09\System;C:
\Program Files (x86)\QuickTime\QTSystem\;C:
\Program Files\NetBeans 7.0.1\java\ant\bin;C:
\Program Files\Java\jdk1.6.0_27\bin;C:
\Program Files\TortoiseSVN\bin;C:
\Program Files (x86)\Rational\Rose RealTime\bin\win32;C:
\Program Files (x86)\Rational\common;C:
\Cadence\SPB_16.5\OpenAccess\bin\win32\opt;C:
\Cadence\SPB_16.5\tools\Capture;C:
\Cadence\SPB_16.5\tools\PSpice\Library;C:
\Cadence\SPB_16.5\tools\PSpice;C:
\Cadence\SPB_16.5\tools\specctra\bin;C:
\Cadence\SPB_16.5\tools\fet\bin;C:
\Cadence\SPB_16.5\tools\libutil\bin;C:
\Cadence\SPB_16.5\tools\bin;C:
\Cadence\SPB_16.5\tools\pcb\bin -C:
\Xilinx\13.3\ISE_DS\ISE\\lib\nt64;C:
\Xilinx\13.3\ISE_DS\ISE\\bin\nt64;C:
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\Xilinx\13.3\ISE_DS\common\lib\nt64;C:
\Windows\system32;C:
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\Windows\System32\Wbem;C:
\Windows\System32\WindowsPowerShell\v1.0\;C:
\Program Files\MATLAB\R2011a\runtime\win64;C:
\Program Files\MATLAB\R2011a\bin;C:
\VXIPNP\WinNT\Bin;C:
\Program Files (x86)\Altium Designer Summer 09\System;C:
\Program Files (x86)\QuickTime\QTSystem\;C:
\Program Files\NetBeans 7.0.1\java\ant\bin;C:
\Program Files\Java\jdk1.6.0_27\bin;C:
\Program Files\TortoiseSVN\bin;C:
\Program Files (x86)\Rational\Rose RealTime\bin\win32;C:
\Program Files (x86)\Rational\common;C:
\Cadence\SPB_16.5\OpenAccess\bin\win32\opt;C:
\Cadence\SPB_16.5\tools\Capture;C:
\Cadence\SPB_16.5\tools\PSpice\Library;C:
\Cadence\SPB_16.5\tools\PSpice;C:
\Cadence\SPB_16.5\tools\specctra\bin;C:
\Cadence\SPB_16.5\tools\fet\bin;C:
\Cadence\SPB_16.5\tools\libutil\bin;C:
\Cadence\SPB_16.5\tools\bin;C:
\Cadence\SPB_16.5\tools\pcb\bin -C:
\Xilinx\13.3\ISE_DS\ISE\\lib\nt64;C:
\Xilinx\13.3\ISE_DS\ISE\\bin\nt64;C:
\Xilinx\13.3\ISE_DS\PlanAhead\bin;C:
\Xilinx\13.3\ISE_DS\ISE\bin\nt64;C:
\Xilinx\13.3\ISE_DS\ISE\lib\nt64;C:
\Xilinx\13.3\ISE_DS\EDK\bin\nt64;C:
\Xilinx\13.3\ISE_DS\EDK\lib\nt64;C:
\Xilinx\13.3\ISE_DS\EDK\gnu\microblaze\nt64\bin;C:
\Xilinx\13.3\ISE_DS\EDK\gnu\powerpc-eabi\nt64\bin;C:
\Xilinx\13.3\ISE_DS\EDK\gnuwin\bin;C:
\Xilinx\13.3\ISE_DS\common\bin\nt64;C:
\Xilinx\13.3\ISE_DS\common\lib\nt64;C:
\Windows\system32;C:
\Windows;C:
\Windows\System32\Wbem;C:
\Windows\System32\WindowsPowerShell\v1.0\;C:
\Program Files\MATLAB\R2011a\runtime\win64;C:
\Program Files\MATLAB\R2011a\bin;C:
\VXIPNP\WinNT\Bin;C:
\Program Files (x86)\Altium Designer Summer 09\System;C:
\Program Files (x86)\QuickTime\QTSystem\;C:
\Program Files\NetBeans 7.0.1\java\ant\bin;C:
\Program Files\Java\jdk1.6.0_27\bin;C:
\Program Files\TortoiseSVN\bin;C:
\Program Files (x86)\Rational\Rose RealTime\bin\win32;C:
\Program Files (x86)\Rational\common;C:
\Cadence\SPB_16.5\OpenAccess\bin\win32\opt;C:
\Cadence\SPB_16.5\tools\Capture;C:
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\Cadence\SPB_16.5\tools\libutil\bin;C:
\Cadence\SPB_16.5\tools\bin;C:
\Cadence\SPB_16.5\tools\pcb\bin -C:
\Xilinx\13.3\ISE_DS\ISE\\lib\nt64;C:
\Xilinx\13.3\ISE_DS\ISE\\bin\nt64;C:
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\Xilinx\13.3\ISE_DS\common\bin\nt64;C:
\Xilinx\13.3\ISE_DS\common\lib\nt64;C:
\Windows\system32;C:
\Windows;C:
\Windows\System32\Wbem;C:
\Windows\System32\WindowsPowerShell\v1.0\;C:
\Program Files\MATLAB\R2011a\runtime\win64;C:
\Program Files\MATLAB\R2011a\bin;C:
\VXIPNP\WinNT\Bin;C:
\Program Files (x86)\Altium Designer Summer 09\System;C:
\Program Files (x86)\QuickTime\QTSystem\;C:
\Program Files\NetBeans 7.0.1\java\ant\bin;C:
\Program Files\Java\jdk1.6.0_27\bin;C:
\Program Files\TortoiseSVN\bin;C:
\Program Files (x86)\Rational\Rose RealTime\bin\win32;C:
\Program Files (x86)\Rational\common;C:
\Cadence\SPB_16.5\OpenAccess\bin\win32\opt;C:
\Cadence\SPB_16.5\tools\Capture;C:
\Cadence\SPB_16.5\tools\PSpice\Library;C:
\Cadence\SPB_16.5\tools\PSpice;C:
\Cadence\SPB_16.5\tools\specctra\bin;C:
\Cadence\SPB_16.5\tools\fet\bin;C:
\Cadence\SPB_16.5\tools\libutil\bin;C:
\Cadence\SPB_16.5\tools\bin;C:
\Cadence\SPB_16.5\tools\pcb\bin +PATHEXT +.COM;
.EXE;
.BAT;
.CMD;
.VBS;
.VBE;
.JS;
.JSE;
.WSF;
.WSH;
.MSC +.COM;
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.CMD;
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.MSC +.COM;
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.MSC +.COM;
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.MSC -PATHEXT -.COM;.EXE;.BAT;.CMD;.VBS;.VBE;.JS;.JSE;.WSF;.WSH;.MSC -.COM;.EXE;.BAT;.CMD;.VBS;.VBE;.JS;.JSE;.WSF;.WSH;.MSC -.COM;.EXE;.BAT;.CMD;.VBS;.VBE;.JS;.JSE;.WSF;.WSH;.MSC -.COM;.EXE;.BAT;.CMD;.VBS;.VBE;.JS;.JSE;.WSF;.WSH;.MSC +Path +C:\Xilinx\13.3\ISE_DS\ISE\\lib\nt64;
C:\Xilinx\13.3\ISE_DS\ISE\\bin\nt64;
C:\Xilinx\13.3\ISE_DS\PlanAhead\bin;
C:\Xilinx\13.3\ISE_DS\ISE\bin\nt64;
C:\Xilinx\13.3\ISE_DS\ISE\lib\nt64;
C:\Xilinx\13.3\ISE_DS\EDK\bin\nt64;
C:\Xilinx\13.3\ISE_DS\EDK\lib\nt64;
C:\Xilinx\13.3\ISE_DS\EDK\gnu\microblaze\nt64\bin;
C:\Xilinx\13.3\ISE_DS\EDK\gnu\powerpc-eabi\nt64\bin;
C:\Xilinx\13.3\ISE_DS\EDK\gnuwin\bin;
C:\Xilinx\13.3\ISE_DS\common\bin\nt64;
C:\Xilinx\13.3\ISE_DS\common\lib\nt64;
C:\Windows\system32;
C:\Windows;
C:\Windows\System32\Wbem;
C:\Windows\System32\WindowsPowerShell\v1.0\;
C:\Program Files\MATLAB\R2011a\runtime\win64;
C:\Program Files\MATLAB\R2011a\bin;
C:\VXIPNP\WinNT\Bin;
C:\Program Files (x86)\Altium Designer Summer 09\System;
C:\Program Files (x86)\QuickTime\QTSystem\;
C:\Program Files\NetBeans 7.0.1\java\ant\bin;
C:\Program Files\Java\jdk1.6.0_27\bin;
C:\Program Files\TortoiseSVN\bin;
C:\Program Files (x86)\Rational\Rose RealTime\bin\win32;
C:\Program Files (x86)\Rational\common;
C:\Cadence\SPB_16.5\OpenAccess\bin\win32\opt;
C:\Cadence\SPB_16.5\tools\Capture;
C:\Cadence\SPB_16.5\tools\PSpice\Library;
C:\Cadence\SPB_16.5\tools\PSpice;
C:\Cadence\SPB_16.5\tools\specctra\bin;
C:\Cadence\SPB_16.5\tools\fet\bin;
C:\Cadence\SPB_16.5\tools\libutil\bin;
C:\Cadence\SPB_16.5\tools\bin;
C:\Cadence\SPB_16.5\tools\pcb\bin +C:\Xilinx\13.3\ISE_DS\ISE\\lib\nt64;
C:\Xilinx\13.3\ISE_DS\ISE\\bin\nt64;
C:\Xilinx\13.3\ISE_DS\PlanAhead\bin;
C:\Xilinx\13.3\ISE_DS\ISE\bin\nt64;
C:\Xilinx\13.3\ISE_DS\ISE\lib\nt64;
C:\Xilinx\13.3\ISE_DS\EDK\bin\nt64;
C:\Xilinx\13.3\ISE_DS\EDK\lib\nt64;
C:\Xilinx\13.3\ISE_DS\EDK\gnu\microblaze\nt64\bin;
C:\Xilinx\13.3\ISE_DS\EDK\gnu\powerpc-eabi\nt64\bin;
C:\Xilinx\13.3\ISE_DS\EDK\gnuwin\bin;
C:\Xilinx\13.3\ISE_DS\common\bin\nt64;
C:\Xilinx\13.3\ISE_DS\common\lib\nt64;
C:\Windows\system32;
C:\Windows;
C:\Windows\System32\Wbem;
C:\Windows\System32\WindowsPowerShell\v1.0\;
C:\Program Files\MATLAB\R2011a\runtime\win64;
C:\Program Files\MATLAB\R2011a\bin;
C:\VXIPNP\WinNT\Bin;
C:\Program Files (x86)\Altium Designer Summer 09\System;
C:\Program Files (x86)\QuickTime\QTSystem\;
C:\Program Files\NetBeans 7.0.1\java\ant\bin;
C:\Program Files\Java\jdk1.6.0_27\bin;
C:\Program Files\TortoiseSVN\bin;
C:\Program Files (x86)\Rational\Rose RealTime\bin\win32;
C:\Program Files (x86)\Rational\common;
C:\Cadence\SPB_16.5\OpenAccess\bin\win32\opt;
C:\Cadence\SPB_16.5\tools\Capture;
C:\Cadence\SPB_16.5\tools\PSpice\Library;
C:\Cadence\SPB_16.5\tools\PSpice;
C:\Cadence\SPB_16.5\tools\specctra\bin;
C:\Cadence\SPB_16.5\tools\fet\bin;
C:\Cadence\SPB_16.5\tools\libutil\bin;
C:\Cadence\SPB_16.5\tools\bin;
C:\Cadence\SPB_16.5\tools\pcb\bin +C:\Xilinx\13.3\ISE_DS\ISE\\lib\nt64;
C:\Xilinx\13.3\ISE_DS\ISE\\bin\nt64;
C:\Xilinx\13.3\ISE_DS\PlanAhead\bin;
C:\Xilinx\13.3\ISE_DS\ISE\bin\nt64;
C:\Xilinx\13.3\ISE_DS\ISE\lib\nt64;
C:\Xilinx\13.3\ISE_DS\EDK\bin\nt64;
C:\Xilinx\13.3\ISE_DS\EDK\lib\nt64;
C:\Xilinx\13.3\ISE_DS\EDK\gnu\microblaze\nt64\bin;
C:\Xilinx\13.3\ISE_DS\EDK\gnu\powerpc-eabi\nt64\bin;
C:\Xilinx\13.3\ISE_DS\EDK\gnuwin\bin;
C:\Xilinx\13.3\ISE_DS\common\bin\nt64;
C:\Xilinx\13.3\ISE_DS\common\lib\nt64;
C:\Windows\system32;
C:\Windows;
C:\Windows\System32\Wbem;
C:\Windows\System32\WindowsPowerShell\v1.0\;
C:\Program Files\MATLAB\R2011a\runtime\win64;
C:\Program Files\MATLAB\R2011a\bin;
C:\VXIPNP\WinNT\Bin;
C:\Program Files (x86)\Altium Designer Summer 09\System;
C:\Program Files (x86)\QuickTime\QTSystem\;
C:\Program Files\NetBeans 7.0.1\java\ant\bin;
C:\Program Files\Java\jdk1.6.0_27\bin;
C:\Program Files\TortoiseSVN\bin;
C:\Program Files (x86)\Rational\Rose RealTime\bin\win32;
C:\Program Files (x86)\Rational\common;
C:\Cadence\SPB_16.5\OpenAccess\bin\win32\opt;
C:\Cadence\SPB_16.5\tools\Capture;
C:\Cadence\SPB_16.5\tools\PSpice\Library;
C:\Cadence\SPB_16.5\tools\PSpice;
C:\Cadence\SPB_16.5\tools\specctra\bin;
C:\Cadence\SPB_16.5\tools\fet\bin;
C:\Cadence\SPB_16.5\tools\libutil\bin;
C:\Cadence\SPB_16.5\tools\bin;
C:\Cadence\SPB_16.5\tools\pcb\bin +C:\Xilinx\13.3\ISE_DS\ISE\\lib\nt64;
C:\Xilinx\13.3\ISE_DS\ISE\\bin\nt64;
C:\Xilinx\13.3\ISE_DS\PlanAhead\bin;
C:\Xilinx\13.3\ISE_DS\ISE\bin\nt64;
C:\Xilinx\13.3\ISE_DS\ISE\lib\nt64;
C:\Xilinx\13.3\ISE_DS\EDK\bin\nt64;
C:\Xilinx\13.3\ISE_DS\EDK\lib\nt64;
C:\Xilinx\13.3\ISE_DS\EDK\gnu\microblaze\nt64\bin;
C:\Xilinx\13.3\ISE_DS\EDK\gnu\powerpc-eabi\nt64\bin;
C:\Xilinx\13.3\ISE_DS\EDK\gnuwin\bin;
C:\Xilinx\13.3\ISE_DS\common\bin\nt64;
C:\Xilinx\13.3\ISE_DS\common\lib\nt64;
C:\Windows\system32;
C:\Windows;
C:\Windows\System32\Wbem;
C:\Windows\System32\WindowsPowerShell\v1.0\;
C:\Program Files\MATLAB\R2011a\runtime\win64;
C:\Program Files\MATLAB\R2011a\bin;
C:\VXIPNP\WinNT\Bin;
C:\Program Files (x86)\Altium Designer Summer 09\System;
C:\Program Files (x86)\QuickTime\QTSystem\;
C:\Program Files\NetBeans 7.0.1\java\ant\bin;
C:\Program Files\Java\jdk1.6.0_27\bin;
C:\Program Files\TortoiseSVN\bin;
C:\Program Files (x86)\Rational\Rose RealTime\bin\win32;
C:\Program Files (x86)\Rational\common;
C:\Cadence\SPB_16.5\OpenAccess\bin\win32\opt;
C:\Cadence\SPB_16.5\tools\Capture;
C:\Cadence\SPB_16.5\tools\PSpice\Library;
C:\Cadence\SPB_16.5\tools\PSpice;
C:\Cadence\SPB_16.5\tools\specctra\bin;
C:\Cadence\SPB_16.5\tools\fet\bin;
C:\Cadence\SPB_16.5\tools\libutil\bin;
C:\Cadence\SPB_16.5\tools\bin;
C:\Cadence\SPB_16.5\tools\pcb\bin XILINX -C:
\Xilinx\13.3\ISE_DS\ISE\ -C:
\Xilinx\13.3\ISE_DS\ISE\ -C:
\Xilinx\13.3\ISE_DS\ISE\ -C:
\Xilinx\13.3\ISE_DS\ISE\ +C:\Xilinx\13.3\ISE_DS\ISE\ +C:\Xilinx\13.3\ISE_DS\ISE\ +C:\Xilinx\13.3\ISE_DS\ISE\ +C:\Xilinx\13.3\ISE_DS\ISE\ XILINXD_LICENSE_FILE 2100@XilinxLM.bu.edu 2100@XilinxLM.bu.edu 2100@XilinxLM.bu.edu -2100@XilinxLM.bu.edu +2100@XilinxLM.bu.edu XILINX_DSP -C:
\Xilinx\13.3\ISE_DS\ISE -C:
\Xilinx\13.3\ISE_DS\ISE -C:
\Xilinx\13.3\ISE_DS\ISE -C:
\Xilinx\13.3\ISE_DS\ISE +C:\Xilinx\13.3\ISE_DS\ISE +C:\Xilinx\13.3\ISE_DS\ISE +C:\Xilinx\13.3\ISE_DS\ISE +C:\Xilinx\13.3\ISE_DS\ISE XILINX_EDK -C:
\Xilinx\13.3\ISE_DS\EDK -C:
\Xilinx\13.3\ISE_DS\EDK -C:
\Xilinx\13.3\ISE_DS\EDK -C:
\Xilinx\13.3\ISE_DS\EDK +C:\Xilinx\13.3\ISE_DS\EDK +C:\Xilinx\13.3\ISE_DS\EDK +C:\Xilinx\13.3\ISE_DS\EDK +C:\Xilinx\13.3\ISE_DS\EDK XILINX_PLANAHEAD -C:
\Xilinx\13.3\ISE_DS\PlanAhead -C:
\Xilinx\13.3\ISE_DS\PlanAhead -C:
\Xilinx\13.3\ISE_DS\PlanAhead -C:
\Xilinx\13.3\ISE_DS\PlanAhead +C:\Xilinx\13.3\ISE_DS\PlanAhead +C:\Xilinx\13.3\ISE_DS\PlanAhead +C:\Xilinx\13.3\ISE_DS\PlanAhead +C:\Xilinx\13.3\ISE_DS\PlanAhead @@ -477,28 +477,28 @@ Default Value --intstyle -  -ise -  +-intstyle +  +ise +  --mt -Enable Multi-Threading -off -off +-mt +Enable Multi-Threading +off +off --ol -Place & Route Effort Level (Overall) -high -std +-ol +Place & Route Effort Level (Overall) +high +std --w -  -true -false +-w +  +true +false @@ -518,28 +518,28 @@ Intel(R) Core(TM)2 Duo CPU E8200 @ 2.66GHz/2660 MHz Intel(R) Core(TM)2 Duo CPU E8200 @ 2.66GHz/2660 MHz Intel(R) Core(TM)2 Duo CPU E8200 @ 2.66GHz/2660 MHz -Intel(R) Core(TM)2 Duo CPU E8200 @ 2.66GHz/2660 MHz +Intel(R) Core(TM)2 Duo CPU E8200 @ 2.66GHz/2660 MHz Host -ECE-PHO115-09 -ECE-PHO115-09 -ECE-PHO115-09 -ECE-PHO115-09 +ECE-PHO115-08 +ECE-PHO115-08 +ECE-PHO115-08 +ECE-PHO115-08 OS Name Microsoft Windows 7 , 64-bit Microsoft Windows 7 , 64-bit Microsoft Windows 7 , 64-bit -Microsoft Windows 7 , 64-bit +Microsoft Windows 7 , 64-bit OS Release Service Pack 1 (build 7601) Service Pack 1 (build 7601) Service Pack 1 (build 7601) -Service Pack 1 (build 7601) +Service Pack 1 (build 7601) \ No newline at end of file diff --git a/ALU_guide.ncd b/ALU_guide.ncd index be0b713..ca10a31 100755 --- a/ALU_guide.ncd +++ b/ALU_guide.ncd @@ -1,3 +1,3 @@ XILINX-XDB 0.1 STUB 0.1 ASCII XILINX-XDM V1.6 -###6396:XlxV32DM 3fff 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NbY21NjacLB9tQ9GrG8zs/fy9d5we2bhLcqksY4p/ub+3LxuNddhvwhrsvtAZQtPEhyoqMP8gcpjrsBXqcdsga9yj9kCb1/EwHauaJUe6xYt5ouWixHWU7RYULTUdTODdy6m40a/XJsrXxk3bcdr56LwvOMdL6zjweOizxP2DbDq8cSvThARb+/z7qIcFnIucKYQ3gXOZCJwAfKYcwHzmHGBucHDD9L45vrOXGsBBols7rTMVQ9gUGnMPY+5/gAMJDN3H+azIGA5tt8EzacyiTH7ncxcsMs1iL1dN5fWEmP2xtpcBEsssbfA5nZVYpm9WjXv+4DVyL7sm3doiRH7Am2+z0qM2Y+z5puXxDL7wct8R5JYYT8imY8aEivtFw1zVSIxd01iP+AACB339Sb4/gvhLrj8DKxcqkoqe5DWkjdF4DnY0d+Bo00DZ5x34GJValVJlrTM0daaVjdwRlK0dfi5LlPLwVO1S7ivYIWWQmgpVBAlD0paQ47NwkQ3pRIZok59wJYmrYYq1twHnVJzrDRHdU8v74aJgonmCz6UFxb6Ghw9SP+psdqAQDOIQaMZbAVKaKwaWElKoTYmtdEBLSkdbaRp9ZRYS+w3QKClnlYzNFMgMxSt2xiBlnlaoml1AxmjaFG46YHTpV6Aq33PXS4h62RV1tydDXHWdUe0VH2SZHoNosWSqSf9qaWj2ujSIdL2SNs+snkODCqkZyI7ExsG2mzSMLU6yikGWDNAtqBkigGudTho+2ATUVosmeKSD9Z8as0n0nzcizXRfHLFJzZ2ru2RWn+VVXEklI8kX1mErpHQWWQ+0X9P4XTBAS4jD9MARh5mAYw9HAcw8XASwNTDaQAzD+cBHHtYBHDi4SqAUwfjKIAzD6MAzj2MA7jwcGgT4eHQJqWHQ5tUHg5t4u2NA5tU3t44sEml71LN/0Ci4bO0BCtXDwQRTHJKqKCMpVSwmqWAJSyTv1HEUvhXUxpFIQ30aprQDLCaMUZJBs8zWjHant9LCWSEUkyIn0UxwxTRUs3HBLn5mpZJWuh05ilqoqiZozDU0OymRo5iP3XSpoUW99BSoI3dc0srCHK0Nc1A1/Yc5ujUnMBmkrKWs5W82HIIZzqujVl2DqVgy5oGT2E2UDDQZSfHX84BP/4+x2fOUS2WlGAGi+OWpfAuKjkGWu0T8JmsTOqCOFaxHwWhT0jxIFlC6IdhK52NSQoCVwwrd0S97ohb4e7n9dN2Uaao968NiqhQi1rUOKCWFEwadIe0RCXSf6MnMgHWnin5VbRSCRE5Ll0pn7sOUTShu5EqAVGIQouhgsRNJ/c9d6hJNvjHWMgX7aJo8KBqHIQs/FKKIGiRkVxyADKgAa7PWvX3eXZmBKn4X6wXzI5hTazSxxTn/2ml3+HWKITG8u2N4nlefC6nbpHsPgsj1/Lvo6/MNtQX7cQ9N5mhsqSftpNFv6BVG9ZvULPfos4MxX8Azq34ww==###2516:XlxV32DM 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\ No newline at end of file diff --git a/ALU_map.map b/ALU_map.map index f6a2ce0..693adae 100755 --- a/ALU_map.map +++ b/ALU_map.map @@ -10,7 +10,7 @@ Target Device : xc6slx16 Target Package : csg324 Target Speed : -3 Mapper Version : spartan6 -- $Revision: 1.55 $ -Mapped Date : Wed Feb 15 15:15:50 2012 +Mapped Date : Thu Feb 16 19:52:56 2012 Mapping design into LUTs... Running directed packing... @@ -19,53 +19,53 @@ Updating timing models... INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report (.mrp). Running timing-driven placement... -Total REAL time at the beginning of Placer: 7 secs +Total REAL time at the beginning of Placer: 6 secs Total CPU time at the beginning of Placer: 5 secs Phase 1.1 Initial Placement Analysis -Phase 1.1 Initial Placement Analysis (Checksum:743131b2) REAL time: 9 secs +Phase 1.1 Initial Placement Analysis (Checksum:ecad4836) REAL time: 7 secs Phase 2.7 Design Feasibility Check -Phase 2.7 Design Feasibility Check (Checksum:743131b2) REAL time: 9 secs +Phase 2.7 Design Feasibility Check (Checksum:ecad4836) REAL time: 7 secs Phase 3.31 Local Placement Optimization -Phase 3.31 Local Placement Optimization (Checksum:743131b2) REAL time: 9 secs +Phase 3.31 Local Placement Optimization (Checksum:ecad4836) REAL time: 7 secs Phase 4.2 Initial Placement for Architecture Specific Features Phase 4.2 Initial Placement for Architecture Specific Features -(Checksum:743131b2) REAL time: 9 secs +(Checksum:ecad4836) REAL time: 7 secs Phase 5.36 Local Placement Optimization -Phase 5.36 Local Placement Optimization (Checksum:743131b2) REAL time: 9 secs +Phase 5.36 Local Placement Optimization (Checksum:ecad4836) REAL time: 7 secs Phase 6.30 Global Clock Region Assignment -Phase 6.30 Global Clock Region Assignment (Checksum:743131b2) REAL time: 9 secs +Phase 6.30 Global Clock Region Assignment (Checksum:ecad4836) REAL time: 7 secs Phase 7.3 Local Placement Optimization -Phase 7.3 Local Placement Optimization (Checksum:743131b2) REAL time: 9 secs +Phase 7.3 Local Placement Optimization (Checksum:ecad4836) REAL time: 7 secs Phase 8.5 Local Placement Optimization -Phase 8.5 Local Placement Optimization (Checksum:743131b2) REAL time: 9 secs +Phase 8.5 Local Placement Optimization (Checksum:ecad4836) REAL time: 7 secs Phase 9.8 Global Placement .. .. -Phase 9.8 Global Placement (Checksum:46f7f38f) REAL time: 9 secs +Phase 9.8 Global Placement (Checksum:59a47f53) REAL time: 7 secs Phase 10.5 Local Placement Optimization -Phase 10.5 Local Placement Optimization (Checksum:46f7f38f) REAL time: 9 secs +Phase 10.5 Local Placement Optimization (Checksum:59a47f53) REAL time: 7 secs Phase 11.18 Placement Optimization -Phase 11.18 Placement Optimization (Checksum:9ea3640f) REAL time: 9 secs +Phase 11.18 Placement Optimization (Checksum:87bc4903) REAL time: 7 secs Phase 12.5 Local Placement Optimization -Phase 12.5 Local Placement Optimization (Checksum:9ea3640f) REAL time: 10 secs +Phase 12.5 Local Placement Optimization (Checksum:87bc4903) REAL time: 7 secs Phase 13.34 Placement Validation -Phase 13.34 Placement Validation (Checksum:9ea3640f) REAL time: 10 secs +Phase 13.34 Placement Validation (Checksum:87bc4903) REAL time: 7 secs -Total REAL time to Placer completion: 10 secs -Total CPU time to Placer completion: 5 secs +Total REAL time to Placer completion: 7 secs +Total CPU time to Placer completion: 6 secs Running post-placement packing... Writing output files... @@ -86,7 +86,7 @@ Slice Logic Utilization: Number used as Memory: 0 out of 2,176 0% Slice Logic Distribution: - Number of occupied Slices: 5 out of 2,278 1% + Number of occupied Slices: 6 out of 2,278 1% Nummber of MUXCYs used: 0 out of 4,556 0% Number of LUT Flip Flop pairs used: 13 Number with an unused Flip Flop: 13 out of 13 100% @@ -130,8 +130,8 @@ Specific Feature Utilization: Average Fanout of Non-Clock Nets: 3.32 -Peak Memory Usage: 352 MB -Total REAL time to MAP completion: 11 secs +Peak Memory Usage: 351 MB +Total REAL time to MAP completion: 8 secs Total CPU time to MAP completion: 6 secs Mapping completed. diff --git a/ALU_map.mrp b/ALU_map.mrp index fa33483..44798c4 100755 --- a/ALU_map.mrp +++ b/ALU_map.mrp @@ -10,7 +10,7 @@ Target Device : xc6slx16 Target Package : csg324 Target Speed : -3 Mapper Version : spartan6 -- $Revision: 1.55 $ -Mapped Date : Wed Feb 15 15:15:50 2012 +Mapped Date : Thu Feb 16 19:52:56 2012 Design Summary -------------- @@ -27,7 +27,7 @@ Slice Logic Utilization: Number used as Memory: 0 out of 2,176 0% Slice Logic Distribution: - Number of occupied Slices: 5 out of 2,278 1% + Number of occupied Slices: 6 out of 2,278 1% Nummber of MUXCYs used: 0 out of 4,556 0% Number of LUT Flip Flop pairs used: 13 Number with an unused Flip Flop: 13 out of 13 100% @@ -71,8 +71,8 @@ Specific Feature Utilization: Average Fanout of Non-Clock Nets: 3.32 -Peak Memory Usage: 352 MB -Total REAL time to MAP completion: 11 secs +Peak Memory Usage: 351 MB +Total REAL time to MAP completion: 8 secs Total CPU time to MAP completion: 6 secs Table of Contents diff --git a/ALU_map.ncd b/ALU_map.ncd index 34a2cbf..41d7376 100755 --- a/ALU_map.ncd +++ b/ALU_map.ncd @@ -1,3 +1,3 @@ XILINX-XDB 0.1 STUB 0.1 ASCII XILINX-XDM V1.6 -###5580:XlxV32DM 35cd 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\ No newline at end of file diff --git a/ALU_map.xrpt b/ALU_map.xrpt index 0af19e6..57b33c1 100755 --- a/ALU_map.xrpt +++ b/ALU_map.xrpt @@ -5,13 +5,13 @@ The structure and the elements are likely to change over the next few releases. This means code written to parse this file will need to be revisited each subsequent release.--> - +
- + @@ -43,7 +43,7 @@ - +
@@ -121,8 +121,8 @@ - - + +
@@ -155,10 +155,10 @@ - + - + diff --git a/ALU_ngdbuild.xrpt b/ALU_ngdbuild.xrpt index bb02950..fad5196 100755 --- a/ALU_ngdbuild.xrpt +++ b/ALU_ngdbuild.xrpt @@ -5,13 +5,13 @@ The structure and the elements are likely to change over the next few releases. This means code written to parse this file will need to be revisited each subsequent release.--> - +
- + @@ -43,7 +43,7 @@ - +
@@ -70,47 +70,39 @@
- + - + - + - - - - - - - - + + + + - +
- + - + - + - - - - - - - - + + + + - +
diff --git a/ALU_pad.csv b/ALU_pad.csv index baff75f..5adfef1 100755 --- a/ALU_pad.csv +++ b/ALU_pad.csv @@ -1,7 +1,7 @@ #Release 13.3 - par O.76xd (nt64) #Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. -#Wed Feb 15 15:16:12 2012 +#Thu Feb 16 19:53:16 2012 # ## NOTE: This file is designed to be imported into a spreadsheet program @@ -26,7 +26,7 @@ A4,,IOBS,IO_L5N_0,UNUSED,,0,,,,,,,,, A5,,IOBS,IO_L6N_0,UNUSED,,0,,,,,,,,, A6,,IOBS,IO_L8N_VREF_0,UNUSED,,0,,,,,,,,, A7,,IOBS,IO_L10N_0,UNUSED,,0,,,,,,,,, -A8,C,IOB,IO_L33N_0,INPUT,LVCMOS25*,0,,,,NONE,,LOCATED,NO,NONE, +A8,,IOBS,IO_L33N_0,UNUSED,,0,,,,,,,,, A9,,IOBS,IO_L35N_GCLK16_0,UNUSED,,0,,,,,,,,, A10,,IOBS,IO_L37N_GCLK12_0,UNUSED,,0,,,,,,,,, A11,,IOBS,IO_L39N_0,UNUSED,,0,,,,,,,,, @@ -58,12 +58,12 @@ B18,,,TMS,,,,,,,,,,,, C1,,IOBS,IO_L83N_VREF_3,UNUSED,,3,,,,,,,,, C2,,IOBM,IO_L83P_3,UNUSED,,3,,,,,,,,, C3,,,GND,,,,,,,,,,,, -C4,,IOBS,IO_L1N_VREF_0,UNUSED,,0,,,,,,,,, +C4,A,IOB,IO_L1N_VREF_0,INPUT,LVCMOS25*,0,,,,NONE,,LOCATED,NO,NONE, C5,,IOBM,IO_L6P_0,UNUSED,,0,,,,,,,,, C6,,IOBS,IO_L3N_0,UNUSED,,0,,,,,,,,, C7,,IOBM,IO_L10P_0,UNUSED,,0,,,,,,,,, C8,,IOBS,IO_L11N_0,UNUSED,,0,,,,,,,,, -C9,A,IOB,IO_L34N_GCLK18_0,INPUT,LVCMOS25*,0,,,,NONE,,LOCATED,NO,NONE, +C9,D,IOB,IO_L34N_GCLK18_0,INPUT,LVCMOS25*,0,,,,NONE,,LOCATED,NO,NONE, C10,,IOBM,IO_L37P_GCLK13_0,UNUSED,,0,,,,,,,,, C11,,IOBS,IO_L36N_GCLK14_0,UNUSED,,0,,,,,,,,, C12,,IOBS,IO_L47N_0,UNUSED,,0,,,,,,,,, @@ -81,7 +81,7 @@ D5,,,GND,,,,,,,,,,,, D6,,IOBM,IO_L3P_0,UNUSED,,0,,,,,,,,, D7,,,VCCO_0,,,0,,,,,any******,,,, D8,,IOBM,IO_L11P_0,UNUSED,,0,,,,,,,,, -D9,D,IOB,IO_L34P_GCLK19_0,INPUT,LVCMOS25*,0,,,,NONE,,LOCATED,NO,NONE, +D9,C,IOB,IO_L34P_GCLK19_0,INPUT,LVCMOS25*,0,,,,NONE,,LOCATED,NO,NONE, D10,,,GND,,,,,,,,,,,, D11,,IOBM,IO_L36P_GCLK15_0,UNUSED,,0,,,,,,,,, D12,,IOBM,IO_L47P_0,UNUSED,,0,,,,,,,,, diff --git a/ALU_pad.txt b/ALU_pad.txt index 1a30998..1085c83 100755 --- a/ALU_pad.txt +++ b/ALU_pad.txt @@ -1,7 +1,7 @@ Release 13.3 - par O.76xd (nt64) Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. -Wed Feb 15 15:16:19 2012 +Thu Feb 16 19:53:22 2012 INFO: The IO information is provided in three file formats as part of the Place and Route (PAR) process. These formats are: @@ -27,7 +27,7 @@ Pinout by Pin Number: |A5 | |IOBS |IO_L6N_0 |UNUSED | |0 | | | | | | | | | |A6 | |IOBS |IO_L8N_VREF_0 |UNUSED | |0 | | | | | | | | | |A7 | |IOBS |IO_L10N_0 |UNUSED | |0 | | | | | | | | | -|A8 |C |IOB |IO_L33N_0 |INPUT |LVCMOS25* |0 | | | |NONE | |LOCATED |NO |NONE | +|A8 | |IOBS |IO_L33N_0 |UNUSED | |0 | | | | | | | | | |A9 | |IOBS |IO_L35N_GCLK16_0 |UNUSED | |0 | | | | | | | | | |A10 | |IOBS |IO_L37N_GCLK12_0 |UNUSED | |0 | | | | | | | | | |A11 | |IOBS |IO_L39N_0 |UNUSED | |0 | | | | | | | | | @@ -59,12 +59,12 @@ Pinout by Pin Number: |C1 | |IOBS |IO_L83N_VREF_3 |UNUSED | |3 | | | | | | | | | |C2 | |IOBM |IO_L83P_3 |UNUSED | |3 | | | | | | | | | |C3 | | |GND | | | | | | | | | | | | -|C4 | |IOBS |IO_L1N_VREF_0 |UNUSED | |0 | | | | | | | | | +|C4 |A |IOB |IO_L1N_VREF_0 |INPUT |LVCMOS25* |0 | | | |NONE | |LOCATED |NO |NONE | |C5 | |IOBM |IO_L6P_0 |UNUSED | |0 | | | | | | | | | |C6 | |IOBS |IO_L3N_0 |UNUSED | |0 | | | | | | | | | |C7 | |IOBM |IO_L10P_0 |UNUSED | |0 | | | | | | | | | |C8 | |IOBS |IO_L11N_0 |UNUSED | |0 | | | | | | | | | -|C9 |A |IOB |IO_L34N_GCLK18_0 |INPUT |LVCMOS25* |0 | | | |NONE | |LOCATED |NO |NONE | +|C9 |D |IOB |IO_L34N_GCLK18_0 |INPUT |LVCMOS25* |0 | | | |NONE | |LOCATED |NO |NONE | |C10 | |IOBM |IO_L37P_GCLK13_0 |UNUSED | |0 | | | | | | | | | |C11 | |IOBS |IO_L36N_GCLK14_0 |UNUSED | |0 | | | | | | | | | |C12 | |IOBS |IO_L47N_0 |UNUSED | |0 | | | | | | | | | @@ -82,7 +82,7 @@ Pinout by Pin Number: |D6 | |IOBM |IO_L3P_0 |UNUSED | |0 | | | | | | | | | |D7 | | |VCCO_0 | | |0 | | | | |any******| | | | |D8 | |IOBM |IO_L11P_0 |UNUSED | |0 | | | | | | | | | -|D9 |D |IOB |IO_L34P_GCLK19_0 |INPUT |LVCMOS25* |0 | | | |NONE | |LOCATED |NO |NONE | +|D9 |C |IOB |IO_L34P_GCLK19_0 |INPUT |LVCMOS25* |0 | | | |NONE | |LOCATED |NO |NONE | |D10 | | |GND | | | | | | | | | | | | |D11 | |IOBM |IO_L36P_GCLK15_0 |UNUSED | |0 | | | | | | | | | |D12 | |IOBM |IO_L47P_0 |UNUSED | |0 | | | | | | | | | diff --git a/ALU_par.xrpt b/ALU_par.xrpt index 41f4b3e..d089c4e 100755 --- a/ALU_par.xrpt +++ b/ALU_par.xrpt @@ -5,13 +5,13 @@ The structure and the elements are likely to change over the next few releases. This means code written to parse this file will need to be revisited each subsequent release.--> - +
- + @@ -43,7 +43,7 @@ - +
@@ -67,7 +67,7 @@ - + @@ -137,16 +137,10 @@ - - + - - + - - - - @@ -348,10 +342,16 @@ - + + - + + + + + + @@ -383,7 +383,7 @@ - + @@ -508,7 +508,7 @@ - + @@ -2287,13 +2287,13 @@ - +
- + @@ -2325,7 +2325,7 @@ - +
@@ -2366,10 +2366,10 @@ - + - + diff --git a/ALU_summary.html b/ALU_summary.html index 840a7a1..dd1ef6d 100755 --- a/ALU_summary.html +++ b/ALU_summary.html @@ -2,7 +2,7 @@
- + @@ -13,26 +13,25 @@ - + - + - + - + +  @@ -43,11 +42,11 @@ No Errors - +
ALU Project Status
ALU Project Status (02/16/2012 - 18:30:33)
Project File: lab1.xiseModule Name: ALU Implementation State:Placed and RoutedMapped
Target Device: xc6slx16-3csg324
  • Errors:
 -No Errors 
Product Version:ISE 13.4Product Version:ISE 13.3
  • Warnings:
2 Warnings (0 new) 
Design Goal: Balanced
  • Routing Results:
 -All Signals Completely Routed
Design Strategy:
Environment: - + System Settings
  • Final Timing Score:
0  (Timing Report)  
@@ -107,7 +106,7 @@ System Settings   Number of occupied Slices -5 +7 2,278 1%   @@ -148,7 +147,7 @@ System Settings 0%   -Number of bonded IOBs +Number of bonded IOBs 18 232 7% @@ -287,7 +286,7 @@ System Settings   Average Fanout of Non-Clock Nets -3.32 +3.26       @@ -296,26 +295,7 @@ System Settings - 
- - - - - - - - - - - - - - - - - -
Performance Summary [-]
Final Timing Score:0 (Setup: 0, Hold: 0)Pinout Data:Pinout Report
Routing Results: -All Signals Completely RoutedClock Data:Clock Report
Timing Constraints:   
+ @@ -323,21 +303,21 @@ System Settings Detailed Reports [-] Report NameStatusGenerated ErrorsWarningsInfos -Synthesis ReportCurrentWed Feb 15 18:59:45 201202 Warnings (0 new)0 -Translation ReportCurrentWed Feb 15 18:59:45 2012000 -Map ReportCurrentWed Feb 15 18:59:45 2012006 Infos (6 new) -Place and Route ReportCurrentWed Feb 15 18:59:46 2012002 Infos (2 new) +Synthesis ReportCurrentThu Feb 16 18:30:08 201202 Warnings (0 new)0 +Translation ReportCurrentThu Feb 16 18:30:17 2012000 +Map ReportCurrentThu Feb 16 18:30:30 2012    +Place and Route ReportOut of DateThu Feb 16 18:19:18 2012002 Infos (0 new) Power Report      -Post-PAR Static Timing ReportCurrentWed Feb 15 18:59:46 2012003 Infos (3 new) -Bitgen Report      +Post-PAR Static Timing ReportOut of DateThu Feb 16 18:19:28 2012003 Infos (0 new) +Bitgen ReportOut of DateThu Feb 16 18:19:51 2012001 Info (0 new)  
- - + +
Secondary Reports [-]
Report NameStatusGenerated
WebTalk ReportCurrentWed Feb 15 18:59:48 2012
WebTalk Log FileCurrentWed Feb 15 18:59:48 2012
WebTalk ReportOut of DateThu Feb 16 18:19:55 2012
WebTalk Log FileOut of DateThu Feb 16 18:20:07 2012
-
Date Generated: 02/15/2012 - 19:01:09
+
Date Generated: 02/16/2012 - 18:37:40
\ No newline at end of file diff --git a/ALU_summary.xml b/ALU_summary.xml index fb30df9..2bacdf8 100755 --- a/ALU_summary.xml +++ b/ALU_summary.xml @@ -4,7 +4,7 @@ changes made to this file may result in unpredictable behavior or data corruption. It is strongly advised that users do not edit the contents of this file. --> - + diff --git a/ALU_usage.xml b/ALU_usage.xml index 333ec93..2bf179f 100755 --- a/ALU_usage.xml +++ b/ALU_usage.xml @@ -4,242 +4,246 @@ changes made to this file may result in unpredictable behavior or data corruption. It is strongly advised that users do not edit the contents of this file. --> - - - + + + - + - + - + - - - + + + - + - + - + - + - + - + - + - - - + + + - - - - - + + + + + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - - + + + + - + - + - + - - - + + + - + - + - + - + - - - + + + - - + + - - + + - + - + - + - + - + - + - - + + - - + + - + - + - + - - + + - + - + - - - + - + + + + + - + - + - - - + - + - - - + + + + + + + + + + + + + - + - + - + - - - + + + + + - + - + - + - - - - - - - + - + - - - - - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + - + diff --git a/ALU_xst.xrpt b/ALU_xst.xrpt index 9b982ba..c3ab59a 100755 --- a/ALU_xst.xrpt +++ b/ALU_xst.xrpt @@ -5,13 +5,13 @@ The structure and the elements are likely to change over the next few releases. This means code written to parse this file will need to be revisited each subsequent release.--> - +
- + @@ -43,7 +43,7 @@ - +
@@ -112,10 +112,6 @@ - - - - @@ -147,15 +143,15 @@
- - + + - + - + - + @@ -167,12 +163,12 @@
- - - - - - + + + + + + diff --git a/Divide.cmd_log b/Divide.cmd_log index c6e0126..b7540e1 100755 --- a/Divide.cmd_log +++ b/Divide.cmd_log @@ -1,2 +1,11 @@ sch2sym -intstyle ise -family spartan6 -refsym Divide {X:/My Documents/ec311/lab1/Divide.sch} {X:/My Documents/ec311/lab1/Divide.sym} sch2sym -intstyle ise -family spartan6 -w -refsym Divide /home/michael/Documents/School/EC311/lab1/Divide.sch /home/michael/Documents/School/EC311/lab1/Divide.sym +sch2sym -intstyle ise -family spartan6 -w -refsym Divide {X:/My Documents/ec311/ec311-lab1/Divide.sch} {X:/My Documents/ec311/ec311-lab1/Divide.sym} +sch2sym -intstyle ise -family spartan6 -w -refsym Divide {X:/My Documents/ec311/ec311-lab1/Divide.sch} {X:/My Documents/ec311/ec311-lab1/Divide.sym} +sch2sym -intstyle ise -family spartan6 -w -refsym Divide {X:/My Documents/ec311/ec311-lab1/Divide.sch} {X:/My Documents/ec311/ec311-lab1/Divide.sym} +sch2sym -intstyle ise -family spartan6 -w -refsym Divide {X:/My Documents/ec311/ec311-lab1/Divide.sch} {X:/My Documents/ec311/ec311-lab1/Divide.sym} +sch2sym -intstyle ise -family spartan6 -w -refsym Divide {X:/My Documents/ec311/ec311-lab1/Divide.sch} {X:/My Documents/ec311/ec311-lab1/Divide.sym} +sch2sym -intstyle ise -family spartan6 -w -refsym Divide {X:/My Documents/ec311/ec311-lab1/Divide.sch} {X:/My Documents/ec311/ec311-lab1/Divide.sym} +sch2sym -intstyle ise -family spartan6 -w -refsym Divide {X:/My Documents/ec311/ec311-lab1/Divide.sch} {X:/My Documents/ec311/ec311-lab1/Divide.sym} +sch2sym -intstyle ise -family spartan6 -w -refsym Divide {X:/My Documents/ec311/ec311-lab1/Divide.sch} {X:/My Documents/ec311/ec311-lab1/Divide.sym} +sch2sym -intstyle ise -family spartan6 -w -refsym Divide {X:/My Documents/ec311/ec311-lab1/Divide.sch} {X:/My Documents/ec311/ec311-lab1/Divide.sym} diff --git a/Divide.jhd b/Divide.jhd index eba0746..0b08bb7 100755 --- a/Divide.jhd +++ b/Divide.jhd @@ -1,9 +1,9 @@ -MODULE Divide - SUBMODULE Divide_1 - INSTANCE XLXI_8 - SUBMODULE Divide_2 - INSTANCE XLXI_9 - SUBMODULE Divide_3 - INSTANCE XLXI_10 - SUBMODULE Divide_0 - INSTANCE XLXI_12 +MODULE Divide + SUBMODULE Divide_1 + INSTANCE XLXI_8 + SUBMODULE Divide_2 + INSTANCE XLXI_9 + SUBMODULE Divide_3 + INSTANCE XLXI_10 + SUBMODULE Divide_0 + INSTANCE XLXI_12 diff --git a/Divide.sch b/Divide.sch index 01ec9d9..1104a30 100755 --- a/Divide.sch +++ b/Divide.sch @@ -1,171 +1,170 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - 2012-2-16T0:25:5 - - - - - - - - - 2012-2-16T0:25:9 - - - - - - - - - 2012-2-16T0:25:12 - - - - - - - - - 2012-2-16T0:25:16 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + 2012-2-16T23:13:16 + + + + + + + + + 2012-2-17T0:27:48 + + + + + + + + + 2012-2-17T0:22:15 + + + + + + + + + 2012-2-16T23:51:54 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/Divide.schlog b/Divide.schlog new file mode 100755 index 0000000..e69de29 diff --git a/Divide.sym b/Divide.sym index 0ca17af..dfbf436 100755 --- a/Divide.sym +++ b/Divide.sym @@ -1,33 +1,33 @@ - - - BLOCK - 2012-2-16T0:25:40 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + BLOCK + 2012-2-17T0:27:58 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Divide.vf b/Divide.vf index c428df2..8d6a587 100755 --- a/Divide.vf +++ b/Divide.vf @@ -7,11 +7,11 @@ // \ \ \/ Version : 13.3 // \ \ Application : sch2hdl // / / Filename : Divide.vf -// /___/ /\ Timestamp : 02/15/2012 15:00:11 +// /___/ /\ Timestamp : 02/16/2012 19:28:10 // \ \ / \ // \___\/\___\ // -//Command: sch2hdl -intstyle ise -family spartan6 -verilog "X:/My Documents/ec311/lab1/Divide.vf" -w "X:/My Documents/ec311/lab1/Divide.sch" +//Command: sch2hdl -intstyle ise -family spartan6 -verilog "X:/My Documents/ec311/ec311-lab1/Divide.vf" -w "X:/My Documents/ec311/ec311-lab1/Divide.sch" //Design Name: Divide //Device: spartan6 //Purpose: @@ -82,25 +82,24 @@ module Divide_2_MUSER_Divide(b0, input b3; output result; - wire XLXN_1; - wire XLXN_2; - wire XLXN_3; - wire XLXN_7; + wire XLXN_9; + wire XLXN_13; + wire XLXN_14; + wire XLXN_15; - OR3 XLXI_1 (.I0(XLXN_1), - .I1(XLXN_7), - .I2(XLXN_3), - .O(result)); - AND3 XLXI_2 (.I0(XLXN_2), - .I1(b3), - .I2(b1), - .O(XLXN_1)); - INV XLXI_3 (.I(b2), - .O(XLXN_2)); - INV XLXI_4 (.I(b0), - .O(XLXN_3)); - INV XLXI_9 (.I(b1), - .O(XLXN_7)); + AND2 XLXI_10 (.I0(XLXN_9), + .I1(b3), + .O(result)); + OR3 XLXI_12 (.I0(XLXN_15), + .I1(XLXN_14), + .I2(XLXN_13), + .O(XLXN_9)); + INV XLXI_13 (.I(b0), + .O(XLXN_13)); + INV XLXI_15 (.I(b1), + .O(XLXN_14)); + INV XLXI_16 (.I(b2), + .O(XLXN_15)); endmodule `timescale 1ns / 1ps @@ -117,14 +116,23 @@ module Divide_3_MUSER_Divide(b0, output result; wire XLXN_2; + wire XLXN_13; + wire XLXN_14; + wire XLXN_15; AND2 XLXI_2 (.I0(XLXN_2), .I1(b3), .O(result)); - NOR3 XLXI_3 (.I0(b0), - .I1(b1), - .I2(b2), - .O(XLXN_2)); + OR3 XLXI_4 (.I0(XLXN_15), + .I1(XLXN_14), + .I2(XLXN_13), + .O(XLXN_2)); + INV XLXI_6 (.I(b2), + .O(XLXN_13)); + INV XLXI_7 (.I(b1), + .O(XLXN_14)); + INV XLXI_8 (.I(b0), + .O(XLXN_15)); endmodule `timescale 1ns / 1ps @@ -140,25 +148,23 @@ module Divide_0_MUSER_Divide(b0, input b3; output result; - wire XLXN_1; wire XLXN_2; wire XLXN_3; wire XLXN_4; wire XLXN_5; wire XLXN_6; + wire XLXN_12; - AND3 XLXI_1 (.I0(b3), + AND3 XLXI_1 (.I0(b0), .I1(b3), .I2(XLXN_2), .O(XLXN_5)); AND2 XLXI_2 (.I0(b1), - .I1(XLXN_1), + .I1(XLXN_12), .O(XLXN_4)); AND2 XLXI_3 (.I0(b1), .I1(XLXN_3), .O(XLXN_6)); - INV XLXI_4 (.I(b3), - .O(XLXN_1)); INV XLXI_5 (.I(b1), .O(XLXN_2)); INV XLXI_6 (.I(b0), @@ -167,6 +173,8 @@ module Divide_0_MUSER_Divide(b0, .I1(XLXN_5), .I2(XLXN_4), .O(result)); + INV XLXI_9 (.I(b3), + .O(XLXN_12)); endmodule `timescale 1ns / 1ps @@ -204,9 +212,9 @@ module Divide(b0, .b2(b2), .b3(b3), .result(out3)); - Divide_0_MUSER_Divide XLXI_12 (.b0(b1), - .b1(b2), + Divide_0_MUSER_Divide XLXI_12 (.b0(b0), + .b1(b1), .b2(b2), - .b3(b0), + .b3(b3), .result(out0)); endmodule diff --git a/Divide_0.cmd_log b/Divide_0.cmd_log index f4446c4..8050f67 100755 --- a/Divide_0.cmd_log +++ b/Divide_0.cmd_log @@ -1,2 +1,9 @@ sch2sym -intstyle ise -family spartan6 -refsym Divide_0 {X:/My Documents/ec311/lab1/Divide_0.sch} {X:/My Documents/ec311/lab1/Divide_0.sym} sch2sym -intstyle ise -family spartan6 -w -refsym Divide_0 /home/michael/Documents/School/EC311/lab1/Divide_0.sch /home/michael/Documents/School/EC311/lab1/Divide_0.sym +sch2sym -intstyle ise -family spartan6 -w -refsym Divide_0 {X:/My Documents/ec311/ec311-lab1/Divide_0.sch} {X:/My Documents/ec311/ec311-lab1/Divide_0.sym} +sch2sym -intstyle ise -family spartan6 -w -refsym Divide_0 {X:/My Documents/ec311/ec311-lab1/Divide_0.sch} {X:/My Documents/ec311/ec311-lab1/Divide_0.sym} +sch2sym -intstyle ise -family spartan6 -w -refsym Divide_0 {X:/My Documents/ec311/ec311-lab1/Divide_0.sch} {X:/My Documents/ec311/ec311-lab1/Divide_0.sym} +sch2sym -intstyle ise -family spartan6 -w -refsym Divide_0 {X:/My Documents/ec311/ec311-lab1/Divide_0.sch} {X:/My Documents/ec311/ec311-lab1/Divide_0.sym} +sch2sym -intstyle ise -family spartan6 -w -refsym Divide_0 {X:/My Documents/ec311/ec311-lab1/Divide_0.sch} {X:/My Documents/ec311/ec311-lab1/Divide_0.sym} +sch2sym -intstyle ise -family spartan6 -w -refsym Divide_0 {X:/My Documents/ec311/ec311-lab1/Divide_0.sch} {X:/My Documents/ec311/ec311-lab1/Divide_0.sym} +sch2sym -intstyle ise -family spartan6 -w -refsym Divide_0 {X:/My Documents/ec311/ec311-lab1/Divide_0.sch} {X:/My Documents/ec311/ec311-lab1/Divide_0.sym} diff --git a/Divide_0.jhd b/Divide_0.jhd index 3505e32..ca45971 100755 --- a/Divide_0.jhd +++ b/Divide_0.jhd @@ -1 +1 @@ -MODULE Divide_0 +MODULE Divide_0 diff --git a/Divide_0.sch b/Divide_0.sch index f1040fd..1ad0c3d 100755 --- a/Divide_0.sch +++ b/Divide_0.sch @@ -1,170 +1,169 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - 2000-1-1T10:10:10 - - - - - - - - - - - 2000-1-1T10:10:10 - - - - - - - - - - 2000-1-1T10:10:10 - - - - - - - - - 2000-1-1T10:10:10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + 2000-1-1T10:10:10 + + + + + + + + + + + 2000-1-1T10:10:10 + + + + + + + + + + 2000-1-1T10:10:10 + + + + + + + + + 2000-1-1T10:10:10 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/Divide_0.sym b/Divide_0.sym index 42aebcb..3703413 100755 --- a/Divide_0.sym +++ b/Divide_0.sym @@ -1,24 +1,24 @@ - - - BLOCK - 2012-2-16T0:25:16 - - - - - - - - - - - - - - - - - - - - + + + BLOCK + 2012-2-16T23:51:54 + + + + + + + + + + + + + + + + + + + + diff --git a/Divide_0.vf b/Divide_0.vf index 1ffdc18..72398c8 100755 --- a/Divide_0.vf +++ b/Divide_0.vf @@ -7,11 +7,11 @@ // \ \ \/ Version : 13.3 // \ \ Application : sch2hdl // / / Filename : Divide_0.vf -// /___/ /\ Timestamp : 02/15/2012 15:00:06 +// /___/ /\ Timestamp : 02/16/2012 18:52:20 // \ \ / \ // \___\/\___\ // -//Command: sch2hdl -intstyle ise -family spartan6 -verilog "X:/My Documents/ec311/lab1/Divide_0.vf" -w "X:/My Documents/ec311/lab1/Divide_0.sch" +//Command: sch2hdl -intstyle ise -family spartan6 -verilog "X:/My Documents/ec311/ec311-lab1/Divide_0.vf" -w "X:/My Documents/ec311/ec311-lab1/Divide_0.sch" //Design Name: Divide_0 //Device: spartan6 //Purpose: @@ -32,25 +32,23 @@ module Divide_0(b0, input b3; output result; - wire XLXN_1; wire XLXN_2; wire XLXN_3; wire XLXN_4; wire XLXN_5; wire XLXN_6; + wire XLXN_12; - AND3 XLXI_1 (.I0(b3), + AND3 XLXI_1 (.I0(b0), .I1(b3), .I2(XLXN_2), .O(XLXN_5)); AND2 XLXI_2 (.I0(b1), - .I1(XLXN_1), + .I1(XLXN_12), .O(XLXN_4)); AND2 XLXI_3 (.I0(b1), .I1(XLXN_3), .O(XLXN_6)); - INV XLXI_4 (.I(b3), - .O(XLXN_1)); INV XLXI_5 (.I(b1), .O(XLXN_2)); INV XLXI_6 (.I(b0), @@ -59,4 +57,6 @@ module Divide_0(b0, .I1(XLXN_5), .I2(XLXN_4), .O(result)); + INV XLXI_9 (.I(b3), + .O(XLXN_12)); endmodule diff --git a/Divide_1.cmd_log b/Divide_1.cmd_log index c56fcf2..c5e6a18 100755 --- a/Divide_1.cmd_log +++ b/Divide_1.cmd_log @@ -1,3 +1,4 @@ sch2sym -intstyle ise -family spartan6 -refsym Divide_1 {X:/My Documents/ec311/lab1/Divide_1.sch} {X:/My Documents/ec311/lab1/Divide_1.sym} sch2sym -intstyle ise -family spartan6 -refsym Divide_1 /home/michael/Documents/School/EC311/lab1/Divide_1.sch /home/michael/Documents/School/EC311/lab1/Divide_1.sym sch2sym -intstyle ise -family spartan6 -w -refsym Divide_1 /home/michael/Documents/School/EC311/lab1/Divide_1.sch /home/michael/Documents/School/EC311/lab1/Divide_1.sym +sch2sym -intstyle ise -family spartan6 -w -refsym Divide_1 {X:/My Documents/ec311/ec311-lab1/Divide_1.sch} {X:/My Documents/ec311/ec311-lab1/Divide_1.sym} diff --git a/Divide_1.jhd b/Divide_1.jhd index f1151f9..de505b8 100755 --- a/Divide_1.jhd +++ b/Divide_1.jhd @@ -1 +1 @@ -MODULE Divide_1 +MODULE Divide_1 diff --git a/Divide_1.sch b/Divide_1.sch index fe2cc4d..4e46655 100755 --- a/Divide_1.sch +++ b/Divide_1.sch @@ -1,209 +1,209 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - 2000-1-1T10:10:10 - - - - - - - - - - - - 2000-1-1T10:10:10 - - - - - - - - - - - - - - 2000-1-1T10:10:10 - - - - - - - - - - 2000-1-1T10:10:10 - - - - - - - - - - - 2000-1-1T10:10:10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2000-1-1T10:10:10 + + + + + + + + + + + + 2000-1-1T10:10:10 + + + + + + + + + + + + + + 2000-1-1T10:10:10 + + + + + + + + + + 2000-1-1T10:10:10 + + + + + + + + + + + 2000-1-1T10:10:10 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/Divide_1.sym b/Divide_1.sym index 4cf6ead..8793446 100755 --- a/Divide_1.sym +++ b/Divide_1.sym @@ -1,24 +1,24 @@ - - - BLOCK - 2012-2-16T0:25:5 - - - - - - - - - - - - - - - - - - - - + + + BLOCK + 2012-2-16T23:13:16 + + + + + + + + + + + + + + + + + + + + diff --git a/Divide_1.vf b/Divide_1.vf index ddd2752..fb10a43 100755 --- a/Divide_1.vf +++ b/Divide_1.vf @@ -7,11 +7,11 @@ // \ \ \/ Version : 13.3 // \ \ Application : sch2hdl // / / Filename : Divide_1.vf -// /___/ /\ Timestamp : 02/15/2012 15:00:06 +// /___/ /\ Timestamp : 02/16/2012 18:40:35 // \ \ / \ // \___\/\___\ // -//Command: sch2hdl -intstyle ise -family spartan6 -verilog "X:/My Documents/ec311/lab1/Divide_1.vf" -w "X:/My Documents/ec311/lab1/Divide_1.sch" +//Command: sch2hdl -intstyle ise -family spartan6 -verilog "X:/My Documents/ec311/ec311-lab1/Divide_1.vf" -w "X:/My Documents/ec311/ec311-lab1/Divide_1.sch" //Design Name: Divide_1 //Device: spartan6 //Purpose: diff --git a/Divide_2.cmd_log b/Divide_2.cmd_log index 9059580..efabe69 100755 --- a/Divide_2.cmd_log +++ b/Divide_2.cmd_log @@ -1,2 +1,4 @@ sch2sym -intstyle ise -family spartan6 -refsym Divide_2 {X:/My Documents/ec311/lab1/Divide_2.sch} {X:/My Documents/ec311/lab1/Divide_2.sym} sch2sym -intstyle ise -family spartan6 -w -refsym Divide_2 /home/michael/Documents/School/EC311/lab1/Divide_2.sch /home/michael/Documents/School/EC311/lab1/Divide_2.sym +sch2sym -intstyle ise -family spartan6 -w -refsym Divide_2 {X:/My Documents/ec311/ec311-lab1/Divide_2.sch} {X:/My Documents/ec311/ec311-lab1/Divide_2.sym} +sch2sym -intstyle ise -family spartan6 -w -refsym Divide_2 {X:/My Documents/ec311/ec311-lab1/Divide_2.sch} {X:/My Documents/ec311/ec311-lab1/Divide_2.sym} diff --git a/Divide_2.jhd b/Divide_2.jhd index 26b7fc0..17d24fb 100755 --- a/Divide_2.jhd +++ b/Divide_2.jhd @@ -1 +1 @@ -MODULE Divide_2 +MODULE Divide_2 diff --git a/Divide_2.sch b/Divide_2.sch index 152b17f..500f1fa 100755 --- a/Divide_2.sch +++ b/Divide_2.sch @@ -1,84 +1,120 @@ - - - - - - - - - - - - - - - - - - - - - 2000-1-1T10:10:10 - - - - - - - - - - 2000-1-1T10:10:10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + 2000-1-1T10:10:10 + + + + + + + + + + 2000-1-1T10:10:10 + + + + + + + + + + + + + + 2000-1-1T10:10:10 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/Divide_2.sym b/Divide_2.sym index 87e2127..2554cf8 100755 --- a/Divide_2.sym +++ b/Divide_2.sym @@ -1,24 +1,24 @@ - - - BLOCK - 2012-2-16T0:25:9 - - - - - - - - - - - - - - - - - - - - + + + BLOCK + 2012-2-17T0:27:48 + + + + + + + + + + + + + + + + + + + + diff --git a/Divide_2.vf b/Divide_2.vf index a09efec..453ee10 100755 --- a/Divide_2.vf +++ b/Divide_2.vf @@ -7,11 +7,11 @@ // \ \ \/ Version : 13.3 // \ \ Application : sch2hdl // / / Filename : Divide_2.vf -// /___/ /\ Timestamp : 02/15/2012 15:00:06 +// /___/ /\ Timestamp : 02/16/2012 19:28:08 // \ \ / \ // \___\/\___\ // -//Command: sch2hdl -intstyle ise -family spartan6 -verilog "X:/My Documents/ec311/lab1/Divide_2.vf" -w "X:/My Documents/ec311/lab1/Divide_2.sch" +//Command: sch2hdl -intstyle ise -family spartan6 -verilog "X:/My Documents/ec311/ec311-lab1/Divide_2.vf" -w "X:/My Documents/ec311/ec311-lab1/Divide_2.sch" //Design Name: Divide_2 //Device: spartan6 //Purpose: @@ -32,23 +32,22 @@ module Divide_2(b0, input b3; output result; - wire XLXN_1; - wire XLXN_2; - wire XLXN_3; - wire XLXN_7; + wire XLXN_9; + wire XLXN_13; + wire XLXN_14; + wire XLXN_15; - OR3 XLXI_1 (.I0(XLXN_1), - .I1(XLXN_7), - .I2(XLXN_3), - .O(result)); - AND3 XLXI_2 (.I0(XLXN_2), - .I1(b3), - .I2(b1), - .O(XLXN_1)); - INV XLXI_3 (.I(b2), - .O(XLXN_2)); - INV XLXI_4 (.I(b0), - .O(XLXN_3)); - INV XLXI_9 (.I(b1), - .O(XLXN_7)); + AND2 XLXI_10 (.I0(XLXN_9), + .I1(b3), + .O(result)); + OR3 XLXI_12 (.I0(XLXN_15), + .I1(XLXN_14), + .I2(XLXN_13), + .O(XLXN_9)); + INV XLXI_13 (.I(b0), + .O(XLXN_13)); + INV XLXI_15 (.I(b1), + .O(XLXN_14)); + INV XLXI_16 (.I(b2), + .O(XLXN_15)); endmodule diff --git a/Divide_3.cmd_log b/Divide_3.cmd_log index 6f95eb8..ec2b844 100755 --- a/Divide_3.cmd_log +++ b/Divide_3.cmd_log @@ -1,2 +1,4 @@ sch2sym -intstyle ise -family spartan6 -refsym Divide_3 {X:/My Documents/ec311/lab1/Divide_3.sch} {X:/My Documents/ec311/lab1/Divide_3.sym} sch2sym -intstyle ise -family spartan6 -w -refsym Divide_3 /home/michael/Documents/School/EC311/lab1/Divide_3.sch /home/michael/Documents/School/EC311/lab1/Divide_3.sym +sch2sym -intstyle ise -family spartan6 -w -refsym Divide_3 {X:/My Documents/ec311/ec311-lab1/Divide_3.sch} {X:/My Documents/ec311/ec311-lab1/Divide_3.sym} +sch2sym -intstyle ise -family spartan6 -w -refsym Divide_3 {X:/My Documents/ec311/ec311-lab1/Divide_3.sch} {X:/My Documents/ec311/ec311-lab1/Divide_3.sym} diff --git a/Divide_3.sch b/Divide_3.sch index c586db1..4760890 100755 --- a/Divide_3.sch +++ b/Divide_3.sch @@ -8,15 +8,18 @@ + - + + + + - 2000-1-1T10:10:10 @@ -27,58 +30,90 @@ - + 2000-1-1T10:10:10 - - + + + - - - + + + + 2000-1-1T10:10:10 + + + + + + - - - - + + + + + + + + + + + + + + + + - - + + + + + + - - + + - - + + - - - + + + - + + + + + + + + + \ No newline at end of file diff --git a/Divide_3.sym b/Divide_3.sym index 65fc49e..f48e1f2 100755 --- a/Divide_3.sym +++ b/Divide_3.sym @@ -1,24 +1,24 @@ - - - BLOCK - 2012-2-16T0:25:12 - - - - - - - - - - - - - - - - - - - - + + + BLOCK + 2012-2-17T0:22:15 + + + + + + + + + + + + + + + + + + + + diff --git a/Divide_3.vf b/Divide_3.vf index 7a443d9..3bb123e 100755 --- a/Divide_3.vf +++ b/Divide_3.vf @@ -7,11 +7,11 @@ // \ \ \/ Version : 13.3 // \ \ Application : sch2hdl // / / Filename : Divide_3.vf -// /___/ /\ Timestamp : 02/15/2012 15:00:07 +// /___/ /\ Timestamp : 02/16/2012 19:22:52 // \ \ / \ // \___\/\___\ // -//Command: sch2hdl -intstyle ise -family spartan6 -verilog "X:/My Documents/ec311/lab1/Divide_3.vf" -w "X:/My Documents/ec311/lab1/Divide_3.sch" +//Command: sch2hdl -intstyle ise -family spartan6 -verilog "X:/My Documents/ec311/ec311-lab1/Divide_3.vf" -w "X:/My Documents/ec311/ec311-lab1/Divide_3.sch" //Design Name: Divide_3 //Device: spartan6 //Purpose: @@ -33,12 +33,21 @@ module Divide_3(b0, output result; wire XLXN_2; + wire XLXN_13; + wire XLXN_14; + wire XLXN_15; AND2 XLXI_2 (.I0(XLXN_2), .I1(b3), .O(result)); - NOR3 XLXI_3 (.I0(b0), - .I1(b1), - .I2(b2), - .O(XLXN_2)); + OR3 XLXI_4 (.I0(XLXN_15), + .I1(XLXN_14), + .I2(XLXN_13), + .O(XLXN_2)); + INV XLXI_6 (.I(b2), + .O(XLXN_13)); + INV XLXI_7 (.I(b1), + .O(XLXN_14)); + INV XLXI_8 (.I(b0), + .O(XLXN_15)); endmodule diff --git a/Modulo.cmd_log b/Modulo.cmd_log index 8d43cf1..6afaaf8 100755 --- a/Modulo.cmd_log +++ b/Modulo.cmd_log @@ -1,2 +1,7 @@ sch2sym -intstyle ise -family spartan6 -refsym Modulo {X:/My Documents/ec311/lab1/Modulo.sch} {X:/My Documents/ec311/lab1/Modulo.sym} sch2sym -intstyle ise -family spartan6 -w -refsym Modulo /home/michael/Documents/School/EC311/lab1/Modulo.sch /home/michael/Documents/School/EC311/lab1/Modulo.sym +sch2sym -intstyle ise -family spartan6 -w -refsym Modulo {X:/My Documents/ec311/ec311-lab1/Modulo.sch} {X:/My Documents/ec311/ec311-lab1/Modulo.sym} +sch2sym -intstyle ise -family spartan6 -w -refsym Modulo {X:/My Documents/ec311/ec311-lab1/Modulo.sch} {X:/My Documents/ec311/ec311-lab1/Modulo.sym} +sch2sym -intstyle ise -family spartan6 -w -refsym Modulo {X:/My Documents/ec311/ec311-lab1/Modulo.sch} {X:/My Documents/ec311/ec311-lab1/Modulo.sym} +sch2sym -intstyle ise -family spartan6 -w -refsym Modulo {X:/My Documents/ec311/ec311-lab1/Modulo.sch} {X:/My Documents/ec311/ec311-lab1/Modulo.sym} +sch2sym -intstyle ise -family spartan6 -w -refsym Modulo {X:/My Documents/ec311/ec311-lab1/Modulo.sch} {X:/My Documents/ec311/ec311-lab1/Modulo.sym} diff --git a/Modulo.sch b/Modulo.sch index 62c204d..7240d6b 100755 --- a/Modulo.sch +++ b/Modulo.sch @@ -23,7 +23,7 @@ - 2012-2-15T19:55:5 + 2012-2-17T0:37:33 @@ -32,7 +32,7 @@ - 2012-2-15T19:55:48 + 2012-2-17T0:43:13 @@ -41,7 +41,7 @@ - 2012-2-15T19:55:1 + 2012-2-17T0:51:57 diff --git a/Modulo.schlog b/Modulo.schlog new file mode 100755 index 0000000..e69de29 diff --git a/Modulo.sym b/Modulo.sym index 618989f..f139633 100755 --- a/Modulo.sym +++ b/Modulo.sym @@ -1,33 +1,33 @@ - - - BLOCK - 2012-2-16T0:29:51 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + BLOCK + 2012-2-17T0:52:15 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Modulo.vf b/Modulo.vf index 045ae26..0007fe1 100755 --- a/Modulo.vf +++ b/Modulo.vf @@ -7,11 +7,11 @@ // \ \ \/ Version : 13.3 // \ \ Application : sch2hdl // / / Filename : Modulo.vf -// /___/ /\ Timestamp : 02/15/2012 15:00:07 +// /___/ /\ Timestamp : 02/16/2012 19:52:31 // \ \ / \ // \___\/\___\ // -//Command: sch2hdl -intstyle ise -family spartan6 -verilog "X:/My Documents/ec311/lab1/Modulo.vf" -w "X:/My Documents/ec311/lab1/Modulo.sch" +//Command: sch2hdl -intstyle ise -family spartan6 -verilog "X:/My Documents/ec311/ec311-lab1/Modulo.vf" -w "X:/My Documents/ec311/ec311-lab1/Modulo.sch" //Design Name: Modulo //Device: spartan6 //Purpose: @@ -35,23 +35,40 @@ module Modulo_0_MUSER_Modulo(b0, wire XLXN_1; wire XLXN_3; wire XLXN_4; - wire XLXN_5; + wire XLXN_12; + wire XLXN_14; + wire XLXN_15; + wire XLXN_16; + wire XLXN_27; + wire XLXN_28; - XNOR2 XLXI_1 (.I0(b0), - .I1(b1), - .O(XLXN_1)); AND2 XLXI_2 (.I0(XLXN_1), .I1(b2), .O(XLXN_4)); - NAND3 XLXI_3 (.I0(XLXN_5), - .I1(b1), - .I2(b2), - .O(XLXN_3)); OR2 XLXI_4 (.I0(XLXN_4), .I1(XLXN_3), .O(result)); - INV XLXI_5 (.I(b0), - .O(XLXN_5)); + INV XLXI_9 (.I(b1), + .O(XLXN_15)); + INV XLXI_10 (.I(b0), + .O(XLXN_16)); + AND3 XLXI_11 (.I0(b0), + .I1(XLXN_28), + .I2(XLXN_27), + .O(XLXN_3)); + INV XLXI_12 (.I(b2), + .O(XLXN_27)); + INV XLXI_13 (.I(b1), + .O(XLXN_28)); + OR2 XLXI_14 (.I0(XLXN_14), + .I1(XLXN_12), + .O(XLXN_1)); + AND2 XLXI_15 (.I0(b0), + .I1(b1), + .O(XLXN_12)); + AND2 XLXI_16 (.I0(XLXN_16), + .I1(XLXN_15), + .O(XLXN_14)); endmodule `timescale 1ns / 1ps @@ -67,24 +84,24 @@ module Modulo_1_MUSER_Modulo(b0, input b3; output result; - wire XLXN_1; wire XLXN_2; wire XLXN_3; wire XLXN_5; wire XLXN_6; wire XLXN_7; - wire XLXN_18; - wire XLXN_19; - wire XLXN_20; - wire XLXN_21; - wire XLXN_22; wire XLXN_23; wire XLXN_24; + wire XLXN_50; + wire XLXN_51; + wire XLXN_54; + wire XLXN_55; + wire XLXN_56; + wire XLXN_57; AND3 XLXI_1 (.I0(b1), .I1(b2), .I2(b3), - .O(XLXN_1)); + .O(XLXN_55)); AND3 XLXI_2 (.I0(XLXN_6), .I1(XLXN_5), .I2(b3), @@ -93,38 +110,38 @@ module Modulo_1_MUSER_Modulo(b0, .I1(XLXN_7), .I2(b3), .O(XLXN_3)); - OR3 XLXI_4 (.I0(XLXN_3), - .I1(XLXN_2), - .I2(XLXN_1), - .O(XLXN_21)); INV XLXI_5 (.I(b1), .O(XLXN_5)); INV XLXI_6 (.I(b0), .O(XLXN_6)); INV XLXI_7 (.I(b2), .O(XLXN_7)); - OR2 XLXI_9 (.I0(XLXN_20), - .I1(XLXN_21), - .O(result)); AND4 XLXI_11 (.I0(b0), .I1(XLXN_24), .I2(b2), .I3(XLXN_23), - .O(XLXN_19)); - OR2 XLXI_12 (.I0(XLXN_19), - .I1(XLXN_18), - .O(XLXN_20)); - NAND4 XLXI_13 (.I0(b0), - .I1(XLXN_22), - .I2(b2), - .I3(b3), - .O(XLXN_18)); - INV XLXI_14 (.I(b1), - .O(XLXN_22)); + .O(XLXN_57)); INV XLXI_15 (.I(b3), .O(XLXN_23)); INV XLXI_16 (.I(b1), .O(XLXN_24)); + AND4 XLXI_18 (.I0(XLXN_54), + .I1(b1), + .I2(XLXN_50), + .I3(XLXN_51), + .O(XLXN_56)); + INV XLXI_19 (.I(b2), + .O(XLXN_50)); + INV XLXI_20 (.I(b3), + .O(XLXN_51)); + INV XLXI_21 (.I(b0), + .O(XLXN_54)); + OR5 XLXI_22 (.I0(XLXN_57), + .I1(XLXN_56), + .I2(XLXN_3), + .I3(XLXN_2), + .I4(XLXN_55), + .O(result)); endmodule `timescale 1ns / 1ps diff --git a/Modulo_0.cmd_log b/Modulo_0.cmd_log index 8677539..c77853d 100755 --- a/Modulo_0.cmd_log +++ b/Modulo_0.cmd_log @@ -1,2 +1,6 @@ sch2sym -intstyle ise -family spartan6 -refsym Modulo_0 {X:/My Documents/ec311/lab1/Modulo_0.sch} {X:/My Documents/ec311/lab1/Modulo_0.sym} sch2sym -intstyle ise -family spartan6 -w -refsym Modulo_0 /home/michael/Documents/School/EC311/lab1/Modulo_0.sch /home/michael/Documents/School/EC311/lab1/Modulo_0.sym +sch2sym -intstyle ise -family spartan6 -w -refsym Modulo_0 {X:/My Documents/ec311/ec311-lab1/Modulo_0.sch} {X:/My Documents/ec311/ec311-lab1/Modulo_0.sym} +sch2sym -intstyle ise -family spartan6 -w -refsym Modulo_0 {X:/My Documents/ec311/ec311-lab1/Modulo_0.sch} {X:/My Documents/ec311/ec311-lab1/Modulo_0.sym} +sch2sym -intstyle ise -family spartan6 -w -refsym Modulo_0 {X:/My Documents/ec311/ec311-lab1/Modulo_0.sch} {X:/My Documents/ec311/ec311-lab1/Modulo_0.sym} +sch2sym -intstyle ise -family spartan6 -w -refsym Modulo_0 {X:/My Documents/ec311/ec311-lab1/Modulo_0.sch} {X:/My Documents/ec311/ec311-lab1/Modulo_0.sym} diff --git a/Modulo_0.sch b/Modulo_0.sch index f060ebf..096f110 100755 --- a/Modulo_0.sch +++ b/Modulo_0.sch @@ -9,31 +9,22 @@ - + + + + + + - - 2000-1-1T10:10:10 - - - - - - - - - - - - 2000-1-1T10:10:10 @@ -44,18 +35,6 @@ - - 2000-1-1T10:10:10 - - - - - - - - - - 2000-1-1T10:10:10 @@ -76,39 +55,70 @@ - - - - - + + 2000-1-1T10:10:10 + + + + + + + + + - - - - - - - + + + + + - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - - @@ -120,34 +130,16 @@ - - - - - - - - - - - - + + - - - - - - - - @@ -156,5 +148,63 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/Modulo_0.sym b/Modulo_0.sym index ed2353e..c12e4f0 100755 --- a/Modulo_0.sym +++ b/Modulo_0.sym @@ -1,24 +1,24 @@ - - - BLOCK - 2012-2-16T0:29:48 - - - - - - - - - - - - - - - - - - - - + + + BLOCK + 2012-2-17T0:51:57 + + + + + + + + + + + + + + + + + + + + diff --git a/Modulo_0.vf b/Modulo_0.vf index 0b8eb41..c0c56d3 100755 --- a/Modulo_0.vf +++ b/Modulo_0.vf @@ -7,11 +7,11 @@ // \ \ \/ Version : 13.3 // \ \ Application : sch2hdl // / / Filename : Modulo_0.vf -// /___/ /\ Timestamp : 02/15/2012 15:00:07 +// /___/ /\ Timestamp : 02/16/2012 19:52:31 // \ \ / \ // \___\/\___\ // -//Command: sch2hdl -intstyle ise -family spartan6 -verilog "X:/My Documents/ec311/lab1/Modulo_0.vf" -w "X:/My Documents/ec311/lab1/Modulo_0.sch" +//Command: sch2hdl -intstyle ise -family spartan6 -verilog "X:/My Documents/ec311/ec311-lab1/Modulo_0.vf" -w "X:/My Documents/ec311/ec311-lab1/Modulo_0.sch" //Design Name: Modulo_0 //Device: spartan6 //Purpose: @@ -35,21 +35,38 @@ module Modulo_0(b0, wire XLXN_1; wire XLXN_3; wire XLXN_4; - wire XLXN_5; + wire XLXN_12; + wire XLXN_14; + wire XLXN_15; + wire XLXN_16; + wire XLXN_27; + wire XLXN_28; - XNOR2 XLXI_1 (.I0(b0), - .I1(b1), - .O(XLXN_1)); AND2 XLXI_2 (.I0(XLXN_1), .I1(b2), .O(XLXN_4)); - NAND3 XLXI_3 (.I0(XLXN_5), - .I1(b1), - .I2(b2), - .O(XLXN_3)); OR2 XLXI_4 (.I0(XLXN_4), .I1(XLXN_3), .O(result)); - INV XLXI_5 (.I(b0), - .O(XLXN_5)); + INV XLXI_9 (.I(b1), + .O(XLXN_15)); + INV XLXI_10 (.I(b0), + .O(XLXN_16)); + AND3 XLXI_11 (.I0(b0), + .I1(XLXN_28), + .I2(XLXN_27), + .O(XLXN_3)); + INV XLXI_12 (.I(b2), + .O(XLXN_27)); + INV XLXI_13 (.I(b1), + .O(XLXN_28)); + OR2 XLXI_14 (.I0(XLXN_14), + .I1(XLXN_12), + .O(XLXN_1)); + AND2 XLXI_15 (.I0(b0), + .I1(b1), + .O(XLXN_12)); + AND2 XLXI_16 (.I0(XLXN_16), + .I1(XLXN_15), + .O(XLXN_14)); endmodule diff --git a/Modulo_1.cmd_log b/Modulo_1.cmd_log index 26beaf7..f539342 100755 --- a/Modulo_1.cmd_log +++ b/Modulo_1.cmd_log @@ -1,2 +1,5 @@ sch2sym -intstyle ise -family spartan6 -refsym Modulo_1 {X:/My Documents/ec311/lab1/Modulo_1.sch} {X:/My Documents/ec311/lab1/Modulo_1.sym} sch2sym -intstyle ise -family spartan6 -w -refsym Modulo_1 /home/michael/Documents/School/EC311/lab1/Modulo_1.sch /home/michael/Documents/School/EC311/lab1/Modulo_1.sym +sch2sym -intstyle ise -family spartan6 -w -refsym Modulo_1 {X:/My Documents/ec311/ec311-lab1/Modulo_1.sch} {X:/My Documents/ec311/ec311-lab1/Modulo_1.sym} +sch2sym -intstyle ise -family spartan6 -w -refsym Modulo_1 {X:/My Documents/ec311/ec311-lab1/Modulo_1.sch} {X:/My Documents/ec311/ec311-lab1/Modulo_1.sym} +sch2sym -intstyle ise -family spartan6 -w -refsym Modulo_1 {X:/My Documents/ec311/ec311-lab1/Modulo_1.sch} {X:/My Documents/ec311/ec311-lab1/Modulo_1.sym} diff --git a/Modulo_1.jhd b/Modulo_1.jhd index 435b81c..189c159 100755 --- a/Modulo_1.jhd +++ b/Modulo_1.jhd @@ -1 +1 @@ -MODULE Modulo_1 +MODULE Modulo_1 diff --git a/Modulo_1.sch b/Modulo_1.sch index dd65a0b..9a67697 100755 --- a/Modulo_1.sch +++ b/Modulo_1.sch @@ -1,295 +1,300 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 2000-1-1T10:10:10 - - - - - - - - - - - 2000-1-1T10:10:10 - - - - - - - - - - - - - - 2000-1-1T10:10:10 - - - - - - - - - 2000-1-1T10:10:10 - - - - - - - - - - - - 2000-1-1T10:10:10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2000-1-1T10:10:10 + + + + + + + + + + + 2000-1-1T10:10:10 + + + + + + + + + 2000-1-1T10:10:10 + + + + + + + + + + + + 2000-1-1T10:10:10 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/Modulo_1.sym b/Modulo_1.sym index cff6acb..42ecca1 100755 --- a/Modulo_1.sym +++ b/Modulo_1.sym @@ -1,24 +1,24 @@ - - - BLOCK - 2012-2-16T0:29:44 - - - - - - - - - - - - - - - - - - - - + + + BLOCK + 2012-2-17T0:43:13 + + + + + + + + + + + + + + + + + + + + diff --git a/Modulo_1.vf b/Modulo_1.vf index 8232c5f..5f6247d 100755 --- a/Modulo_1.vf +++ b/Modulo_1.vf @@ -7,11 +7,11 @@ // \ \ \/ Version : 13.3 // \ \ Application : sch2hdl // / / Filename : Modulo_1.vf -// /___/ /\ Timestamp : 02/15/2012 15:00:10 +// /___/ /\ Timestamp : 02/16/2012 19:44:03 // \ \ / \ // \___\/\___\ // -//Command: sch2hdl -intstyle ise -family spartan6 -verilog "X:/My Documents/ec311/lab1/Modulo_1.vf" -w "X:/My Documents/ec311/lab1/Modulo_1.sch" +//Command: sch2hdl -intstyle ise -family spartan6 -verilog "X:/My Documents/ec311/ec311-lab1/Modulo_1.vf" -w "X:/My Documents/ec311/ec311-lab1/Modulo_1.sch" //Design Name: Modulo_1 //Device: spartan6 //Purpose: @@ -32,24 +32,24 @@ module Modulo_1(b0, input b3; output result; - wire XLXN_1; wire XLXN_2; wire XLXN_3; wire XLXN_5; wire XLXN_6; wire XLXN_7; - wire XLXN_18; - wire XLXN_19; - wire XLXN_20; - wire XLXN_21; - wire XLXN_22; wire XLXN_23; wire XLXN_24; + wire XLXN_50; + wire XLXN_51; + wire XLXN_54; + wire XLXN_55; + wire XLXN_56; + wire XLXN_57; AND3 XLXI_1 (.I0(b1), .I1(b2), .I2(b3), - .O(XLXN_1)); + .O(XLXN_55)); AND3 XLXI_2 (.I0(XLXN_6), .I1(XLXN_5), .I2(b3), @@ -58,36 +58,36 @@ module Modulo_1(b0, .I1(XLXN_7), .I2(b3), .O(XLXN_3)); - OR3 XLXI_4 (.I0(XLXN_3), - .I1(XLXN_2), - .I2(XLXN_1), - .O(XLXN_21)); INV XLXI_5 (.I(b1), .O(XLXN_5)); INV XLXI_6 (.I(b0), .O(XLXN_6)); INV XLXI_7 (.I(b2), .O(XLXN_7)); - OR2 XLXI_9 (.I0(XLXN_20), - .I1(XLXN_21), - .O(result)); AND4 XLXI_11 (.I0(b0), .I1(XLXN_24), .I2(b2), .I3(XLXN_23), - .O(XLXN_19)); - OR2 XLXI_12 (.I0(XLXN_19), - .I1(XLXN_18), - .O(XLXN_20)); - NAND4 XLXI_13 (.I0(b0), - .I1(XLXN_22), - .I2(b2), - .I3(b3), - .O(XLXN_18)); - INV XLXI_14 (.I(b1), - .O(XLXN_22)); + .O(XLXN_57)); INV XLXI_15 (.I(b3), .O(XLXN_23)); INV XLXI_16 (.I(b1), .O(XLXN_24)); + AND4 XLXI_18 (.I0(XLXN_54), + .I1(b1), + .I2(XLXN_50), + .I3(XLXN_51), + .O(XLXN_56)); + INV XLXI_19 (.I(b2), + .O(XLXN_50)); + INV XLXI_20 (.I(b3), + .O(XLXN_51)); + INV XLXI_21 (.I(b0), + .O(XLXN_54)); + OR5 XLXI_22 (.I0(XLXN_57), + .I1(XLXN_56), + .I2(XLXN_3), + .I3(XLXN_2), + .I4(XLXN_55), + .O(result)); endmodule diff --git a/Modulo_3.cmd_log b/Modulo_3.cmd_log index 0734386..bd30288 100755 --- a/Modulo_3.cmd_log +++ b/Modulo_3.cmd_log @@ -1,2 +1,4 @@ sch2sym -intstyle ise -family spartan6 -refsym Modulo_3 {X:/My Documents/ec311/lab1/Modulo_3.sch} {X:/My Documents/ec311/lab1/Modulo_3.sym} sch2sym -intstyle ise -family spartan6 -w -refsym Modulo_3 /home/michael/Documents/School/EC311/lab1/Modulo_3.sch /home/michael/Documents/School/EC311/lab1/Modulo_3.sym +sch2sym -intstyle ise -family spartan6 -w -refsym Modulo_3 {X:/My Documents/ec311/ec311-lab1/Modulo_3.sch} {X:/My Documents/ec311/ec311-lab1/Modulo_3.sym} +sch2sym -intstyle ise -family spartan6 -w -refsym Modulo_3 {X:/My Documents/ec311/ec311-lab1/Modulo_3.sch} {X:/My Documents/ec311/ec311-lab1/Modulo_3.sym} diff --git a/Modulo_3.schlog b/Modulo_3.schlog new file mode 100755 index 0000000..69e4688 --- /dev/null +++ b/Modulo_3.schlog @@ -0,0 +1,2 @@ +select figure at 1561 1090 8 -branches -sn=1 +select figure at 1554 1281 8 -branches -sn=1 diff --git a/Modulo_3.sym b/Modulo_3.sym index de3738d..63f2cb1 100755 --- a/Modulo_3.sym +++ b/Modulo_3.sym @@ -1,24 +1,24 @@ - - - BLOCK - 2012-2-16T0:29:41 - - - - - - - - - - - - - - - - - - - - + + + BLOCK + 2012-2-17T0:37:33 + + + + + + + + + + + + + + + + + + + + diff --git a/Modulo_3.vf b/Modulo_3.vf index eef4bc0..50f1c0d 100755 --- a/Modulo_3.vf +++ b/Modulo_3.vf @@ -7,11 +7,11 @@ // \ \ \/ Version : 13.3 // \ \ Application : sch2hdl // / / Filename : Modulo_3.vf -// /___/ /\ Timestamp : 02/15/2012 15:00:10 +// /___/ /\ Timestamp : 02/16/2012 18:40:31 // \ \ / \ // \___\/\___\ // -//Command: sch2hdl -intstyle ise -family spartan6 -verilog "X:/My Documents/ec311/lab1/Modulo_3.vf" -w "X:/My Documents/ec311/lab1/Modulo_3.sch" +//Command: sch2hdl -intstyle ise -family spartan6 -verilog "X:/My Documents/ec311/ec311-lab1/Modulo_3.vf" -w "X:/My Documents/ec311/ec311-lab1/Modulo_3.sch" //Design Name: Modulo_3 //Device: spartan6 //Purpose: diff --git a/Negate.cmd_log b/Negate.cmd_log index f6426a6..28d7294 100755 --- a/Negate.cmd_log +++ b/Negate.cmd_log @@ -1,2 +1,6 @@ sch2sym -intstyle ise -family spartan6 -refsym Negate {X:/My Documents/ec311/lab1/Negate.sch} {X:/My Documents/ec311/lab1/Negate.sym} sch2sym -intstyle ise -family spartan6 -w -refsym Negate /home/michael/Documents/School/EC311/lab1/Negate.sch /home/michael/Documents/School/EC311/lab1/Negate.sym +sch2sym -intstyle ise -family spartan6 -w -refsym Negate {X:/My Documents/ec311/ec311-lab1/Negate.sch} {X:/My Documents/ec311/ec311-lab1/Negate.sym} +sch2sym -intstyle ise -family spartan6 -w -refsym Negate {X:/My Documents/ec311/ec311-lab1/Negate.sch} {X:/My Documents/ec311/ec311-lab1/Negate.sym} +sch2sym -intstyle ise -family spartan6 -w -refsym Negate {X:/My Documents/ec311/ec311-lab1/Negate.sch} {X:/My Documents/ec311/ec311-lab1/Negate.sym} +sch2sym -intstyle ise -family spartan6 -w -refsym Negate {X:/My Documents/ec311/ec311-lab1/Negate.sch} {X:/My Documents/ec311/ec311-lab1/Negate.sym} diff --git a/Negate.jhd b/Negate.jhd index 1fc293d..2436bdf 100755 --- a/Negate.jhd +++ b/Negate.jhd @@ -1,9 +1,9 @@ -MODULE Negate - SUBMODULE Negate_0 - INSTANCE XLXI_8 - SUBMODULE Negate_1 - INSTANCE XLXI_9 - SUBMODULE Negate_2 - INSTANCE XLXI_10 - SUBMODULE Negate_3 - INSTANCE XLXI_12 +MODULE Negate + SUBMODULE Negate_0 + INSTANCE XLXI_8 + SUBMODULE Negate_1 + INSTANCE XLXI_9 + SUBMODULE Negate_2 + INSTANCE XLXI_10 + SUBMODULE Negate_3 + INSTANCE XLXI_12 diff --git a/Negate.sch b/Negate.sch index e61f5b1..5d0ac8c 100755 --- a/Negate.sch +++ b/Negate.sch @@ -1,170 +1,170 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - 2012-2-16T0:44:2 - - - - - - - - - 2012-2-16T0:43:59 - - - - - - - - - 2012-2-16T0:43:56 - - - - - - - - - 2012-2-16T0:43:52 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + 2012-2-16T23:39:45 + + + + + + + + + 2012-2-16T23:39:49 + + + + + + + + + 2012-2-16T23:53:56 + + + + + + + + + 2012-2-16T23:39:56 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/Negate.schlog b/Negate.schlog new file mode 100755 index 0000000..e69de29 diff --git a/Negate.sym b/Negate.sym index 7528c93..7492348 100755 --- a/Negate.sym +++ b/Negate.sym @@ -1,33 +1,33 @@ - - - BLOCK - 2012-2-16T0:44:17 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + BLOCK + 2012-2-16T23:54:10 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/Negate.vf b/Negate.vf index 2f68f03..eb96691 100755 --- a/Negate.vf +++ b/Negate.vf @@ -7,11 +7,11 @@ // \ \ \/ Version : 13.3 // \ \ Application : sch2hdl // / / Filename : Negate.vf -// /___/ /\ Timestamp : 02/15/2012 15:00:10 +// /___/ /\ Timestamp : 02/16/2012 18:54:27 // \ \ / \ // \___\/\___\ // -//Command: sch2hdl -intstyle ise -family spartan6 -verilog "X:/My Documents/ec311/lab1/Negate.vf" -w "X:/My Documents/ec311/lab1/Negate.sch" +//Command: sch2hdl -intstyle ise -family spartan6 -verilog "X:/My Documents/ec311/ec311-lab1/Negate.vf" -w "X:/My Documents/ec311/ec311-lab1/Negate.sch" //Design Name: Negate //Device: spartan6 //Purpose: @@ -33,17 +33,17 @@ module Negate_3_MUSER_Negate(b0, output result; wire XLXN_8; - wire XLXN_9; + wire XLXN_10; - OR3 XLXI_5 (.I0(b2), - .I1(b1), - .I2(b0), - .O(XLXN_9)); - NAND2 XLXI_9 (.I0(XLXN_8), - .I1(b3), - .O(result)); - INV XLXI_12 (.I(XLXN_9), + OR3 XLXI_14 (.I0(b2), + .I1(b1), + .I2(b0), .O(XLXN_8)); + INV XLXI_15 (.I(b3), + .O(XLXN_10)); + AND2 XLXI_16 (.I0(XLXN_8), + .I1(XLXN_10), + .O(result)); endmodule `timescale 1ns / 1ps @@ -101,33 +101,38 @@ module Negate_2_MUSER_Negate(b0, input b3; output result; - wire XLXN_7; - wire XLXN_9; - wire XLXN_10; - wire XLXN_12; - wire XLXN_16; - wire XLXN_17; + wire XLXN_35; + wire XLXN_37; + wire XLXN_40; + wire XLXN_41; + wire XLXN_44; + wire XLXN_47; + wire XLXN_49; - AND2 XLXI_1 (.I0(XLXN_7), - .I1(b3), - .O(XLXN_9)); - AND3 XLXI_2 (.I0(b2), - .I1(XLXN_16), - .I2(XLXN_17), - .O(XLXN_10)); - OR2 XLXI_3 (.I0(XLXN_10), - .I1(XLXN_9), + OR4 XLXI_8 (.I0(XLXN_37), + .I1(XLXN_41), + .I2(XLXN_40), + .I3(XLXN_35), .O(result)); - OR3 XLXI_4 (.I0(XLXN_12), - .I1(b1), - .I2(b0), - .O(XLXN_7)); - INV XLXI_5 (.I(b2), - .O(XLXN_12)); - INV XLXI_6 (.I(b1), - .O(XLXN_16)); - INV XLXI_7 (.I(b0), - .O(XLXN_17)); + AND2 XLXI_9 (.I0(XLXN_44), + .I1(b3), + .O(XLXN_35)); + AND2 XLXI_10 (.I0(b1), + .I1(XLXN_44), + .O(XLXN_41)); + AND2 XLXI_11 (.I0(b0), + .I1(XLXN_44), + .O(XLXN_40)); + INV XLXI_14 (.I(b2), + .O(XLXN_44)); + AND3 XLXI_15 (.I0(XLXN_47), + .I1(XLXN_49), + .I2(b2), + .O(XLXN_37)); + INV XLXI_16 (.I(b1), + .O(XLXN_49)); + INV XLXI_17 (.I(b0), + .O(XLXN_47)); endmodule `timescale 1ns / 1ps diff --git a/Negate_0.cmd_log b/Negate_0.cmd_log index c334167..757de99 100755 --- a/Negate_0.cmd_log +++ b/Negate_0.cmd_log @@ -1,2 +1,4 @@ sch2sym -intstyle ise -family spartan6 -refsym Negate_0 {X:/My Documents/ec311/lab1/Negate_0.sch} {X:/My Documents/ec311/lab1/Negate_0.sym} sch2sym -intstyle ise -family spartan6 -w -refsym Negate_0 /home/michael/Documents/School/EC311/lab1/Negate_0.sch /home/michael/Documents/School/EC311/lab1/Negate_0.sym +sch2sym -intstyle ise -family spartan6 -w -refsym Negate_0 {X:/My Documents/ec311/ec311-lab1/Negate_0.sch} {X:/My Documents/ec311/ec311-lab1/Negate_0.sym} +sch2sym -intstyle ise -family spartan6 -w -refsym Negate_0 {X:/My Documents/ec311/ec311-lab1/Negate_0.sch} {X:/My Documents/ec311/ec311-lab1/Negate_0.sym} diff --git a/Negate_0.sym b/Negate_0.sym index 06adc0f..b101625 100755 --- a/Negate_0.sym +++ b/Negate_0.sym @@ -1,24 +1,24 @@ - - - BLOCK - 2012-2-16T0:44:2 - - - - - - - - - - - - - - - - - - - - + + + BLOCK + 2012-2-16T23:39:45 + + + + + + + + + + + + + + + + + + + + diff --git a/Negate_0.vf b/Negate_0.vf index 4ea3c60..3bdfa8b 100755 --- a/Negate_0.vf +++ b/Negate_0.vf @@ -7,11 +7,11 @@ // \ \ \/ Version : 13.3 // \ \ Application : sch2hdl // / / Filename : Negate_0.vf -// /___/ /\ Timestamp : 02/15/2012 15:00:09 +// /___/ /\ Timestamp : 02/16/2012 18:40:37 // \ \ / \ // \___\/\___\ // -//Command: sch2hdl -intstyle ise -family spartan6 -verilog "X:/My Documents/ec311/lab1/Negate_0.vf" -w "X:/My Documents/ec311/lab1/Negate_0.sch" +//Command: sch2hdl -intstyle ise -family spartan6 -verilog "X:/My Documents/ec311/ec311-lab1/Negate_0.vf" -w "X:/My Documents/ec311/ec311-lab1/Negate_0.sch" //Design Name: Negate_0 //Device: spartan6 //Purpose: diff --git a/Negate_1.cmd_log b/Negate_1.cmd_log index 8255945..c566d5e 100755 --- a/Negate_1.cmd_log +++ b/Negate_1.cmd_log @@ -1,2 +1,4 @@ sch2sym -intstyle ise -family spartan6 -refsym Negate_1 {X:/My Documents/ec311/lab1/Negate_1.sch} {X:/My Documents/ec311/lab1/Negate_1.sym} sch2sym -intstyle ise -family spartan6 -w -refsym Negate_1 /home/michael/Documents/School/EC311/lab1/Negate_1.sch /home/michael/Documents/School/EC311/lab1/Negate_1.sym +sch2sym -intstyle ise -family spartan6 -w -refsym Negate_1 {X:/My Documents/ec311/ec311-lab1/Negate_1.sch} {X:/My Documents/ec311/ec311-lab1/Negate_1.sym} +sch2sym -intstyle ise -family spartan6 -w -refsym Negate_1 {X:/My Documents/ec311/ec311-lab1/Negate_1.sch} {X:/My Documents/ec311/ec311-lab1/Negate_1.sym} diff --git a/Negate_1.sym b/Negate_1.sym index bd9722a..c530133 100755 --- a/Negate_1.sym +++ b/Negate_1.sym @@ -1,24 +1,24 @@ - - - BLOCK - 2012-2-16T0:43:59 - - - - - - - - - - - - - - - - - - - - + + + BLOCK + 2012-2-16T23:39:49 + + + + + + + + + + + + + + + + + + + + diff --git a/Negate_1.vf b/Negate_1.vf index 23a40c7..664d073 100755 --- a/Negate_1.vf +++ b/Negate_1.vf @@ -7,11 +7,11 @@ // \ \ \/ Version : 13.3 // \ \ Application : sch2hdl // / / Filename : Negate_1.vf -// /___/ /\ Timestamp : 02/15/2012 15:00:09 +// /___/ /\ Timestamp : 02/16/2012 18:40:35 // \ \ / \ // \___\/\___\ // -//Command: sch2hdl -intstyle ise -family spartan6 -verilog "X:/My Documents/ec311/lab1/Negate_1.vf" -w "X:/My Documents/ec311/lab1/Negate_1.sch" +//Command: sch2hdl -intstyle ise -family spartan6 -verilog "X:/My Documents/ec311/ec311-lab1/Negate_1.vf" -w "X:/My Documents/ec311/ec311-lab1/Negate_1.sch" //Design Name: Negate_1 //Device: spartan6 //Purpose: diff --git a/Negate_2.cmd_log b/Negate_2.cmd_log index c69baf9..eb4f0b5 100755 --- a/Negate_2.cmd_log +++ b/Negate_2.cmd_log @@ -1,2 +1,6 @@ sch2sym -intstyle ise -family spartan6 -refsym Negate_2 {X:/My Documents/ec311/lab1/Negate_2.sch} {X:/My Documents/ec311/lab1/Negate_2.sym} sch2sym -intstyle ise -family spartan6 -w -refsym Negate_2 /home/michael/Documents/School/EC311/lab1/Negate_2.sch /home/michael/Documents/School/EC311/lab1/Negate_2.sym +sch2sym -intstyle ise -family spartan6 -w -refsym Negate_2 {X:/My Documents/ec311/ec311-lab1/Negate_2.sch} {X:/My Documents/ec311/ec311-lab1/Negate_2.sym} +sch2sym -intstyle ise -family spartan6 -w -refsym Negate_2 {X:/My Documents/ec311/ec311-lab1/Negate_2.sch} {X:/My Documents/ec311/ec311-lab1/Negate_2.sym} +sch2sym -intstyle ise -family spartan6 -w -refsym Negate_2 {X:/My Documents/ec311/ec311-lab1/Negate_2.sch} {X:/My Documents/ec311/ec311-lab1/Negate_2.sym} +sch2sym -intstyle ise -family spartan6 -w -refsym Negate_2 {X:/My Documents/ec311/ec311-lab1/Negate_2.sch} {X:/My Documents/ec311/ec311-lab1/Negate_2.sym} diff --git a/Negate_2.jhd b/Negate_2.jhd index 237044d..ae25d66 100755 --- a/Negate_2.jhd +++ b/Negate_2.jhd @@ -1 +1 @@ -MODULE Negate_2 +MODULE Negate_2 diff --git a/Negate_2.sch b/Negate_2.sch index 2aa228c..5d7d5a3 100755 --- a/Negate_2.sch +++ b/Negate_2.sch @@ -1,179 +1,192 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - 2000-1-1T10:10:10 - - - - - - - - - - 2000-1-1T10:10:10 - - - - - - - - - - - - - - - 2000-1-1T10:10:10 - - - - - - - - - - - - 2000-1-1T10:10:10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2000-1-1T10:10:10 + + + + + + + + + + 2000-1-1T10:10:10 + + + + + + + + + + + + + + + 2000-1-1T10:10:10 + + + + + + + + + 2000-1-1T10:10:10 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/Negate_2.sym b/Negate_2.sym index 6763b85..92fd357 100755 --- a/Negate_2.sym +++ b/Negate_2.sym @@ -1,24 +1,24 @@ - - - BLOCK - 2012-2-16T0:43:56 - - - - - - - - - - - - - - - - - - - - + + + BLOCK + 2012-2-16T23:53:56 + + + + + + + + + + + + + + + + + + + + diff --git a/Negate_2.vf b/Negate_2.vf index 6ce41b2..b2302b8 100755 --- a/Negate_2.vf +++ b/Negate_2.vf @@ -7,11 +7,11 @@ // \ \ \/ Version : 13.3 // \ \ Application : sch2hdl // / / Filename : Negate_2.vf -// /___/ /\ Timestamp : 02/15/2012 15:00:09 +// /___/ /\ Timestamp : 02/16/2012 18:54:27 // \ \ / \ // \___\/\___\ // -//Command: sch2hdl -intstyle ise -family spartan6 -verilog "X:/My Documents/ec311/lab1/Negate_2.vf" -w "X:/My Documents/ec311/lab1/Negate_2.sch" +//Command: sch2hdl -intstyle ise -family spartan6 -verilog "X:/My Documents/ec311/ec311-lab1/Negate_2.vf" -w "X:/My Documents/ec311/ec311-lab1/Negate_2.sch" //Design Name: Negate_2 //Device: spartan6 //Purpose: @@ -32,31 +32,36 @@ module Negate_2(b0, input b3; output result; - wire XLXN_7; - wire XLXN_9; - wire XLXN_10; - wire XLXN_12; - wire XLXN_16; - wire XLXN_17; + wire XLXN_35; + wire XLXN_37; + wire XLXN_40; + wire XLXN_41; + wire XLXN_44; + wire XLXN_47; + wire XLXN_49; - AND2 XLXI_1 (.I0(XLXN_7), - .I1(b3), - .O(XLXN_9)); - AND3 XLXI_2 (.I0(b2), - .I1(XLXN_16), - .I2(XLXN_17), - .O(XLXN_10)); - OR2 XLXI_3 (.I0(XLXN_10), - .I1(XLXN_9), + OR4 XLXI_8 (.I0(XLXN_37), + .I1(XLXN_41), + .I2(XLXN_40), + .I3(XLXN_35), .O(result)); - OR3 XLXI_4 (.I0(XLXN_12), - .I1(b1), - .I2(b0), - .O(XLXN_7)); - INV XLXI_5 (.I(b2), - .O(XLXN_12)); - INV XLXI_6 (.I(b1), - .O(XLXN_16)); - INV XLXI_7 (.I(b0), - .O(XLXN_17)); + AND2 XLXI_9 (.I0(XLXN_44), + .I1(b3), + .O(XLXN_35)); + AND2 XLXI_10 (.I0(b1), + .I1(XLXN_44), + .O(XLXN_41)); + AND2 XLXI_11 (.I0(b0), + .I1(XLXN_44), + .O(XLXN_40)); + INV XLXI_14 (.I(b2), + .O(XLXN_44)); + AND3 XLXI_15 (.I0(XLXN_47), + .I1(XLXN_49), + .I2(b2), + .O(XLXN_37)); + INV XLXI_16 (.I(b1), + .O(XLXN_49)); + INV XLXI_17 (.I(b0), + .O(XLXN_47)); endmodule diff --git a/Negate_3.cmd_log b/Negate_3.cmd_log index 3df4b90..253b96d 100755 --- a/Negate_3.cmd_log +++ b/Negate_3.cmd_log @@ -1,2 +1,4 @@ sch2sym -intstyle ise -family spartan6 -refsym Negate_3 {X:/My Documents/ec311/lab1/Negate_3.sch} {X:/My Documents/ec311/lab1/Negate_3.sym} sch2sym -intstyle ise -family spartan6 -w -refsym Negate_3 /home/michael/Documents/School/EC311/lab1/Negate_3.sch /home/michael/Documents/School/EC311/lab1/Negate_3.sym +sch2sym -intstyle ise -family spartan6 -w -refsym Negate_3 {X:/My Documents/ec311/ec311-lab1/Negate_3.sch} {X:/My Documents/ec311/ec311-lab1/Negate_3.sym} +sch2sym -intstyle ise -family spartan6 -w -refsym Negate_3 {X:/My Documents/ec311/ec311-lab1/Negate_3.sch} {X:/My Documents/ec311/ec311-lab1/Negate_3.sym} diff --git a/Negate_3.jhd b/Negate_3.jhd index a943761..8ba0414 100755 --- a/Negate_3.jhd +++ b/Negate_3.jhd @@ -1 +1 @@ -MODULE Negate_3 +MODULE Negate_3 diff --git a/Negate_3.sch b/Negate_3.sch index 7568688..01b6d13 100755 --- a/Negate_3.sch +++ b/Negate_3.sch @@ -1,89 +1,105 @@ - - - - - - - - - - - - - - - - - - - - - 2000-1-1T10:10:10 - - - - - - - - - - - 2000-1-1T10:10:10 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + + + + + + + + + + + + + + + + + + + 2000-1-1T10:10:10 + + + + + + + + + + + + + + 2000-1-1T10:10:10 + + + + + + + + + 2000-1-1T10:10:10 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/Negate_3.sym b/Negate_3.sym index 3a12c24..f222519 100755 --- a/Negate_3.sym +++ b/Negate_3.sym @@ -1,24 +1,24 @@ - - - BLOCK - 2012-2-16T0:43:52 - - - - - - - - - - - - - - - - - - - - + + + BLOCK + 2012-2-16T23:39:56 + + + + + + + + + + + + + + + + + + + + diff --git a/Negate_3.vf b/Negate_3.vf index 7205c3a..4b821ca 100755 --- a/Negate_3.vf +++ b/Negate_3.vf @@ -7,11 +7,11 @@ // \ \ \/ Version : 13.3 // \ \ Application : sch2hdl // / / Filename : Negate_3.vf -// /___/ /\ Timestamp : 02/15/2012 15:00:08 +// /___/ /\ Timestamp : 02/16/2012 19:22:52 // \ \ / \ // \___\/\___\ // -//Command: sch2hdl -intstyle ise -family spartan6 -verilog "X:/My Documents/ec311/lab1/Negate_3.vf" -w "X:/My Documents/ec311/lab1/Negate_3.sch" +//Command: sch2hdl -intstyle ise -family spartan6 -verilog "X:/My Documents/ec311/ec311-lab1/Negate_3.vf" -w "X:/My Documents/ec311/ec311-lab1/Negate_3.sch" //Design Name: Negate_3 //Device: spartan6 //Purpose: @@ -33,15 +33,15 @@ module Negate_3(b0, output result; wire XLXN_8; - wire XLXN_9; + wire XLXN_10; - OR3 XLXI_5 (.I0(b2), - .I1(b1), - .I2(b0), - .O(XLXN_9)); - NAND2 XLXI_9 (.I0(XLXN_8), - .I1(b3), - .O(result)); - INV XLXI_12 (.I(XLXN_9), + OR3 XLXI_14 (.I0(b2), + .I1(b1), + .I2(b0), .O(XLXN_8)); + INV XLXI_15 (.I(b3), + .O(XLXN_10)); + AND2 XLXI_16 (.I0(XLXN_8), + .I1(XLXN_10), + .O(result)); endmodule diff --git a/_ngo/netlist.lst b/_ngo/netlist.lst index c77d9e2..8d387ea 100755 --- a/_ngo/netlist.lst +++ b/_ngo/netlist.lst @@ -1,2 +1,2 @@ -X:\My Documents\ec311\lab1\ALU.ngc 1329336939 +X:\My Documents\ec311\ec311-lab1\ALU.ngc 1329439965 OK diff --git a/_xmsgs/bitgen.xmsgs b/_xmsgs/bitgen.xmsgs index 78d5ffb..6581d17 100755 --- a/_xmsgs/bitgen.xmsgs +++ b/_xmsgs/bitgen.xmsgs @@ -5,7 +5,7 @@ behavior or data corruption. It is strongly advised that users do not edit the contents of this file. --> -Setting the Persist option to "Yes" with the CONFIG_MODE constraint value "UnSpecified" will result in the 8-bit SelectMap port being persisted. +Setting the Persist option to "Yes" with the CONFIG_MODE constraint value "UnSpecified" will result in the 8-bit SelectMap port being persisted. diff --git a/_xmsgs/map.xmsgs b/_xmsgs/map.xmsgs index b32095a..4ecf2a7 100755 --- a/_xmsgs/map.xmsgs +++ b/_xmsgs/map.xmsgs @@ -5,22 +5,22 @@ behavior or data corruption. It is strongly advised that users do not edit the contents of this file. --> -No environment variables are currently set. +No environment variables are currently set. -All of the single ended outputs in this design are using slew rate limited output drivers. The delay on speed critical single ended outputs can be dramatically reduced by designating them as fast outputs. +All of the single ended outputs in this design are using slew rate limited output drivers. The delay on speed critical single ended outputs can be dramatically reduced by designating them as fast outputs. -Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius) +Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius) -Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts) +Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts) -The Interim Design Summary has been generated in the MAP Report (.mrp). +The Interim Design Summary has been generated in the MAP Report (.mrp). -Map created a placed design. +Map created a placed design. diff --git a/_xmsgs/par.xmsgs b/_xmsgs/par.xmsgs index 848b12c..5f1f5f1 100755 --- a/_xmsgs/par.xmsgs +++ b/_xmsgs/par.xmsgs @@ -5,10 +5,10 @@ behavior or data corruption. It is strongly advised that users do not edit the contents of this file. --> -No user timing constraints were detected or you have set the option to ignore timing constraints ("par -x"). Place and Route will run in "Performance Evaluation Mode" to automatically improve the performance of all internal clocks in this design. Because there are not defined timing requirements, a timing score will not be reported in the PAR report in this mode. The PAR timing summary will list the performance achieved for each clock. Note: For the fastest runtime, set the effort level to "std". For best performance, set the effort level to "high". +No user timing constraints were detected or you have set the option to ignore timing constraints ("par -x"). Place and Route will run in "Performance Evaluation Mode" to automatically improve the performance of all internal clocks in this design. Because there are not defined timing requirements, a timing score will not be reported in the PAR report in this mode. The PAR timing summary will list the performance achieved for each clock. Note: For the fastest runtime, set the effort level to "std". For best performance, set the effort level to "high". -The Clock Report is not displayed in the non timing-driven mode. +The Clock Report is not displayed in the non timing-driven mode. diff --git a/_xmsgs/pn_parser.xmsgs b/_xmsgs/pn_parser.xmsgs index 2211003..ee464b0 100755 --- a/_xmsgs/pn_parser.xmsgs +++ b/_xmsgs/pn_parser.xmsgs @@ -1,12 +1,12 @@ - - - - - - - - - - - - + + + + + + + + + + + + diff --git a/_xmsgs/trce.xmsgs b/_xmsgs/trce.xmsgs index 120dfa1..80cb2e4 100755 --- a/_xmsgs/trce.xmsgs +++ b/_xmsgs/trce.xmsgs @@ -5,11 +5,11 @@ behavior or data corruption. It is strongly advised that users do not edit the contents of this file. --> -No timing constraints found, doing default enumeration. +No timing constraints found, doing default enumeration. -To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report. +To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report. -The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet. +The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet. diff --git a/alu.bgn b/alu.bgn index f3ad255..6d6d984 100755 --- a/alu.bgn +++ b/alu.bgn @@ -5,7 +5,7 @@ C:\Xilinx\13.3\ISE_DS\ISE\. "ALU" is an NCD, version 3.2, device xc6slx16, package csg324, speed -3 Opened constraints file ALU.pcf. -Wed Feb 15 15:16:39 2012 +Thu Feb 16 19:53:39 2012 C:\Xilinx\13.3\ISE_DS\ISE\bin\nt64\unwrapped\bitgen.exe -intstyle ise -w -g DebugBitstream:No -g Binary:no -g CRC:Enable -g Reset_on_err:No -g ConfigRate:2 -g ProgPin:PullUp -g TckPin:PullUp -g TdiPin:PullUp -g TdoPin:PullUp -g TmsPin:PullUp -g UnusedPin:PullDown -g UserID:0xFFFFFFFF -g ExtMasterCclk_en:No -g SPI_buswidth:1 -g TIMER_CFG:0xFFFF -g multipin_wakeup:No -g StartUpClk:JtagClk -g DONE_cycle:4 -g GTS_cycle:5 -g GWE_cycle:6 -g LCK_cycle:NoWait -g Security:None -g Persist:Yes -m -g ReadBack -g DonePipe:No -g DriveDone:No -g en_sw_gsr:No -g drive_awake:No -g sw_clk:Startupclk -g sw_gwe_cycle:5 -g sw_gts_cycle:4 ALU.ncd diff --git a/alu.bit b/alu.bit index a9ad5c0..4b4dd13 100755 Binary files a/alu.bit and b/alu.bit differ diff --git a/alu.drc b/alu.drc index 39644f9..f6dcace 100755 --- a/alu.drc +++ b/alu.drc @@ -1,7 +1,7 @@ Release 13.3 Drc O.76xd (nt64) Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. -Wed Feb 15 15:16:39 2012 +Thu Feb 16 19:53:39 2012 drc -z ALU.ncd ALU.pcf diff --git a/alu.msd b/alu.msd index b05823c..48c0ca2 100755 --- a/alu.msd +++ b/alu.msd @@ -4,7 +4,7 @@ Design name: ALU.ncd;UserID=0xFFFFFFFF Architecture: spartan6 Part: 6slx16csg324 Type: mask -Date: Wed Feb 15 15:16:40 2012 +Date: Thu Feb 16 19:53:41 2012 Bits: 3711248 1111111111111111 1111111111111111 diff --git a/alu.msk b/alu.msk index 4f0c2a8..000ece4 100755 Binary files a/alu.msk and b/alu.msk differ diff --git a/alu.rbb b/alu.rbb index 7cf8d8e..e027349 100755 Binary files a/alu.rbb and b/alu.rbb differ diff --git a/alu.rbd b/alu.rbd index f52b655..342558b 100755 --- a/alu.rbd +++ b/alu.rbd @@ -4,7 +4,7 @@ Design name: ALU.ncd;UserID=0xFFFFFFFF Architecture: spartan6 Part: 6slx16csg324 Type: readback -Date: Wed Feb 15 15:16:40 2012 +Date: Thu Feb 16 19:53:41 2012 Bits: 3711248 0000000000000000 0000000000000000 @@ -23535,10 +23535,7 @@ Bits: 3711248 0000000000000000 0000000000000000 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b/iseconfig/ALU.xreport index dbe97f4..20fba66 100755 --- a/iseconfig/ALU.xreport +++ b/iseconfig/ALU.xreport @@ -1,11 +1,11 @@
- 2012-02-15T19:01:09 + 2012-02-16T18:37:40 ALU - Unknown - /home/michael/Documents/School/EC311/lab1/iseconfig/ALU.xreport - /home/michael/Documents/School/EC311/lab1/ + 2012-02-16T18:30:33 + X:/My Documents/ec311/ec311-lab1/iseconfig/ALU.xreport + X:/My Documents/ec311/ec311-lab1\ 2012-02-15T14:52:54 false
diff --git a/iseconfig/lab1.projectmgr b/iseconfig/lab1.projectmgr index 6dc197a..2b2f3c6 100755 --- a/iseconfig/lab1.projectmgr +++ b/iseconfig/lab1.projectmgr @@ -1,79 +1,77 @@ - - - - - - - - - 2 - /ALU X:|My Documents|ec311|lab1|ALU.sch/XLXI_1 - Divide - /ALU X:|My Documents|ec311|lab1|ALU.sch/XLXI_2 - Modulo - /ALU X:|My Documents|ec311|lab1|ALU.sch/XLXI_3 - Negate - - - ALU (/home/michael/Documents/School/EC311/lab1/ALU.sch) - - 0 - 0 - 000000ff00000000000000010000000100000000000000000000000000000000020200000001000000010000006400000150000000020000000000000000000000000200000064ffffffff000000810000000300000002000001500000000100000003000000000000000100000003 - true - ALU (/home/michael/Documents/School/EC311/lab1/ALU.sch) - - - - 1 - - - Update All Schematic Files - - 0 - 0 - 000000ff00000000000000010000000100000000000000000000000000000000000000000000000183000000010000000100000000000000000000000064ffffffff000000810000000000000001000001830000000100000000 - false - Update All Schematic Files - - - - 1 - - - Modulo_1.sch - - 0 - 0 - 000000ff00000000000000010000000000000000010000000000000000000000000000000000000287000000040101000100000000000000000000000064ffffffff0000008100000000000000040000008300000001000000000000002400000001000000000000006600000001000000000000017a0000000100000000 - false - Modulo_1.sch - - - - 1 - work - - - 0 - 0 - 000000ff00000000000000010000000000000000010000000000000000000000000000000000000117000000010001000100000000000000000000000064ffffffff000000810000000000000001000001170000000100000000 - false - work - - - - 1 - Implement Design/Map - Implement Design/Place & Route - Implement Design/Translate - - - - - 0 - 0 - 000000ff00000000000000010000000100000000000000000000000000000000000000000000000173000000010000000100000000000000000000000064ffffffff000000810000000000000001000001730000000100000000 - false - - - 000000ff00000000000000020000011b0000011b01000000050100000002 - Implementation - + + + + + + + + + 2 + /ALU X:|My Documents|ec311|lab1|ALU.sch/XLXI_1 - Divide + /ALU X:|My Documents|ec311|lab1|ALU.sch/XLXI_2 - Modulo + /ALU X:|My Documents|ec311|lab1|ALU.sch/XLXI_3 - Negate + + + ALU (X:/My Documents/ec311/ec311-lab1/ALU.sch) + + 0 + 0 + 000000ff0000000000000001000000010000000000000000000000000000000002020000000100000001000000640000012b000000020000000000000000000000000200000064ffffffff0000008100000003000000020000012b0000000100000003000000000000000100000003 + true + ALU (X:/My Documents/ec311/ec311-lab1/ALU.sch) + + + + 1 + + + Update All Schematic Files + + 0 + 0 + 000000ff00000000000000010000000100000000000000000000000000000000000000000000000140000000010000000100000000000000000000000064ffffffff000000810000000000000001000001400000000100000000 + false + Update All Schematic Files + + + + 1 + + + 0 + 0 + 000000ff00000000000000010000000000000000010000000000000000000000000000000000000171000000040101000100000000000000000000000064ffffffff000000810000000000000004000000830000000100000000000000240000000100000000000000660000000100000000000000640000000100000000 + false + Modulo_0.sch + + + + 1 + work + + + 0 + 0 + 000000ff00000000000000010000000000000000010000000000000000000000000000000000000140000000010001000100000000000000000000000064ffffffff000000810000000000000001000001400000000100000000 + false + work + + + + 1 + Implement Design/Map + Implement Design/Place & Route + Implement Design/Translate + + + Generate Programming File + + 9 + 0 + 000000ff0000000000000001000000010000000000000000000000000000000000000000000000012f000000010000000100000000000000000000000064ffffffff0000008100000000000000010000012f0000000100000000 + false + Generate Programming File + + 000000ff00000000000000020000011b0000011b01000000050100000002 + Implementation + diff --git a/lab1.gise b/lab1.gise index 054a65f..68616f9 100755 --- a/lab1.gise +++ b/lab1.gise @@ -36,6 +36,7 @@ + @@ -44,6 +45,7 @@ + @@ -98,6 +100,7 @@ + @@ -115,11 +118,9 @@ - + - - @@ -152,18 +153,15 @@ - - - + - @@ -179,25 +177,22 @@ - + - - + - - + - @@ -210,10 +205,9 @@ - + - @@ -225,12 +219,9 @@ - + - - - @@ -241,15 +232,21 @@ - + - + + + + + + + + - + - diff --git a/lab1.xise b/lab1.xise index 5bf0c30..9526429 100755 --- a/lab1.xise +++ b/lab1.xise @@ -12,7 +12,7 @@ - + @@ -109,7 +109,7 @@ - + @@ -226,7 +226,6 @@ - diff --git a/pa.fromHdl.tcl b/pa.fromHdl.tcl index 68516e9..42b9671 100755 --- a/pa.fromHdl.tcl +++ b/pa.fromHdl.tcl @@ -1,7 +1,7 @@ # PlanAhead Launch Script for Pre-Synthesis Floorplanning, created by Project Navigator -create_project -name lab1 -dir "X:/My Documents/ec311/lab1/planAhead_run_1" -part xc6slx16csg324-3 +create_project -name lab1 -dir "X:/My Documents/ec311/ec311-lab1/planAhead_run_1" -part xc6slx16csg324-3 set_param project.pinAheadLayout yes set srcset [get_property srcset [current_run -impl]] set_property top ALU $srcset diff --git a/pa.fromNetlist.tcl b/pa.fromNetlist.tcl index d74db7f..0391841 100755 --- a/pa.fromNetlist.tcl +++ b/pa.fromNetlist.tcl @@ -1,10 +1,10 @@ # PlanAhead Launch Script for Post-Synthesis pin planning, created by Project Navigator -create_project -name lab1 -dir "X:/My Documents/ec311/lab1/planAhead_run_1" -part xc6slx16csg324-3 +create_project -name lab1 -dir "X:/My Documents/ec311/ec311-lab1/planAhead_run_2" -part xc6slx16csg324-3 set_property design_mode GateLvl [get_property srcset [current_run -impl]] -set_property edif_top_file "X:/My Documents/ec311/lab1/ALU.ngc" [ get_property srcset [ current_run ] ] -add_files -norecurse { {X:/My Documents/ec311/lab1} } +set_property edif_top_file "X:/My Documents/ec311/ec311-lab1/ALU.ngc" [ get_property srcset [ current_run ] ] +add_files -norecurse { {X:/My Documents/ec311/ec311-lab1} } set_param project.pinAheadLayout yes set_property target_constrs_file "ALU.ucf" [current_fileset -constrset] add_files [list {ALU.ucf}] -fileset [get_property constrset [current_run]] diff --git a/par_usage_statistics.html b/par_usage_statistics.html index 00cf4de..3088792 100755 --- a/par_usage_statistics.html +++ b/par_usage_statistics.html @@ -6,20 +6,20 @@
- - - - + + + + - - + + - - + + @@ -27,6 +27,6 @@ - +
Total Non-vccgnd Conns=63
Total Non-vccgnd Timing Constrained Conns=0
Phase 1 CPU=4.6 sec
Phase 2 CPU=4.6 sec
Phase 3 CPU=5.4 sec
Phase 4 CPU=6.1 sec
Phase 5 CPU=6.2 sec
Phase 2 CPU=4.7 sec
Phase 3 CPU=5.5 sec
Phase 4 CPU=6.3 sec
Phase 5 CPU=6.3 sec
Phase 6 CPU=6.3 sec
Phase 7 CPU=6.3 sec
Phase 8 CPU=6.3 sec
Phase 9 CPU=6.3 sec
Phase 10 CPU=6.3 sec
AvgWirelenPerPin Fanout 1=25.0
AvgWirelenPerPin Fanout 2=0.5
AvgWirelenPerPin Fanout 1=27.0
AvgWirelenPerPin Fanout 2=1.0
AvgWirelenPerPin Fanout 3=0.0
AvgWirelenPerPin Fanout 4=37.8
AvgWirelenPerPin Fanout 10=5.6
AvgWirelenPerPin Fanout 4=38.3
AvgWirelenPerPin Fanout 10=5.5
AvgWirelenPerPin Fanout 50=0.0
AvgWirelenPerPin Fanout 100=0.0
AvgWirelenPerPin Fanout 500=0.0
AvgWirelenPerPin Fanout 20000=0.0
AvgWirelenPerPin Fanout 50000=0.0
AvgWirelenPerPin Fanout 100000=0.0
IRR Gamma=1.0040
IRR Gamma=1.0011
diff --git a/planAhead.ngc2edif.log b/planAhead.ngc2edif.log index 00c1f0a..cf6c2fc 100755 --- a/planAhead.ngc2edif.log +++ b/planAhead.ngc2edif.log @@ -9,3 +9,91 @@ Processing design ... Writing EDIF netlist file ALU.edif ... ngc2edif: Total memory usage is 78968 kilobytes +Release 13.3 - ngc2edif O.76xd (nt64) +Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. +Reading design ALU.ngc ... +WARNING:NetListWriters:298 - No output is written to ALU.xncf, ignored. +Processing design ... + Preping design's networks ... + Preping design's macros ... + finished :Prep +Writing EDIF netlist file ALU.edif ... +ngc2edif: Total memory usage is 91624 kilobytes + +Release 13.3 - ngc2edif O.76xd (nt64) +Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. +Reading design ALU.ngc ... +WARNING:NetListWriters:298 - No output is written to ALU.xncf, ignored. +Processing design ... + Preping design's networks ... + Preping design's macros ... + finished :Prep +Writing EDIF netlist file ALU.edif ... +ngc2edif: Total memory usage is 91624 kilobytes + +Release 13.3 - ngc2edif O.76xd (nt64) +Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. +Reading design ALU.ngc ... +WARNING:NetListWriters:298 - No output is written to ALU.xncf, ignored. +Processing design ... + Preping design's networks ... + Preping design's macros ... + finished :Prep +Writing EDIF netlist file ALU.edif ... +ngc2edif: Total memory usage is 91432 kilobytes + +Release 13.3 - ngc2edif O.76xd (nt64) +Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. +Reading design ALU.ngc ... +WARNING:NetListWriters:298 - No output is written to ALU.xncf, ignored. +Processing design ... + Preping design's networks ... + Preping design's macros ... + finished :Prep +Writing EDIF netlist file ALU.edif ... +ngc2edif: Total memory usage is 91752 kilobytes + +Release 13.3 - ngc2edif O.76xd (nt64) +Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. +Reading design ALU.ngc ... +WARNING:NetListWriters:298 - No output is written to ALU.xncf, ignored. +Processing design ... + Preping design's networks ... + Preping design's macros ... + finished :Prep +Writing EDIF netlist file ALU.edif ... +ngc2edif: Total memory usage is 91560 kilobytes + +Release 13.3 - ngc2edif O.76xd (nt64) +Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. +Reading design ALU.ngc ... +WARNING:NetListWriters:298 - No output is written to ALU.xncf, ignored. +Processing design ... + Preping design's networks ... + Preping design's macros ... + finished :Prep +Writing EDIF netlist file ALU.edif ... +ngc2edif: Total memory usage is 91880 kilobytes + +Release 13.3 - ngc2edif O.76xd (nt64) +Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. +Reading design ALU.ngc ... +WARNING:NetListWriters:298 - No output is written to ALU.xncf, ignored. +Processing design ... + Preping design's networks ... + Preping design's macros ... + finished :Prep +Writing EDIF netlist file ALU.edif ... +ngc2edif: Total memory usage is 91368 kilobytes + +Release 13.3 - ngc2edif O.76xd (nt64) +Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. +Reading design ALU.ngc ... +WARNING:NetListWriters:298 - No output is written to ALU.xncf, ignored. +Processing design ... + Preping design's networks ... + Preping design's macros ... + finished :Prep +Writing EDIF netlist file ALU.edif ... +ngc2edif: Total memory usage is 91304 kilobytes + diff --git a/planAhead_run_1/lab1.data/cache/ALU_ngc_c04f956c.edif b/planAhead_run_1/lab1.data/cache/ALU_ngc_c04f956c.edif new file mode 100755 index 0000000..0b84157 --- /dev/null +++ b/planAhead_run_1/lab1.data/cache/ALU_ngc_c04f956c.edif @@ -0,0 +1,2404 @@ +(edif ALU + (edifVersion 2 0 0) + (edifLevel 0) + (keywordMap (keywordLevel 0)) + (status + (written + (timestamp 2012 2 16 18 17 18) + (program "Xilinx ngc2edif" (version "O.76xd")) + (author "Xilinx. Inc ") + (comment "This EDIF netlist is to be used within supported synthesis tools") + (comment "for determining resource/timing estimates of the design component") + (comment "represented by this netlist.") + (comment "Command line: -mdp2sp -w -secure ALU.ngc ALU.edif "))) + (external UNISIMS + (edifLevel 0) + (technology (numberDefinition)) + (cell GND + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port G + (direction OUTPUT) + ) + ) + ) + ) + (cell VCC + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port P + (direction OUTPUT) + ) + ) + ) + ) + (cell OR3 + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port I0 + (direction INPUT) + ) + (port I1 + (direction INPUT) + ) + (port I2 + (direction INPUT) + ) + (port O + (direction OUTPUT) + ) + ) + ) + ) + (cell OR2 + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port I0 + (direction INPUT) + ) + (port I1 + (direction INPUT) + ) + (port O + (direction OUTPUT) + ) + ) + ) + ) + (cell INV + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port I + (direction INPUT) + ) + (port O + (direction OUTPUT) + ) + ) + ) + ) + (cell AND2 + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port I0 + (direction INPUT) + ) + (port I1 + (direction INPUT) + ) + (port O + (direction OUTPUT) + ) + ) + ) + ) + (cell AND4 + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port I0 + (direction INPUT) + ) + (port I1 + (direction INPUT) + ) + (port I2 + (direction INPUT) + ) + (port I3 + (direction INPUT) + ) + (port O + (direction OUTPUT) + ) + ) + ) + ) + (cell NOR3 + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port I0 + (direction INPUT) + ) + (port I1 + (direction INPUT) + ) + (port I2 + (direction INPUT) + ) + (port O + (direction OUTPUT) + ) + ) + ) + ) + (cell AND3 + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port I0 + (direction INPUT) + ) + (port I1 + (direction INPUT) + ) + (port I2 + (direction INPUT) + ) + (port O + (direction OUTPUT) + ) + ) + ) + ) + (cell NAND4 + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port I0 + (direction INPUT) + ) + (port I1 + (direction INPUT) + ) + (port I2 + (direction INPUT) + ) + (port I3 + (direction INPUT) + ) + (port O + (direction OUTPUT) + ) + ) + ) + ) + (cell NAND3 + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port I0 + (direction INPUT) + ) + (port I1 + (direction INPUT) + ) + (port I2 + (direction INPUT) + ) + (port O + (direction OUTPUT) + ) + ) + ) + ) + (cell XNOR2 + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port I0 + (direction INPUT) + ) + (port I1 + (direction INPUT) + ) + (port O + (direction OUTPUT) + ) + ) + ) + ) + (cell OR4 + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port I0 + (direction INPUT) + ) + (port I1 + (direction INPUT) + ) + (port I2 + (direction INPUT) + ) + (port I3 + (direction INPUT) + ) + (port O + (direction OUTPUT) + ) + ) + ) + ) + (cell NAND2 + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port I0 + (direction INPUT) + ) + (port I1 + (direction INPUT) + ) + (port O + (direction OUTPUT) + ) + ) + ) + ) + (cell LUT6 + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port I0 + (direction INPUT) + ) + (port I1 + (direction INPUT) + ) + (port I2 + (direction INPUT) + ) + (port I3 + (direction INPUT) + ) + (port I4 + (direction INPUT) + ) + (port I5 + (direction INPUT) + ) + (port O + (direction OUTPUT) + ) + ) + ) + ) + (cell BUF + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port I + (direction INPUT) + ) + (port O + (direction OUTPUT) + ) + ) + ) + ) + (cell OR5 + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port I0 + (direction INPUT) + ) + (port I1 + (direction INPUT) + ) + (port I2 + (direction INPUT) + ) + (port I3 + (direction INPUT) + ) + (port I4 + (direction INPUT) + ) + (port O + (direction OUTPUT) + ) + ) + ) + ) + (cell XOR2 + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port I0 + (direction INPUT) + ) + (port I1 + (direction INPUT) + ) + (port O + (direction OUTPUT) + ) + ) + ) + ) + (cell IBUF + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port I + (direction INPUT) + ) + (port O + (direction OUTPUT) + ) + ) + ) + ) + (cell OBUF + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port I + (direction INPUT) + ) + (port O + (direction OUTPUT) + ) + ) + ) + ) + ) + + (library ALU_lib + (edifLevel 0) + (technology (numberDefinition)) + (cell (rename M4_1E_HXILINX_ALU_NO3_XLXI_4 "M4_1E_HXILINX_ALU") + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port D0 + (direction INPUT) + ) + (port D1 + (direction INPUT) + ) + (port D2 + (direction INPUT) + ) + (port D3 + (direction INPUT) + ) + (port E + (direction INPUT) + ) + (port S0 + (direction INPUT) + ) + (port S1 + (direction INPUT) + ) + (port O + (direction OUTPUT) + ) + ) + (contents + (instance Mmux_O11 + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "DFD5DAD08F858A80") (owner "Xilinx")) + ) + (net D0 + (joined + (portRef D0) + (portRef I4 (instanceRef Mmux_O11)) + ) + ) + (net D1 + (joined + (portRef D1) + (portRef I3 (instanceRef Mmux_O11)) + ) + ) + (net D2 + (joined + (portRef D2) + (portRef I5 (instanceRef Mmux_O11)) + ) + ) + (net D3 + (joined + (portRef D3) + (portRef I1 (instanceRef Mmux_O11)) + ) + ) + (net S0 + (joined + (portRef S0) + (portRef I0 (instanceRef Mmux_O11)) + ) + ) + (net S1 + (joined + (portRef S1) + (portRef I2 (instanceRef Mmux_O11)) + ) + ) + (net O + (joined + (portRef O) + (portRef O (instanceRef Mmux_O11)) + ) + ) + ) + ) + ) + (cell (rename M4_1E_HXILINX_ALU_NO2_XLXI_5 "M4_1E_HXILINX_ALU") + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port D0 + (direction INPUT) + ) + (port D1 + (direction INPUT) + ) + (port D2 + (direction INPUT) + ) + (port D3 + (direction INPUT) + ) + (port E + (direction INPUT) + ) + (port S0 + (direction INPUT) + ) + (port S1 + (direction INPUT) + ) + (port O + (direction OUTPUT) + ) + ) + (contents + (instance Mmux_O11 + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "DFD5DAD08F858A80") (owner "Xilinx")) + ) + (net D0 + (joined + (portRef D0) + (portRef I4 (instanceRef Mmux_O11)) + ) + ) + (net D1 + (joined + (portRef D1) + (portRef I3 (instanceRef Mmux_O11)) + ) + ) + (net D2 + (joined + (portRef D2) + (portRef I5 (instanceRef Mmux_O11)) + ) + ) + (net D3 + (joined + (portRef D3) + (portRef I1 (instanceRef Mmux_O11)) + ) + ) + (net S0 + (joined + (portRef S0) + (portRef I0 (instanceRef Mmux_O11)) + ) + ) + (net S1 + (joined + (portRef S1) + (portRef I2 (instanceRef Mmux_O11)) + ) + ) + (net O + (joined + (portRef O) + (portRef O (instanceRef Mmux_O11)) + ) + ) + ) + ) + ) + (cell (rename M4_1E_HXILINX_ALU_NO1_XLXI_6 "M4_1E_HXILINX_ALU") + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port D0 + (direction INPUT) + ) + (port D1 + (direction INPUT) + ) + (port D2 + (direction INPUT) + ) + (port D3 + (direction INPUT) + ) + (port E + (direction INPUT) + ) + (port S0 + (direction INPUT) + ) + (port S1 + (direction INPUT) + ) + (port O + (direction OUTPUT) + ) + ) + (contents + (instance Mmux_O11 + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "DFD5DAD08F858A80") (owner "Xilinx")) + ) + (net D0 + (joined + (portRef D0) + (portRef I4 (instanceRef Mmux_O11)) + ) + ) + (net D1 + (joined + (portRef D1) + (portRef I3 (instanceRef Mmux_O11)) + ) + ) + (net D2 + (joined + (portRef D2) + (portRef I5 (instanceRef Mmux_O11)) + ) + ) + (net D3 + (joined + (portRef D3) + (portRef I1 (instanceRef Mmux_O11)) + ) + ) + (net S0 + (joined + (portRef S0) + (portRef I0 (instanceRef Mmux_O11)) + ) + ) + (net S1 + (joined + (portRef S1) + (portRef I2 (instanceRef Mmux_O11)) + ) + ) + (net O + (joined + (portRef O) + (portRef O (instanceRef Mmux_O11)) + ) + ) + ) + ) + ) + (cell (rename M4_1E_HXILINX_ALU_XLXI_7 "M4_1E_HXILINX_ALU") + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port D0 + (direction INPUT) + ) + (port D1 + (direction INPUT) + ) + (port D2 + (direction INPUT) + ) + (port D3 + (direction INPUT) + ) + (port E + (direction INPUT) + ) + (port S0 + (direction INPUT) + ) + (port S1 + (direction INPUT) + ) + (port O + (direction OUTPUT) + ) + ) + (contents + (instance Mmux_O11 + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "DFD5DAD08F858A80") (owner "Xilinx")) + ) + (net D0 + (joined + (portRef D0) + (portRef I4 (instanceRef Mmux_O11)) + ) + ) + (net D1 + (joined + (portRef D1) + (portRef I3 (instanceRef Mmux_O11)) + ) + ) + (net D2 + (joined + (portRef D2) + (portRef I5 (instanceRef Mmux_O11)) + ) + ) + (net D3 + (joined + (portRef D3) + (portRef I1 (instanceRef Mmux_O11)) + ) + ) + (net S0 + (joined + (portRef S0) + (portRef I0 (instanceRef Mmux_O11)) + ) + ) + (net S1 + (joined + (portRef S1) + (portRef I2 (instanceRef Mmux_O11)) + ) + ) + (net O + (joined + (portRef O) + (portRef O (instanceRef Mmux_O11)) + ) + ) + ) + ) + ) + (cell ALU + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port A + (direction INPUT) + ) + (port B + (direction INPUT) + ) + (port C + (direction INPUT) + ) + (port D + (direction INPUT) + ) + (port S0 + (direction INPUT) + ) + (port S1 + (direction INPUT) + ) + (port AN0 + (direction OUTPUT) + ) + (port AN1 + (direction OUTPUT) + ) + (port AN2 + (direction OUTPUT) + ) + (port AN3 + (direction OUTPUT) + ) + (port a_out + (direction OUTPUT) + ) + (port b_out + (direction OUTPUT) + ) + (port c_out + (direction OUTPUT) + ) + (port d_out + (direction OUTPUT) + ) + (port e_out + (direction OUTPUT) + ) + (port f_out + (direction OUTPUT) + ) + (port g_out + (direction OUTPUT) + ) + (port sign + (direction OUTPUT) + ) + (designator "xc6slx16-3-csg324") + (property TYPE (string "ALU") (owner "Xilinx")) + (property SHREG_MIN_SIZE (string "2") (owner "Xilinx")) + (property SHREG_EXTRACT_NGC (string "YES") (owner "Xilinx")) + (property NLW_UNIQUE_ID (integer 0) (owner "Xilinx")) + (property NLW_MACRO_TAG (integer 0) (owner "Xilinx")) + (property NLW_MACRO_ALIAS (string "ALU_ALU") (owner "Xilinx")) + ) + (contents + (instance XST_GND + (viewRef view_1 (cellRef GND (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance XLXI_8 + (viewRef view_1 (cellRef VCC (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_1_XLXI_8_XLXI_2 "XLXI_1/XLXI_8/XLXI_2") + (viewRef view_1 (cellRef OR3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_1_XLXI_8_XLXI_5 "XLXI_1/XLXI_8/XLXI_5") + (viewRef view_1 (cellRef OR2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_1_XLXI_8_XLXI_7 "XLXI_1/XLXI_8/XLXI_7") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_1_XLXI_8_XLXI_6 "XLXI_1/XLXI_8/XLXI_6") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_1_XLXI_8_XLXI_4 "XLXI_1/XLXI_8/XLXI_4") + (viewRef view_1 (cellRef AND2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_1_XLXI_8_XLXI_8 "XLXI_1/XLXI_8/XLXI_8") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_1_XLXI_8_XLXI_3 "XLXI_1/XLXI_8/XLXI_3") + (viewRef view_1 (cellRef AND2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_1_XLXI_8_XLXI_9 "XLXI_1/XLXI_8/XLXI_9") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_1_XLXI_8_XLXI_1 "XLXI_1/XLXI_8/XLXI_1") + (viewRef view_1 (cellRef AND4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_1_XLXI_9_XLXI_10 "XLXI_1/XLXI_9/XLXI_10") + (viewRef view_1 (cellRef AND2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_1_XLXI_9_XLXI_11 "XLXI_1/XLXI_9/XLXI_11") + (viewRef view_1 (cellRef NOR3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_1_XLXI_10_XLXI_2 "XLXI_1/XLXI_10/XLXI_2") + (viewRef view_1 (cellRef AND2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_1_XLXI_10_XLXI_3 "XLXI_1/XLXI_10/XLXI_3") + (viewRef view_1 (cellRef NOR3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_1_XLXI_12_XLXI_7 "XLXI_1/XLXI_12/XLXI_7") + (viewRef view_1 (cellRef OR3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_1_XLXI_12_XLXI_4 "XLXI_1/XLXI_12/XLXI_4") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_1_XLXI_12_XLXI_5 "XLXI_1/XLXI_12/XLXI_5") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_1_XLXI_12_XLXI_3 "XLXI_1/XLXI_12/XLXI_3") + (viewRef view_1 (cellRef AND2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_1_XLXI_12_XLXI_2 "XLXI_1/XLXI_12/XLXI_2") + (viewRef view_1 (cellRef AND2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_1_XLXI_12_XLXI_6 "XLXI_1/XLXI_12/XLXI_6") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_1_XLXI_12_XLXI_1 "XLXI_1/XLXI_12/XLXI_1") + (viewRef view_1 (cellRef AND3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_2_XLXI_2_XLXI_4 "XLXI_2/XLXI_2/XLXI_4") + (viewRef view_1 (cellRef OR3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_2_XLXI_2_XLXI_2 "XLXI_2/XLXI_2/XLXI_2") + (viewRef view_1 (cellRef AND3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_2_XLXI_2_XLXI_7 "XLXI_2/XLXI_2/XLXI_7") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_2_XLXI_2_XLXI_5 "XLXI_2/XLXI_2/XLXI_5") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_2_XLXI_2_XLXI_1 "XLXI_2/XLXI_2/XLXI_1") + (viewRef view_1 (cellRef AND3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_2_XLXI_2_XLXI_6 "XLXI_2/XLXI_2/XLXI_6") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_2_XLXI_2_XLXI_3 "XLXI_2/XLXI_2/XLXI_3") + (viewRef view_1 (cellRef AND3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_2_XLXI_1_XLXI_4 "XLXI_2/XLXI_1/XLXI_4") + (viewRef view_1 (cellRef OR3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_2_XLXI_1_XLXI_2 "XLXI_2/XLXI_1/XLXI_2") + (viewRef view_1 (cellRef AND3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_2_XLXI_1_XLXI_7 "XLXI_2/XLXI_1/XLXI_7") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_2_XLXI_1_XLXI_5 "XLXI_2/XLXI_1/XLXI_5") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_2_XLXI_1_XLXI_1 "XLXI_2/XLXI_1/XLXI_1") + (viewRef view_1 (cellRef AND3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_2_XLXI_1_XLXI_6 "XLXI_2/XLXI_1/XLXI_6") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_2_XLXI_1_XLXI_3 "XLXI_2/XLXI_1/XLXI_3") + (viewRef view_1 (cellRef AND3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_2_XLXI_3_XLXI_17 "XLXI_2/XLXI_3/XLXI_17") + (viewRef view_1 (cellRef OR3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_2_XLXI_3_XLXI_4 "XLXI_2/XLXI_3/XLXI_4") + (viewRef view_1 (cellRef OR3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_2_XLXI_3_XLXI_15 "XLXI_2/XLXI_3/XLXI_15") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_2_XLXI_3_XLXI_2 "XLXI_2/XLXI_3/XLXI_2") + (viewRef view_1 (cellRef AND3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_2_XLXI_3_XLXI_7 "XLXI_2/XLXI_3/XLXI_7") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_2_XLXI_3_XLXI_16 "XLXI_2/XLXI_3/XLXI_16") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_2_XLXI_3_XLXI_14 "XLXI_2/XLXI_3/XLXI_14") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_2_XLXI_3_XLXI_5 "XLXI_2/XLXI_3/XLXI_5") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_2_XLXI_3_XLXI_1 "XLXI_2/XLXI_3/XLXI_1") + (viewRef view_1 (cellRef AND3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_2_XLXI_3_XLXI_13 "XLXI_2/XLXI_3/XLXI_13") + (viewRef view_1 (cellRef NAND4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_2_XLXI_3_XLXI_11 "XLXI_2/XLXI_3/XLXI_11") + (viewRef view_1 (cellRef AND4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_2_XLXI_3_XLXI_6 "XLXI_2/XLXI_3/XLXI_6") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_2_XLXI_3_XLXI_3 "XLXI_2/XLXI_3/XLXI_3") + (viewRef view_1 (cellRef AND3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_2_XLXI_4_XLXI_4 "XLXI_2/XLXI_4/XLXI_4") + (viewRef view_1 (cellRef OR2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_2_XLXI_4_XLXI_2 "XLXI_2/XLXI_4/XLXI_2") + (viewRef view_1 (cellRef AND2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_2_XLXI_4_XLXI_3 "XLXI_2/XLXI_4/XLXI_3") + (viewRef view_1 (cellRef NAND3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_2_XLXI_4_XLXI_5 "XLXI_2/XLXI_4/XLXI_5") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_2_XLXI_4_XLXI_1 "XLXI_2/XLXI_4/XLXI_1") + (viewRef view_1 (cellRef XNOR2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_3_XLXI_8_XLXI_8 "XLXI_3/XLXI_8/XLXI_8") + (viewRef view_1 (cellRef AND3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_3_XLXI_8_XLXI_10 "XLXI_3/XLXI_8/XLXI_10") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_3_XLXI_8_XLXI_9 "XLXI_3/XLXI_8/XLXI_9") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_3_XLXI_8_XLXI_12 "XLXI_3/XLXI_8/XLXI_12") + (viewRef view_1 (cellRef OR2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_3_XLXI_9_XLXI_4 "XLXI_3/XLXI_9/XLXI_4") + (viewRef view_1 (cellRef OR3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_3_XLXI_9_XLXI_3 "XLXI_3/XLXI_9/XLXI_3") + (viewRef view_1 (cellRef AND3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_3_XLXI_9_XLXI_5 "XLXI_3/XLXI_9/XLXI_5") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_3_XLXI_9_XLXI_6 "XLXI_3/XLXI_9/XLXI_6") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_3_XLXI_9_XLXI_1 "XLXI_3/XLXI_9/XLXI_1") + (viewRef view_1 (cellRef AND2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_3_XLXI_9_XLXI_7 "XLXI_3/XLXI_9/XLXI_7") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_3_XLXI_9_XLXI_2 "XLXI_3/XLXI_9/XLXI_2") + (viewRef view_1 (cellRef AND2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_3_XLXI_10_XLXI_8 "XLXI_3/XLXI_10/XLXI_8") + (viewRef view_1 (cellRef OR4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_3_XLXI_10_XLXI_9 "XLXI_3/XLXI_10/XLXI_9") + (viewRef view_1 (cellRef AND2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_3_XLXI_10_XLXI_14 "XLXI_3/XLXI_10/XLXI_14") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_3_XLXI_10_XLXI_10 "XLXI_3/XLXI_10/XLXI_10") + (viewRef view_1 (cellRef AND2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_3_XLXI_10_XLXI_12 "XLXI_3/XLXI_10/XLXI_12") + (viewRef view_1 (cellRef NAND3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_3_XLXI_10_XLXI_11 "XLXI_3/XLXI_10/XLXI_11") + (viewRef view_1 (cellRef AND2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_3_XLXI_12_XLXI_9 "XLXI_3/XLXI_12/XLXI_9") + (viewRef view_1 (cellRef NAND2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_3_XLXI_12_XLXI_13 "XLXI_3/XLXI_12/XLXI_13") + (viewRef view_1 (cellRef NOR3 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance XLXI_7 + (viewRef view_1 (cellRef M4_1E_HXILINX_ALU_XLXI_7 (libraryRef ALU_lib))) + (property HU_SET (string "XLXI_7_3") (owner "Xilinx")) + (property NLW_UNIQUE_ID (integer 0) (owner "Xilinx")) + (property NLW_MACRO_TAG (integer 1) (owner "Xilinx")) + (property NLW_MACRO_ALIAS (string "M4_1E_HXILINX_ALU_XLXI_7") (owner "Xilinx")) + ) + (instance XLXI_6 + (viewRef view_1 (cellRef M4_1E_HXILINX_ALU_NO1_XLXI_6 (libraryRef ALU_lib))) + (property HU_SET (string "XLXI_6_2") (owner "Xilinx")) + (property NLW_UNIQUE_ID (integer 1) (owner "Xilinx")) + (property NLW_MACRO_TAG (integer 2) (owner "Xilinx")) + (property NLW_MACRO_ALIAS (string "M4_1E_HXILINX_ALU_NO1_XLXI_6") (owner "Xilinx")) + ) + (instance XLXI_5 + (viewRef view_1 (cellRef M4_1E_HXILINX_ALU_NO2_XLXI_5 (libraryRef ALU_lib))) + (property HU_SET (string "XLXI_5_1") (owner "Xilinx")) + (property NLW_UNIQUE_ID (integer 2) (owner "Xilinx")) + (property NLW_MACRO_TAG (integer 3) (owner "Xilinx")) + (property NLW_MACRO_ALIAS (string "M4_1E_HXILINX_ALU_NO2_XLXI_5") (owner "Xilinx")) + ) + (instance XLXI_4 + (viewRef view_1 (cellRef M4_1E_HXILINX_ALU_NO3_XLXI_4 (libraryRef ALU_lib))) + (property HU_SET (string "XLXI_4_0") (owner "Xilinx")) + (property NLW_UNIQUE_ID (integer 3) (owner "Xilinx")) + (property NLW_MACRO_TAG (integer 4) (owner "Xilinx")) + (property NLW_MACRO_ALIAS (string "M4_1E_HXILINX_ALU_NO3_XLXI_4") (owner "Xilinx")) + ) + (instance (rename XLXI_9_XLXI_8 "XLXI_9/XLXI_8") + (viewRef view_1 (cellRef BUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_9_XLXI_7 "XLXI_9/XLXI_7") + (viewRef view_1 (cellRef BUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_9_XLXI_6 "XLXI_9/XLXI_6") + (viewRef view_1 (cellRef BUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_9_XLXI_5 "XLXI_9/XLXI_5") + (viewRef view_1 (cellRef BUF (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_9_XLXI_68 "XLXI_9/XLXI_68") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_9_XLXI_69 "XLXI_9/XLXI_69") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_9_XLXI_71 "XLXI_9/XLXI_71") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_9_XLXI_70 "XLXI_9/XLXI_70") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_9_XLXI_66 "XLXI_9/XLXI_66") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_9_XLXI_73 "XLXI_9/XLXI_73") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_9_XLXI_65 "XLXI_9/XLXI_65") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_9_XLXI_67 "XLXI_9/XLXI_67") + (viewRef view_1 (cellRef INV (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_9_XLXI_53 "XLXI_9/XLXI_53") + (viewRef view_1 (cellRef OR2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_9_XLXI_57 "XLXI_9/XLXI_57") + (viewRef view_1 (cellRef AND2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_9_XLXI_43 "XLXI_9/XLXI_43") + (viewRef view_1 (cellRef AND2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_9_XLXI_52 "XLXI_9/XLXI_52") + (viewRef view_1 (cellRef OR4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_9_XLXI_49 "XLXI_9/XLXI_49") + (viewRef view_1 (cellRef AND2 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename XLXI_9_XLXI_44 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XLXI_1_XLXI_8_XLXI_2)) + (portRef I0 (instanceRef XLXI_1_XLXI_8_XLXI_4)) + ) + ) + (net (rename XLXI_1_XLXI_8_XLXN_13 "XLXI_1/XLXI_8/XLXN_13") + (joined + (portRef I2 (instanceRef XLXI_1_XLXI_8_XLXI_2)) + (portRef O (instanceRef XLXI_1_XLXI_8_XLXI_7)) + ) + ) + (net (rename XLXI_1_XLXI_8_XLXN_8 "XLXI_1/XLXI_8/XLXN_8") + (joined + (portRef O (instanceRef XLXI_1_XLXI_8_XLXI_6)) + (portRef I2 (instanceRef XLXI_1_XLXI_8_XLXI_1)) + ) + ) + (net (rename XLXI_1_XLXI_8_XLXN_4 "XLXI_1/XLXI_8/XLXN_4") + (joined + (portRef I1 (instanceRef XLXI_1_XLXI_8_XLXI_5)) + (portRef O (instanceRef XLXI_1_XLXI_8_XLXI_4)) + ) + ) + (net (rename XLXI_1_XLXI_8_XLXN_16 "XLXI_1/XLXI_8/XLXN_16") + (joined + (portRef I0 (instanceRef XLXI_1_XLXI_8_XLXI_2)) + (portRef O (instanceRef XLXI_1_XLXI_8_XLXI_8)) + ) + ) + (net (rename XLXI_1_XLXI_8_XLXN_1 "XLXI_1/XLXI_8/XLXN_1") + (joined + (portRef I1 (instanceRef XLXI_1_XLXI_8_XLXI_2)) + (portRef O (instanceRef XLXI_1_XLXI_8_XLXI_3)) + ) + ) + (net (rename XLXI_1_XLXI_8_XLXN_17 "XLXI_1/XLXI_8/XLXN_17") + (joined + (portRef I0 (instanceRef XLXI_1_XLXI_8_XLXI_3)) + (portRef O (instanceRef XLXI_1_XLXI_8_XLXI_9)) + ) + ) + (net (rename XLXI_1_XLXI_8_XLXN_5 "XLXI_1/XLXI_8/XLXN_5") + (joined + (portRef I0 (instanceRef XLXI_1_XLXI_8_XLXI_5)) + (portRef O (instanceRef XLXI_1_XLXI_8_XLXI_1)) + ) + ) + (net (rename XLXI_1_XLXI_9_XLXN_9 "XLXI_1/XLXI_9/XLXN_9") + (joined + (portRef I0 (instanceRef XLXI_1_XLXI_9_XLXI_10)) + (portRef O (instanceRef XLXI_1_XLXI_9_XLXI_11)) + ) + ) + (net (rename XLXI_1_XLXI_10_XLXN_2 "XLXI_1/XLXI_10/XLXN_2") + (joined + (portRef I0 (instanceRef XLXI_1_XLXI_10_XLXI_2)) + (portRef O (instanceRef XLXI_1_XLXI_10_XLXI_3)) + ) + ) + (net (rename XLXI_1_XLXI_12_XLXN_1 "XLXI_1/XLXI_12/XLXN_1") + (joined + (portRef O (instanceRef XLXI_1_XLXI_12_XLXI_4)) + (portRef I1 (instanceRef XLXI_1_XLXI_12_XLXI_2)) + ) + ) + (net (rename XLXI_1_XLXI_12_XLXN_2 "XLXI_1/XLXI_12/XLXN_2") + (joined + (portRef O (instanceRef XLXI_1_XLXI_12_XLXI_5)) + (portRef I2 (instanceRef XLXI_1_XLXI_12_XLXI_1)) + ) + ) + (net (rename XLXI_1_XLXI_12_XLXN_6 "XLXI_1/XLXI_12/XLXN_6") + (joined + (portRef I0 (instanceRef XLXI_1_XLXI_12_XLXI_7)) + (portRef O (instanceRef XLXI_1_XLXI_12_XLXI_3)) + ) + ) + (net (rename XLXI_1_XLXI_12_XLXN_4 "XLXI_1/XLXI_12/XLXN_4") + (joined + (portRef I2 (instanceRef XLXI_1_XLXI_12_XLXI_7)) + (portRef O (instanceRef XLXI_1_XLXI_12_XLXI_2)) + ) + ) + (net (rename XLXI_1_XLXI_12_XLXN_3 "XLXI_1/XLXI_12/XLXN_3") + (joined + (portRef I1 (instanceRef XLXI_1_XLXI_12_XLXI_3)) + (portRef O (instanceRef XLXI_1_XLXI_12_XLXI_6)) + ) + ) + (net (rename XLXI_1_XLXI_12_XLXN_5 "XLXI_1/XLXI_12/XLXN_5") + (joined + (portRef I1 (instanceRef XLXI_1_XLXI_12_XLXI_7)) + (portRef O (instanceRef XLXI_1_XLXI_12_XLXI_1)) + ) + ) + (net (rename XLXI_2_XLXI_2_XLXN_2 "XLXI_2/XLXI_2/XLXN_2") + (joined + (portRef I1 (instanceRef XLXI_2_XLXI_2_XLXI_4)) + (portRef O (instanceRef XLXI_2_XLXI_2_XLXI_2)) + ) + ) + (net (rename XLXI_2_XLXI_2_XLXN_7 "XLXI_2/XLXI_2/XLXN_7") + (joined + (portRef O (instanceRef XLXI_2_XLXI_2_XLXI_7)) + (portRef I1 (instanceRef XLXI_2_XLXI_2_XLXI_3)) + ) + ) + (net (rename XLXI_2_XLXI_2_XLXN_5 "XLXI_2/XLXI_2/XLXN_5") + (joined + (portRef I1 (instanceRef XLXI_2_XLXI_2_XLXI_2)) + (portRef O (instanceRef XLXI_2_XLXI_2_XLXI_5)) + ) + ) + (net (rename XLXI_2_XLXI_2_XLXN_1 "XLXI_2/XLXI_2/XLXN_1") + (joined + (portRef I2 (instanceRef XLXI_2_XLXI_2_XLXI_4)) + (portRef O (instanceRef XLXI_2_XLXI_2_XLXI_1)) + ) + ) + (net (rename XLXI_2_XLXI_2_XLXN_6 "XLXI_2/XLXI_2/XLXN_6") + (joined + (portRef I0 (instanceRef XLXI_2_XLXI_2_XLXI_2)) + (portRef O (instanceRef XLXI_2_XLXI_2_XLXI_6)) + ) + ) + (net (rename XLXI_2_XLXI_2_XLXN_3 "XLXI_2/XLXI_2/XLXN_3") + (joined + (portRef I0 (instanceRef XLXI_2_XLXI_2_XLXI_4)) + (portRef O (instanceRef XLXI_2_XLXI_2_XLXI_3)) + ) + ) + (net (rename XLXI_2_XLXI_1_XLXN_2 "XLXI_2/XLXI_1/XLXN_2") + (joined + (portRef I1 (instanceRef XLXI_2_XLXI_1_XLXI_4)) + (portRef O (instanceRef XLXI_2_XLXI_1_XLXI_2)) + ) + ) + (net (rename XLXI_2_XLXI_1_XLXN_7 "XLXI_2/XLXI_1/XLXN_7") + (joined + (portRef O (instanceRef XLXI_2_XLXI_1_XLXI_7)) + (portRef I1 (instanceRef XLXI_2_XLXI_1_XLXI_3)) + ) + ) + (net (rename XLXI_2_XLXI_1_XLXN_5 "XLXI_2/XLXI_1/XLXN_5") + (joined + (portRef I1 (instanceRef XLXI_2_XLXI_1_XLXI_2)) + (portRef O (instanceRef XLXI_2_XLXI_1_XLXI_5)) + ) + ) + (net (rename XLXI_2_XLXI_1_XLXN_1 "XLXI_2/XLXI_1/XLXN_1") + (joined + (portRef I2 (instanceRef XLXI_2_XLXI_1_XLXI_4)) + (portRef O (instanceRef XLXI_2_XLXI_1_XLXI_1)) + ) + ) + (net (rename XLXI_2_XLXI_1_XLXN_6 "XLXI_2/XLXI_1/XLXN_6") + (joined + (portRef I0 (instanceRef XLXI_2_XLXI_1_XLXI_2)) + (portRef O (instanceRef XLXI_2_XLXI_1_XLXI_6)) + ) + ) + (net (rename XLXI_2_XLXI_1_XLXN_3 "XLXI_2/XLXI_1/XLXN_3") + (joined + (portRef I0 (instanceRef XLXI_2_XLXI_1_XLXI_4)) + (portRef O (instanceRef XLXI_2_XLXI_1_XLXI_3)) + ) + ) + (net (rename XLXI_2_XLXI_3_XLXN_21 "XLXI_2/XLXI_3/XLXN_21") + (joined + (portRef I2 (instanceRef XLXI_2_XLXI_3_XLXI_17)) + (portRef O (instanceRef XLXI_2_XLXI_3_XLXI_4)) + ) + ) + (net (rename XLXI_2_XLXI_3_XLXN_23 "XLXI_2/XLXI_3/XLXN_23") + (joined + (portRef O (instanceRef XLXI_2_XLXI_3_XLXI_15)) + (portRef I3 (instanceRef XLXI_2_XLXI_3_XLXI_11)) + ) + ) + (net (rename XLXI_2_XLXI_3_XLXN_2 "XLXI_2/XLXI_3/XLXN_2") + (joined + (portRef I1 (instanceRef XLXI_2_XLXI_3_XLXI_4)) + (portRef O (instanceRef XLXI_2_XLXI_3_XLXI_2)) + ) + ) + (net (rename XLXI_2_XLXI_3_XLXN_7 "XLXI_2/XLXI_3/XLXN_7") + (joined + (portRef O (instanceRef XLXI_2_XLXI_3_XLXI_7)) + (portRef I1 (instanceRef XLXI_2_XLXI_3_XLXI_3)) + ) + ) + (net (rename XLXI_2_XLXI_3_XLXN_24 "XLXI_2/XLXI_3/XLXN_24") + (joined + (portRef O (instanceRef XLXI_2_XLXI_3_XLXI_16)) + (portRef I1 (instanceRef XLXI_2_XLXI_3_XLXI_11)) + ) + ) + (net (rename XLXI_2_XLXI_3_XLXN_22 "XLXI_2/XLXI_3/XLXN_22") + (joined + (portRef O (instanceRef XLXI_2_XLXI_3_XLXI_14)) + (portRef I1 (instanceRef XLXI_2_XLXI_3_XLXI_13)) + ) + ) + (net (rename XLXI_2_XLXI_3_XLXN_5 "XLXI_2/XLXI_3/XLXN_5") + (joined + (portRef I1 (instanceRef XLXI_2_XLXI_3_XLXI_2)) + (portRef O (instanceRef XLXI_2_XLXI_3_XLXI_5)) + ) + ) + (net (rename XLXI_2_XLXI_3_XLXN_1 "XLXI_2/XLXI_3/XLXN_1") + (joined + (portRef I2 (instanceRef XLXI_2_XLXI_3_XLXI_4)) + (portRef O (instanceRef XLXI_2_XLXI_3_XLXI_1)) + ) + ) + (net (rename XLXI_2_XLXI_3_XLXN_31 "XLXI_2/XLXI_3/XLXN_31") + (joined + (portRef I1 (instanceRef XLXI_2_XLXI_3_XLXI_17)) + (portRef O (instanceRef XLXI_2_XLXI_3_XLXI_13)) + ) + ) + (net (rename XLXI_2_XLXI_3_XLXN_46 "XLXI_2/XLXI_3/XLXN_46") + (joined + (portRef I0 (instanceRef XLXI_2_XLXI_3_XLXI_17)) + (portRef O (instanceRef XLXI_2_XLXI_3_XLXI_11)) + ) + ) + (net (rename XLXI_2_XLXI_3_XLXN_6 "XLXI_2/XLXI_3/XLXN_6") + (joined + (portRef I0 (instanceRef XLXI_2_XLXI_3_XLXI_2)) + (portRef O (instanceRef XLXI_2_XLXI_3_XLXI_6)) + ) + ) + (net (rename XLXI_2_XLXI_3_XLXN_3 "XLXI_2/XLXI_3/XLXN_3") + (joined + (portRef I0 (instanceRef XLXI_2_XLXI_3_XLXI_4)) + (portRef O (instanceRef XLXI_2_XLXI_3_XLXI_3)) + ) + ) + (net (rename XLXI_2_XLXI_4_XLXN_4 "XLXI_2/XLXI_4/XLXN_4") + (joined + (portRef I0 (instanceRef XLXI_2_XLXI_4_XLXI_4)) + (portRef O (instanceRef XLXI_2_XLXI_4_XLXI_2)) + ) + ) + (net (rename XLXI_2_XLXI_4_XLXN_3 "XLXI_2/XLXI_4/XLXN_3") + (joined + (portRef I1 (instanceRef XLXI_2_XLXI_4_XLXI_4)) + (portRef O (instanceRef XLXI_2_XLXI_4_XLXI_3)) + ) + ) + (net (rename XLXI_2_XLXI_4_XLXN_5 "XLXI_2/XLXI_4/XLXN_5") + (joined + (portRef I0 (instanceRef XLXI_2_XLXI_4_XLXI_3)) + (portRef O (instanceRef XLXI_2_XLXI_4_XLXI_5)) + ) + ) + (net (rename XLXI_2_XLXI_4_XLXN_1 "XLXI_2/XLXI_4/XLXN_1") + (joined + (portRef I0 (instanceRef XLXI_2_XLXI_4_XLXI_2)) + (portRef O (instanceRef XLXI_2_XLXI_4_XLXI_1)) + ) + ) + (net (rename XLXI_3_XLXI_8_XLXN_17 "XLXI_3/XLXI_8/XLXN_17") + (joined + (portRef O (instanceRef XLXI_3_XLXI_8_XLXI_8)) + (portRef I0 (instanceRef XLXI_3_XLXI_8_XLXI_12)) + ) + ) + (net (rename XLXI_3_XLXI_8_XLXN_15 "XLXI_3/XLXI_8/XLXN_15") + (joined + (portRef I1 (instanceRef XLXI_3_XLXI_8_XLXI_8)) + (portRef O (instanceRef XLXI_3_XLXI_8_XLXI_10)) + ) + ) + (net (rename XLXI_3_XLXI_8_XLXN_14 "XLXI_3/XLXI_8/XLXN_14") + (joined + (portRef I2 (instanceRef XLXI_3_XLXI_8_XLXI_8)) + (portRef O (instanceRef XLXI_3_XLXI_8_XLXI_9)) + ) + ) + (net (rename XLXI_3_XLXI_9_XLXN_3 "XLXI_3/XLXI_9/XLXN_3") + (joined + (portRef I0 (instanceRef XLXI_3_XLXI_9_XLXI_4)) + (portRef O (instanceRef XLXI_3_XLXI_9_XLXI_3)) + ) + ) + (net (rename XLXI_3_XLXI_9_XLXN_4 "XLXI_3/XLXI_9/XLXN_4") + (joined + (portRef I0 (instanceRef XLXI_3_XLXI_9_XLXI_3)) + (portRef O (instanceRef XLXI_3_XLXI_9_XLXI_5)) + ) + ) + (net (rename XLXI_3_XLXI_9_XLXN_5 "XLXI_3/XLXI_9/XLXN_5") + (joined + (portRef I1 (instanceRef XLXI_3_XLXI_9_XLXI_3)) + (portRef O (instanceRef XLXI_3_XLXI_9_XLXI_6)) + (portRef I0 (instanceRef XLXI_3_XLXI_9_XLXI_2)) + ) + ) + (net (rename XLXI_3_XLXI_9_XLXN_2 "XLXI_3/XLXI_9/XLXN_2") + (joined + (portRef I2 (instanceRef XLXI_3_XLXI_9_XLXI_4)) + (portRef O (instanceRef XLXI_3_XLXI_9_XLXI_1)) + ) + ) + (net (rename XLXI_3_XLXI_9_XLXN_6 "XLXI_3/XLXI_9/XLXN_6") + (joined + (portRef I1 (instanceRef XLXI_3_XLXI_9_XLXI_1)) + (portRef O (instanceRef XLXI_3_XLXI_9_XLXI_7)) + ) + ) + (net (rename XLXI_3_XLXI_9_XLXN_1 "XLXI_3/XLXI_9/XLXN_1") + (joined + (portRef I1 (instanceRef XLXI_3_XLXI_9_XLXI_4)) + (portRef O (instanceRef XLXI_3_XLXI_9_XLXI_2)) + ) + ) + (net (rename XLXI_3_XLXI_10_XLXN_35 "XLXI_3/XLXI_10/XLXN_35") + (joined + (portRef I3 (instanceRef XLXI_3_XLXI_10_XLXI_8)) + (portRef O (instanceRef XLXI_3_XLXI_10_XLXI_9)) + ) + ) + (net (rename XLXI_3_XLXI_10_XLXN_44 "XLXI_3/XLXI_10/XLXN_44") + (joined + (portRef I0 (instanceRef XLXI_3_XLXI_10_XLXI_9)) + (portRef O (instanceRef XLXI_3_XLXI_10_XLXI_14)) + (portRef I1 (instanceRef XLXI_3_XLXI_10_XLXI_10)) + (portRef I2 (instanceRef XLXI_3_XLXI_10_XLXI_12)) + (portRef I1 (instanceRef XLXI_3_XLXI_10_XLXI_11)) + ) + ) + (net (rename XLXI_3_XLXI_10_XLXN_41 "XLXI_3/XLXI_10/XLXN_41") + (joined + (portRef I1 (instanceRef XLXI_3_XLXI_10_XLXI_8)) + (portRef O (instanceRef XLXI_3_XLXI_10_XLXI_10)) + ) + ) + (net (rename XLXI_3_XLXI_10_XLXN_37 "XLXI_3/XLXI_10/XLXN_37") + (joined + (portRef I0 (instanceRef XLXI_3_XLXI_10_XLXI_8)) + (portRef O (instanceRef XLXI_3_XLXI_10_XLXI_12)) + ) + ) + (net (rename XLXI_3_XLXI_10_XLXN_40 "XLXI_3/XLXI_10/XLXN_40") + (joined + (portRef I2 (instanceRef XLXI_3_XLXI_10_XLXI_8)) + (portRef O (instanceRef XLXI_3_XLXI_10_XLXI_11)) + ) + ) + (net (rename XLXI_3_XLXI_12_XLXN_8 "XLXI_3/XLXI_12/XLXN_8") + (joined + (portRef I0 (instanceRef XLXI_3_XLXI_12_XLXI_9)) + (portRef O (instanceRef XLXI_3_XLXI_12_XLXI_13)) + ) + ) + (net (rename XLXI_9_XLXN_158 "XLXI_9/XLXN_158") + (joined + (portRef O (instanceRef XLXI_9_XLXI_53)) + (portRef I (instanceRef XLXI_9_XLXI_68)) + ) + ) + (net (rename XLXI_9_XLXN_131 "XLXI_9/XLXN_131") + (joined + (portRef I0 (instanceRef XLXI_9_XLXI_58)) + (portRef O (instanceRef XLXI_9_XLXI_57)) + ) + ) + (net (rename XLXI_9_XLXN_92 "XLXI_9/XLXN_92") + (joined + (portRef I2 (instanceRef XLXI_9_XLXI_41)) + (portRef O (instanceRef XLXI_9_XLXI_43)) + ) + ) + (net (rename XLXI_9_XLXN_156 "XLXI_9/XLXN_156") + (joined + (portRef O (instanceRef XLXI_9_XLXI_52)) + (portRef I (instanceRef XLXI_9_XLXI_69)) + ) + ) + (net (rename XLXI_9_XLXN_126 "XLXI_9/XLXN_126") + (joined + (portRef O (instanceRef XLXI_9_XLXI_49)) + (portRef I2 (instanceRef XLXI_9_XLXI_52)) + (portRef I0 (instanceRef XLXI_9_XLXI_53)) + ) + ) + (net (rename XLXI_9_XLXN_93 "XLXI_9/XLXN_93") + (joined + (portRef I1 (instanceRef XLXI_9_XLXI_41)) + (portRef O (instanceRef XLXI_9_XLXI_44)) + ) + ) + (net (rename XLXI_9_XLXN_63 "XLXI_9/XLXN_63") + (joined + (portRef I2 (instanceRef XLXI_9_XLXI_34)) + (portRef O (instanceRef XLXI_9_XLXI_32)) + ) + ) + (net (rename XLXI_9_XLXN_162 "XLXI_9/XLXN_162") + (joined + (portRef O (instanceRef XLXI_9_XLXI_60)) + (portRef I (instanceRef XLXI_9_XLXI_71)) + ) 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+) + diff --git a/planAhead_run_1/lab1.data/constrs_1/designprops.xml b/planAhead_run_1/lab1.data/constrs_1/designprops.xml new file mode 100755 index 0000000..ae00c39 --- /dev/null +++ b/planAhead_run_1/lab1.data/constrs_1/designprops.xml @@ -0,0 +1,29 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/planAhead_run_1/lab1.data/constrs_1/fileset.xml b/planAhead_run_1/lab1.data/constrs_1/fileset.xml index 80984cf..6fa147b 100755 --- a/planAhead_run_1/lab1.data/constrs_1/fileset.xml +++ b/planAhead_run_1/lab1.data/constrs_1/fileset.xml @@ -15,6 +15,26 @@ Val="1"/> + + + + + + + + + + + + + +