From 70b77304f37d9681aa3bfa0eb57df0bcfd1aef81 Mon Sep 17 00:00:00 2001 From: Michael Abed Date: Fri, 17 Feb 2012 12:08:05 -0500 Subject: make it work --- ALU.vf | 258 ++++++++++++++++++++++++++++++++++++----------------------------- 1 file changed, 144 insertions(+), 114 deletions(-) (limited to 'ALU.vf') diff --git a/ALU.vf b/ALU.vf index a99f305..d4c14ec 100755 --- a/ALU.vf +++ b/ALU.vf @@ -7,11 +7,11 @@ // \ \ \/ Version : 13.3 // \ \ Application : sch2hdl // / / Filename : ALU.vf -// /___/ /\ Timestamp : 02/15/2012 15:00:05 +// /___/ /\ Timestamp : 02/16/2012 19:52:33 // \ \ / \ // \___\/\___\ // -//Command: sch2hdl -intstyle ise -family spartan6 -verilog "X:/My Documents/ec311/lab1/ALU.vf" -w "X:/My Documents/ec311/lab1/ALU.sch" +//Command: sch2hdl -intstyle ise -family spartan6 -verilog "X:/My Documents/ec311/ec311-lab1/ALU.vf" -w "X:/My Documents/ec311/ec311-lab1/ALU.sch" //Design Name: ALU //Device: spartan6 //Purpose: @@ -282,17 +282,17 @@ module Negate_3_MUSER_ALU(b0, output result; wire XLXN_8; - wire XLXN_9; + wire XLXN_10; - OR3 XLXI_5 (.I0(b2), - .I1(b1), - .I2(b0), - .O(XLXN_9)); - NAND2 XLXI_9 (.I0(XLXN_8), - .I1(b3), - .O(result)); - INV XLXI_12 (.I(XLXN_9), + OR3 XLXI_14 (.I0(b2), + .I1(b1), + .I2(b0), .O(XLXN_8)); + INV XLXI_15 (.I(b3), + .O(XLXN_10)); + AND2 XLXI_16 (.I0(XLXN_8), + .I1(XLXN_10), + .O(result)); endmodule `timescale 1ns / 1ps @@ -350,33 +350,38 @@ module Negate_2_MUSER_ALU(b0, input b3; output result; - wire XLXN_7; - wire XLXN_9; - wire XLXN_10; - wire XLXN_12; - wire XLXN_16; - wire XLXN_17; - - AND2 XLXI_1 (.I0(XLXN_7), - .I1(b3), - .O(XLXN_9)); - AND3 XLXI_2 (.I0(b2), - .I1(XLXN_16), - .I2(XLXN_17), - .O(XLXN_10)); - OR2 XLXI_3 (.I0(XLXN_10), - .I1(XLXN_9), + wire XLXN_35; + wire XLXN_37; + wire XLXN_40; + wire XLXN_41; + wire XLXN_44; + wire XLXN_47; + wire XLXN_49; + + OR4 XLXI_8 (.I0(XLXN_37), + .I1(XLXN_41), + .I2(XLXN_40), + .I3(XLXN_35), .O(result)); - OR3 XLXI_4 (.I0(XLXN_12), - .I1(b1), - .I2(b0), - .O(XLXN_7)); - INV XLXI_5 (.I(b2), - .O(XLXN_12)); - INV XLXI_6 (.I(b1), - .O(XLXN_16)); - INV XLXI_7 (.I(b0), - .O(XLXN_17)); + AND2 XLXI_9 (.I0(XLXN_44), + .I1(b3), + .O(XLXN_35)); + AND2 XLXI_10 (.I0(b1), + .I1(XLXN_44), + .O(XLXN_41)); + AND2 XLXI_11 (.I0(b0), + .I1(XLXN_44), + .O(XLXN_40)); + INV XLXI_14 (.I(b2), + .O(XLXN_44)); + AND3 XLXI_15 (.I0(XLXN_47), + .I1(XLXN_49), + .I2(b2), + .O(XLXN_37)); + INV XLXI_16 (.I(b1), + .O(XLXN_49)); + INV XLXI_17 (.I(b0), + .O(XLXN_47)); endmodule `timescale 1ns / 1ps @@ -467,23 +472,40 @@ module Modulo_0_MUSER_ALU(b0, wire XLXN_1; wire XLXN_3; wire XLXN_4; - wire XLXN_5; + wire XLXN_12; + wire XLXN_14; + wire XLXN_15; + wire XLXN_16; + wire XLXN_27; + wire XLXN_28; - XNOR2 XLXI_1 (.I0(b0), - .I1(b1), - .O(XLXN_1)); AND2 XLXI_2 (.I0(XLXN_1), .I1(b2), .O(XLXN_4)); - NAND3 XLXI_3 (.I0(XLXN_5), - .I1(b1), - .I2(b2), - .O(XLXN_3)); OR2 XLXI_4 (.I0(XLXN_4), .I1(XLXN_3), .O(result)); - INV XLXI_5 (.I(b0), - .O(XLXN_5)); + INV XLXI_9 (.I(b1), + .O(XLXN_15)); + INV XLXI_10 (.I(b0), + .O(XLXN_16)); + AND3 XLXI_11 (.I0(b0), + .I1(XLXN_28), + .I2(XLXN_27), + .O(XLXN_3)); + INV XLXI_12 (.I(b2), + .O(XLXN_27)); + INV XLXI_13 (.I(b1), + .O(XLXN_28)); + OR2 XLXI_14 (.I0(XLXN_14), + .I1(XLXN_12), + .O(XLXN_1)); + AND2 XLXI_15 (.I0(b0), + .I1(b1), + .O(XLXN_12)); + AND2 XLXI_16 (.I0(XLXN_16), + .I1(XLXN_15), + .O(XLXN_14)); endmodule `timescale 1ns / 1ps @@ -499,24 +521,24 @@ module Modulo_1_MUSER_ALU(b0, input b3; output result; - wire XLXN_1; wire XLXN_2; wire XLXN_3; wire XLXN_5; wire XLXN_6; wire XLXN_7; - wire XLXN_18; - wire XLXN_19; - wire XLXN_20; - wire XLXN_21; - wire XLXN_22; wire XLXN_23; wire XLXN_24; + wire XLXN_50; + wire XLXN_51; + wire XLXN_54; + wire XLXN_55; + wire XLXN_56; + wire XLXN_57; AND3 XLXI_1 (.I0(b1), .I1(b2), .I2(b3), - .O(XLXN_1)); + .O(XLXN_55)); AND3 XLXI_2 (.I0(XLXN_6), .I1(XLXN_5), .I2(b3), @@ -525,38 +547,38 @@ module Modulo_1_MUSER_ALU(b0, .I1(XLXN_7), .I2(b3), .O(XLXN_3)); - OR3 XLXI_4 (.I0(XLXN_3), - .I1(XLXN_2), - .I2(XLXN_1), - .O(XLXN_21)); INV XLXI_5 (.I(b1), .O(XLXN_5)); INV XLXI_6 (.I(b0), .O(XLXN_6)); INV XLXI_7 (.I(b2), .O(XLXN_7)); - OR2 XLXI_9 (.I0(XLXN_20), - .I1(XLXN_21), - .O(result)); AND4 XLXI_11 (.I0(b0), .I1(XLXN_24), .I2(b2), .I3(XLXN_23), - .O(XLXN_19)); - OR2 XLXI_12 (.I0(XLXN_19), - .I1(XLXN_18), - .O(XLXN_20)); - NAND4 XLXI_13 (.I0(b0), - .I1(XLXN_22), - .I2(b2), - .I3(b3), - .O(XLXN_18)); - INV XLXI_14 (.I(b1), - .O(XLXN_22)); + .O(XLXN_57)); INV XLXI_15 (.I(b3), .O(XLXN_23)); INV XLXI_16 (.I(b1), .O(XLXN_24)); + AND4 XLXI_18 (.I0(XLXN_54), + .I1(b1), + .I2(XLXN_50), + .I3(XLXN_51), + .O(XLXN_56)); + INV XLXI_19 (.I(b2), + .O(XLXN_50)); + INV XLXI_20 (.I(b3), + .O(XLXN_51)); + INV XLXI_21 (.I(b0), + .O(XLXN_54)); + OR5 XLXI_22 (.I0(XLXN_57), + .I1(XLXN_56), + .I2(XLXN_3), + .I3(XLXN_2), + .I4(XLXN_55), + .O(result)); endmodule `timescale 1ns / 1ps @@ -708,25 +730,24 @@ module Divide_2_MUSER_ALU(b0, input b3; output result; - wire XLXN_1; - wire XLXN_2; - wire XLXN_3; - wire XLXN_7; + wire XLXN_9; + wire XLXN_13; + wire XLXN_14; + wire XLXN_15; - OR3 XLXI_1 (.I0(XLXN_1), - .I1(XLXN_7), - .I2(XLXN_3), - .O(result)); - AND3 XLXI_2 (.I0(XLXN_2), - .I1(b3), - .I2(b1), - .O(XLXN_1)); - INV XLXI_3 (.I(b2), - .O(XLXN_2)); - INV XLXI_4 (.I(b0), - .O(XLXN_3)); - INV XLXI_9 (.I(b1), - .O(XLXN_7)); + AND2 XLXI_10 (.I0(XLXN_9), + .I1(b3), + .O(result)); + OR3 XLXI_12 (.I0(XLXN_15), + .I1(XLXN_14), + .I2(XLXN_13), + .O(XLXN_9)); + INV XLXI_13 (.I(b0), + .O(XLXN_13)); + INV XLXI_15 (.I(b1), + .O(XLXN_14)); + INV XLXI_16 (.I(b2), + .O(XLXN_15)); endmodule `timescale 1ns / 1ps @@ -743,14 +764,23 @@ module Divide_3_MUSER_ALU(b0, output result; wire XLXN_2; + wire XLXN_13; + wire XLXN_14; + wire XLXN_15; AND2 XLXI_2 (.I0(XLXN_2), .I1(b3), .O(result)); - NOR3 XLXI_3 (.I0(b0), - .I1(b1), - .I2(b2), - .O(XLXN_2)); + OR3 XLXI_4 (.I0(XLXN_15), + .I1(XLXN_14), + .I2(XLXN_13), + .O(XLXN_2)); + INV XLXI_6 (.I(b2), + .O(XLXN_13)); + INV XLXI_7 (.I(b1), + .O(XLXN_14)); + INV XLXI_8 (.I(b0), + .O(XLXN_15)); endmodule `timescale 1ns / 1ps @@ -766,25 +796,23 @@ module Divide_0_MUSER_ALU(b0, input b3; output result; - wire XLXN_1; wire XLXN_2; wire XLXN_3; wire XLXN_4; wire XLXN_5; wire XLXN_6; + wire XLXN_12; - AND3 XLXI_1 (.I0(b3), + AND3 XLXI_1 (.I0(b0), .I1(b3), .I2(XLXN_2), .O(XLXN_5)); AND2 XLXI_2 (.I0(b1), - .I1(XLXN_1), + .I1(XLXN_12), .O(XLXN_4)); AND2 XLXI_3 (.I0(b1), .I1(XLXN_3), .O(XLXN_6)); - INV XLXI_4 (.I(b3), - .O(XLXN_1)); INV XLXI_5 (.I(b1), .O(XLXN_2)); INV XLXI_6 (.I(b0), @@ -793,6 +821,8 @@ module Divide_0_MUSER_ALU(b0, .I1(XLXN_5), .I2(XLXN_4), .O(result)); + INV XLXI_9 (.I(b3), + .O(XLXN_12)); endmodule `timescale 1ns / 1ps @@ -830,10 +860,10 @@ module Divide_MUSER_ALU(b0, .b2(b2), .b3(b3), .result(out3)); - Divide_0_MUSER_ALU XLXI_12 (.b0(b1), - .b1(b2), + Divide_0_MUSER_ALU XLXI_12 (.b0(b0), + .b1(b1), .b2(b2), - .b3(b0), + .b3(b3), .result(out0)); endmodule `timescale 1ns / 1ps @@ -881,10 +911,6 @@ module ALU(A, wire XLXN_23; wire XLXN_24; wire XLXN_25; - wire XLXN_26; - wire XLXN_27; - wire XLXN_28; - wire XLXN_31; wire XLXN_33; wire XLXN_34; wire XLXN_35; @@ -893,6 +919,10 @@ module ALU(A, wire XLXN_38; wire XLXN_39; wire XLXN_41; + wire XLXN_42; + wire XLXN_43; + wire XLXN_44; + wire XLXN_45; Divide_MUSER_ALU XLXI_1 (.b0(D), .b1(C), @@ -914,13 +944,13 @@ module ALU(A, .b1(C), .b2(B), .b3(A), - .out0(XLXN_27), - .out1(XLXN_28), - .out2(XLXN_31), - .out3(XLXN_26)); + .out0(XLXN_42), + .out1(XLXN_43), + .out2(XLXN_44), + .out3(XLXN_45)); (* HU_SET = "XLXI_4_0" *) M4_1E_HXILINX_ALU XLXI_4 (.D0(A), - .D1(XLXN_26), + .D1(XLXN_45), .D2(XLXN_33), .D3(XLXN_41), .E(XLXN_12), @@ -929,7 +959,7 @@ module ALU(A, .O(XLXN_22)); (* HU_SET = "XLXI_5_1" *) M4_1E_HXILINX_ALU XLXI_5 (.D0(B), - .D1(XLXN_27), + .D1(XLXN_44), .D2(XLXN_34), .D3(XLXN_39), .E(XLXN_12), @@ -938,7 +968,7 @@ module ALU(A, .O(XLXN_23)); (* HU_SET = "XLXI_6_2" *) M4_1E_HXILINX_ALU XLXI_6 (.D0(C), - .D1(XLXN_28), + .D1(XLXN_43), .D2(XLXN_35), .D3(XLXN_38), .E(XLXN_12), @@ -947,7 +977,7 @@ module ALU(A, .O(XLXN_24)); (* HU_SET = "XLXI_7_3" *) M4_1E_HXILINX_ALU XLXI_7 (.D0(D), - .D1(XLXN_31), + .D1(XLXN_42), .D2(XLXN_36), .D3(XLXN_37), .E(XLXN_12), -- cgit v1.2.3