Xilinx System Settings Report

From 57738e75e221fe61a8f87270b430c0f1c0b8ead5 Mon Sep 17 00:00:00 2001 From: Michael Abed Date: Thu, 16 Feb 2012 15:46:19 -0500 Subject: initial commit --- ALU_envsettings.html | 545 +++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 545 insertions(+) create mode 100644 ALU_envsettings.html (limited to 'ALU_envsettings.html') diff --git a/ALU_envsettings.html b/ALU_envsettings.html new file mode 100644 index 0000000..2c65f7c --- /dev/null +++ b/ALU_envsettings.html @@ -0,0 +1,545 @@ +Xilinx System Settings Report + +System Settings
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Environment Settings
Environment Variable	xst	ngdbuild	map	par
PATH	C: \Xilinx\13.3\ISE_DS\ISE\\lib\nt64;C: \Xilinx\13.3\ISE_DS\ISE\\bin\nt64;C: \Xilinx\13.3\ISE_DS\PlanAhead\bin;C: \Xilinx\13.3\ISE_DS\ISE\bin\nt64;C: \Xilinx\13.3\ISE_DS\ISE\lib\nt64;C: \Xilinx\13.3\ISE_DS\EDK\bin\nt64;C: \Xilinx\13.3\ISE_DS\EDK\lib\nt64;C: \Xilinx\13.3\ISE_DS\EDK\gnu\microblaze\nt64\bin;C: \Xilinx\13.3\ISE_DS\EDK\gnu\powerpc-eabi\nt64\bin;C: \Xilinx\13.3\ISE_DS\EDK\gnuwin\bin;C: \Xilinx\13.3\ISE_DS\common\bin\nt64;C: \Xilinx\13.3\ISE_DS\common\lib\nt64;C: \Windows\system32;C: \Windows;C: \Windows\System32\Wbem;C: \Windows\System32\WindowsPowerShell\v1.0\;C: \Program Files\MATLAB\R2011a\runtime\win64;C: \Program Files\MATLAB\R2011a\bin;C: \VXIPNP\WinNT\Bin;C: \Program Files (x86)\Altium Designer Summer 09\System;C: \Program Files (x86)\QuickTime\QTSystem\;C: \Program Files\NetBeans 7.0.1\java\ant\bin;C: \Program Files\Java\jdk1.6.0_27\bin;C: \Program Files\TortoiseSVN\bin;C: \Program Files (x86)\Rational\Rose RealTime\bin\win32;C: \Program Files (x86)\Rational\common;C: \Cadence\SPB_16.5\OpenAccess\bin\win32\opt;C: \Cadence\SPB_16.5\tools\Capture;C: \Cadence\SPB_16.5\tools\PSpice\Library;C: \Cadence\SPB_16.5\tools\PSpice;C: \Cadence\SPB_16.5\tools\specctra\bin;C: \Cadence\SPB_16.5\tools\fet\bin;C: \Cadence\SPB_16.5\tools\libutil\bin;C: \Cadence\SPB_16.5\tools\bin;C: \Cadence\SPB_16.5\tools\pcb\bin	C: \Xilinx\13.3\ISE_DS\ISE\\lib\nt64;C: \Xilinx\13.3\ISE_DS\ISE\\bin\nt64;C: \Xilinx\13.3\ISE_DS\PlanAhead\bin;C: \Xilinx\13.3\ISE_DS\ISE\bin\nt64;C: \Xilinx\13.3\ISE_DS\ISE\lib\nt64;C: \Xilinx\13.3\ISE_DS\EDK\bin\nt64;C: \Xilinx\13.3\ISE_DS\EDK\lib\nt64;C: \Xilinx\13.3\ISE_DS\EDK\gnu\microblaze\nt64\bin;C: \Xilinx\13.3\ISE_DS\EDK\gnu\powerpc-eabi\nt64\bin;C: \Xilinx\13.3\ISE_DS\EDK\gnuwin\bin;C: \Xilinx\13.3\ISE_DS\common\bin\nt64;C: \Xilinx\13.3\ISE_DS\common\lib\nt64;C: \Windows\system32;C: \Windows;C: \Windows\System32\Wbem;C: \Windows\System32\WindowsPowerShell\v1.0\;C: \Program Files\MATLAB\R2011a\runtime\win64;C: \Program Files\MATLAB\R2011a\bin;C: \VXIPNP\WinNT\Bin;C: \Program Files (x86)\Altium Designer Summer 09\System;C: \Program Files (x86)\QuickTime\QTSystem\;C: \Program Files\NetBeans 7.0.1\java\ant\bin;C: \Program Files\Java\jdk1.6.0_27\bin;C: \Program Files\TortoiseSVN\bin;C: \Program Files (x86)\Rational\Rose RealTime\bin\win32;C: \Program Files (x86)\Rational\common;C: \Cadence\SPB_16.5\OpenAccess\bin\win32\opt;C: \Cadence\SPB_16.5\tools\Capture;C: \Cadence\SPB_16.5\tools\PSpice\Library;C: \Cadence\SPB_16.5\tools\PSpice;C: \Cadence\SPB_16.5\tools\specctra\bin;C: \Cadence\SPB_16.5\tools\fet\bin;C: \Cadence\SPB_16.5\tools\libutil\bin;C: \Cadence\SPB_16.5\tools\bin;C: \Cadence\SPB_16.5\tools\pcb\bin	C: \Xilinx\13.3\ISE_DS\ISE\\lib\nt64;C: \Xilinx\13.3\ISE_DS\ISE\\bin\nt64;C: \Xilinx\13.3\ISE_DS\PlanAhead\bin;C: \Xilinx\13.3\ISE_DS\ISE\bin\nt64;C: \Xilinx\13.3\ISE_DS\ISE\lib\nt64;C: \Xilinx\13.3\ISE_DS\EDK\bin\nt64;C: \Xilinx\13.3\ISE_DS\EDK\lib\nt64;C: \Xilinx\13.3\ISE_DS\EDK\gnu\microblaze\nt64\bin;C: \Xilinx\13.3\ISE_DS\EDK\gnu\powerpc-eabi\nt64\bin;C: \Xilinx\13.3\ISE_DS\EDK\gnuwin\bin;C: \Xilinx\13.3\ISE_DS\common\bin\nt64;C: \Xilinx\13.3\ISE_DS\common\lib\nt64;C: \Windows\system32;C: \Windows;C: \Windows\System32\Wbem;C: \Windows\System32\WindowsPowerShell\v1.0\;C: \Program Files\MATLAB\R2011a\runtime\win64;C: \Program Files\MATLAB\R2011a\bin;C: \VXIPNP\WinNT\Bin;C: \Program Files (x86)\Altium Designer Summer 09\System;C: \Program Files (x86)\QuickTime\QTSystem\;C: \Program Files\NetBeans 7.0.1\java\ant\bin;C: \Program Files\Java\jdk1.6.0_27\bin;C: \Program Files\TortoiseSVN\bin;C: \Program Files (x86)\Rational\Rose RealTime\bin\win32;C: \Program Files (x86)\Rational\common;C: \Cadence\SPB_16.5\OpenAccess\bin\win32\opt;C: \Cadence\SPB_16.5\tools\Capture;C: \Cadence\SPB_16.5\tools\PSpice\Library;C: \Cadence\SPB_16.5\tools\PSpice;C: \Cadence\SPB_16.5\tools\specctra\bin;C: \Cadence\SPB_16.5\tools\fet\bin;C: \Cadence\SPB_16.5\tools\libutil\bin;C: \Cadence\SPB_16.5\tools\bin;C: \Cadence\SPB_16.5\tools\pcb\bin	C: \Xilinx\13.3\ISE_DS\ISE\\lib\nt64;C: \Xilinx\13.3\ISE_DS\ISE\\bin\nt64;C: \Xilinx\13.3\ISE_DS\PlanAhead\bin;C: \Xilinx\13.3\ISE_DS\ISE\bin\nt64;C: \Xilinx\13.3\ISE_DS\ISE\lib\nt64;C: \Xilinx\13.3\ISE_DS\EDK\bin\nt64;C: \Xilinx\13.3\ISE_DS\EDK\lib\nt64;C: \Xilinx\13.3\ISE_DS\EDK\gnu\microblaze\nt64\bin;C: \Xilinx\13.3\ISE_DS\EDK\gnu\powerpc-eabi\nt64\bin;C: \Xilinx\13.3\ISE_DS\EDK\gnuwin\bin;C: \Xilinx\13.3\ISE_DS\common\bin\nt64;C: \Xilinx\13.3\ISE_DS\common\lib\nt64;C: \Windows\system32;C: \Windows;C: \Windows\System32\Wbem;C: \Windows\System32\WindowsPowerShell\v1.0\;C: \Program Files\MATLAB\R2011a\runtime\win64;C: \Program Files\MATLAB\R2011a\bin;C: \VXIPNP\WinNT\Bin;C: \Program Files (x86)\Altium Designer Summer 09\System;C: \Program Files (x86)\QuickTime\QTSystem\;C: \Program Files\NetBeans 7.0.1\java\ant\bin;C: \Program Files\Java\jdk1.6.0_27\bin;C: \Program Files\TortoiseSVN\bin;C: \Program Files (x86)\Rational\Rose RealTime\bin\win32;C: \Program Files (x86)\Rational\common;C: \Cadence\SPB_16.5\OpenAccess\bin\win32\opt;C: \Cadence\SPB_16.5\tools\Capture;C: \Cadence\SPB_16.5\tools\PSpice\Library;C: \Cadence\SPB_16.5\tools\PSpice;C: \Cadence\SPB_16.5\tools\specctra\bin;C: \Cadence\SPB_16.5\tools\fet\bin;C: \Cadence\SPB_16.5\tools\libutil\bin;C: \Cadence\SPB_16.5\tools\bin;C: \Cadence\SPB_16.5\tools\pcb\bin
PATHEXT	.COM;.EXE;.BAT;.CMD;.VBS;.VBE;.JS;.JSE;.WSF;.WSH;.MSC	.COM;.EXE;.BAT;.CMD;.VBS;.VBE;.JS;.JSE;.WSF;.WSH;.MSC	.COM;.EXE;.BAT;.CMD;.VBS;.VBE;.JS;.JSE;.WSF;.WSH;.MSC	.COM;.EXE;.BAT;.CMD;.VBS;.VBE;.JS;.JSE;.WSF;.WSH;.MSC
XILINX	C: \Xilinx\13.3\ISE_DS\ISE\	C: \Xilinx\13.3\ISE_DS\ISE\	C: \Xilinx\13.3\ISE_DS\ISE\	C: \Xilinx\13.3\ISE_DS\ISE\
XILINXD_LICENSE_FILE	2100@XilinxLM.bu.edu	2100@XilinxLM.bu.edu	2100@XilinxLM.bu.edu	2100@XilinxLM.bu.edu
XILINX_DSP	C: \Xilinx\13.3\ISE_DS\ISE	C: \Xilinx\13.3\ISE_DS\ISE	C: \Xilinx\13.3\ISE_DS\ISE	C: \Xilinx\13.3\ISE_DS\ISE
XILINX_EDK	C: \Xilinx\13.3\ISE_DS\EDK	C: \Xilinx\13.3\ISE_DS\EDK	C: \Xilinx\13.3\ISE_DS\EDK	C: \Xilinx\13.3\ISE_DS\EDK
XILINX_PLANAHEAD	C: \Xilinx\13.3\ISE_DS\PlanAhead	C: \Xilinx\13.3\ISE_DS\PlanAhead	C: \Xilinx\13.3\ISE_DS\PlanAhead	C: \Xilinx\13.3\ISE_DS\PlanAhead

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Synthesis Property Settings
Switch Name	Property Name	Value	Default Value
-ifn		ALU.prj
-ofn		ALU
-ofmt		NGC	NGC
-p		xc6slx16-3-csg324
-top		ALU
-opt_mode	Optimization Goal	Speed	Speed
-opt_level	Optimization Effort	1	1
-power	Power Reduction	NO	No
-iuc	Use synthesis Constraints File	NO	No
-keep_hierarchy	Keep Hierarchy	No	No
-netlist_hierarchy	Netlist Hierarchy	As_Optimized	As_Optimized
-rtlview	Generate RTL Schematic	Yes	No
-glob_opt	Global Optimization Goal	AllClockNets	AllClockNets
-read_cores	Read Cores	YES	Yes
-write_timing_constraints	Write Timing Constraints	NO	No
-cross_clock_analysis	Cross Clock Analysis	NO	No
-bus_delimiter	Bus Delimiter	<>	<>
-slice_utilization_ratio	Slice Utilization Ratio	100	100
-bram_utilization_ratio	BRAM Utilization Ratio	100	100
-dsp_utilization_ratio	DSP Utilization Ratio	100	100
-reduce_control_sets		Auto	Auto
-fsm_extract		YES	Yes
-fsm_encoding		Auto	Auto
-safe_implementation		No	No
-fsm_style		LUT	LUT
-ram_extract		Yes	Yes
-ram_style		Auto	Auto
-rom_extract		Yes	Yes
-shreg_extract		YES	Yes
-rom_style		Auto	Auto
-auto_bram_packing		NO	No
-resource_sharing		YES	Yes
-async_to_sync		NO	No
-use_dsp48		Auto	Auto
-iobuf		YES	Yes
-max_fanout		100000	100000
-bufg		16	16
-register_duplication		YES	Yes
-register_balancing		No	No
-optimize_primitives		NO	No
-use_clock_enable		Auto	Auto
-use_sync_set		Auto	Auto
-use_sync_reset		Auto	Auto
-iob		Auto	Auto
-equivalent_register_removal		YES	Yes
-slice_utilization_ratio_maxmargin		5	0

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Translation Property Settings
Switch Name	Property Name	Value	Default Value
-intstyle		ise	None
-dd		_ngo	None
-p		xc6slx16-csg324-3	None
-uc		ALU.ucf	None

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Map Property Settings
Switch Name	Property Name	Value	Default Value
-ol	Place & Route Effort Level (Overall)	high	high
-xt	Extra Cost Tables	0	0
-ir	Use RLOC Constraints	OFF	OFF
-t	Starting Placer Cost Table (1-100) Map	1	0
-r	Register Ordering	4	4
-intstyle		ise	None
-lc	LUT Combining	off	off
-o		ALU_map.ncd	None
-w		true	false
-pr	Pack I/O Registers/Latches into IOBs	off	off
-p		xc6slx16-csg324-3	None

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Place and Route Property Settings
Switch Name	Property Name	Value	Default Value
-intstyle		ise
-mt	Enable Multi-Threading	off	off
-ol	Place & Route Effort Level (Overall)	high	std
-w		true	false

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Operating System Information
Operating System Information	xst	ngdbuild	map	par
CPU Architecture/Speed	Intel(R) Core(TM)2 Duo CPU E8200 @ 2.66GHz/2660 MHz	Intel(R) Core(TM)2 Duo CPU E8200 @ 2.66GHz/2660 MHz	Intel(R) Core(TM)2 Duo CPU E8200 @ 2.66GHz/2660 MHz	Intel(R) Core(TM)2 Duo CPU E8200 @ 2.66GHz/2660 MHz
Host	ECE-PHO115-09	ECE-PHO115-09	ECE-PHO115-09	ECE-PHO115-09
OS Name	Microsoft Windows 7 , 64-bit	Microsoft Windows 7 , 64-bit	Microsoft Windows 7 , 64-bit	Microsoft Windows 7 , 64-bit
OS Release	Service Pack 1 (build 7601)	Service Pack 1 (build 7601)	Service Pack 1 (build 7601)	Service Pack 1 (build 7601)

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