From 70b77304f37d9681aa3bfa0eb57df0bcfd1aef81 Mon Sep 17 00:00:00 2001 From: Michael Abed Date: Fri, 17 Feb 2012 12:08:05 -0500 Subject: make it work --- ALU_map.map | 40 ++++++++++++++++++++-------------------- 1 file changed, 20 insertions(+), 20 deletions(-) (limited to 'ALU_map.map') diff --git a/ALU_map.map b/ALU_map.map index f6a2ce0..693adae 100755 --- a/ALU_map.map +++ b/ALU_map.map @@ -10,7 +10,7 @@ Target Device : xc6slx16 Target Package : csg324 Target Speed : -3 Mapper Version : spartan6 -- $Revision: 1.55 $ -Mapped Date : Wed Feb 15 15:15:50 2012 +Mapped Date : Thu Feb 16 19:52:56 2012 Mapping design into LUTs... Running directed packing... @@ -19,53 +19,53 @@ Updating timing models... INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report (.mrp). Running timing-driven placement... -Total REAL time at the beginning of Placer: 7 secs +Total REAL time at the beginning of Placer: 6 secs Total CPU time at the beginning of Placer: 5 secs Phase 1.1 Initial Placement Analysis -Phase 1.1 Initial Placement Analysis (Checksum:743131b2) REAL time: 9 secs +Phase 1.1 Initial Placement Analysis (Checksum:ecad4836) REAL time: 7 secs Phase 2.7 Design Feasibility Check -Phase 2.7 Design Feasibility Check (Checksum:743131b2) REAL time: 9 secs +Phase 2.7 Design Feasibility Check (Checksum:ecad4836) REAL time: 7 secs Phase 3.31 Local Placement Optimization -Phase 3.31 Local Placement Optimization (Checksum:743131b2) REAL time: 9 secs +Phase 3.31 Local Placement Optimization (Checksum:ecad4836) REAL time: 7 secs Phase 4.2 Initial Placement for Architecture Specific Features Phase 4.2 Initial Placement for Architecture Specific Features -(Checksum:743131b2) REAL time: 9 secs +(Checksum:ecad4836) REAL time: 7 secs Phase 5.36 Local Placement Optimization -Phase 5.36 Local Placement Optimization (Checksum:743131b2) REAL time: 9 secs +Phase 5.36 Local Placement Optimization (Checksum:ecad4836) REAL time: 7 secs Phase 6.30 Global Clock Region Assignment -Phase 6.30 Global Clock Region Assignment (Checksum:743131b2) REAL time: 9 secs +Phase 6.30 Global Clock Region Assignment (Checksum:ecad4836) REAL time: 7 secs Phase 7.3 Local Placement Optimization -Phase 7.3 Local Placement Optimization (Checksum:743131b2) REAL time: 9 secs +Phase 7.3 Local Placement Optimization (Checksum:ecad4836) REAL time: 7 secs Phase 8.5 Local Placement Optimization -Phase 8.5 Local Placement Optimization (Checksum:743131b2) REAL time: 9 secs +Phase 8.5 Local Placement Optimization (Checksum:ecad4836) REAL time: 7 secs Phase 9.8 Global Placement .. .. -Phase 9.8 Global Placement (Checksum:46f7f38f) REAL time: 9 secs +Phase 9.8 Global Placement (Checksum:59a47f53) REAL time: 7 secs Phase 10.5 Local Placement Optimization -Phase 10.5 Local Placement Optimization (Checksum:46f7f38f) REAL time: 9 secs +Phase 10.5 Local Placement Optimization (Checksum:59a47f53) REAL time: 7 secs Phase 11.18 Placement Optimization -Phase 11.18 Placement Optimization (Checksum:9ea3640f) REAL time: 9 secs +Phase 11.18 Placement Optimization (Checksum:87bc4903) REAL time: 7 secs Phase 12.5 Local Placement Optimization -Phase 12.5 Local Placement Optimization (Checksum:9ea3640f) REAL time: 10 secs +Phase 12.5 Local Placement Optimization (Checksum:87bc4903) REAL time: 7 secs Phase 13.34 Placement Validation -Phase 13.34 Placement Validation (Checksum:9ea3640f) REAL time: 10 secs +Phase 13.34 Placement Validation (Checksum:87bc4903) REAL time: 7 secs -Total REAL time to Placer completion: 10 secs -Total CPU time to Placer completion: 5 secs +Total REAL time to Placer completion: 7 secs +Total CPU time to Placer completion: 6 secs Running post-placement packing... Writing output files... @@ -86,7 +86,7 @@ Slice Logic Utilization: Number used as Memory: 0 out of 2,176 0% Slice Logic Distribution: - Number of occupied Slices: 5 out of 2,278 1% + Number of occupied Slices: 6 out of 2,278 1% Nummber of MUXCYs used: 0 out of 4,556 0% Number of LUT Flip Flop pairs used: 13 Number with an unused Flip Flop: 13 out of 13 100% @@ -130,8 +130,8 @@ Specific Feature Utilization: Average Fanout of Non-Clock Nets: 3.32 -Peak Memory Usage: 352 MB -Total REAL time to MAP completion: 11 secs +Peak Memory Usage: 351 MB +Total REAL time to MAP completion: 8 secs Total CPU time to MAP completion: 6 secs Mapping completed. -- cgit v1.2.3