From 57738e75e221fe61a8f87270b430c0f1c0b8ead5 Mon Sep 17 00:00:00 2001 From: Michael Abed Date: Thu, 16 Feb 2012 15:46:19 -0500 Subject: initial commit --- ALU_summary.html | 343 +++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 343 insertions(+) create mode 100755 ALU_summary.html (limited to 'ALU_summary.html') diff --git a/ALU_summary.html b/ALU_summary.html new file mode 100755 index 0000000..840a7a1 --- /dev/null +++ b/ALU_summary.html @@ -0,0 +1,343 @@ +Xilinx Design Summary + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
ALU Project Status
Project File:lab1.xiseParser Errors: No Errors
Module Name:ALUImplementation State:Placed and Routed
Target Device:xc6slx16-3csg324
  • Errors:
 +No Errors
Product Version:ISE 13.4
  • Warnings:
2 Warnings (0 new)
Design Goal:Balanced
  • Routing Results:
 +All Signals Completely Routed
Design Strategy:Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment: + +System Settings +
  • Final Timing Score:
0  (Timing Report)
+ + + + 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Device Utilization Summary [-]
Slice Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Registers018,2240% 
Number of Slice LUTs139,1121% 
    Number used as logic139,1121% 
        Number using O6 output only13   
        Number using O5 output only0   
        Number using O5 and O60   
        Number used as ROM0   
    Number used as Memory02,1760% 
Number of occupied Slices52,2781% 
Nummber of MUXCYs used04,5560% 
Number of LUT Flip Flop pairs used13   
    Number with an unused Flip Flop1313100% 
    Number with an unused LUT0130% 
    Number of fully used LUT-FF pairs0130% 
    Number of slice register sites lost
        to control set restrictions		018,2240% 
Number of bonded IOBs182327% 
    Number of LOCed IOBs1818100% 
Number of RAMB16BWERs0320% 
Number of RAMB8BWERs0640% 
Number of BUFIO2/BUFIO2_2CLKs0320% 
Number of BUFIO2FB/BUFIO2FB_2CLKs0320% 
Number of BUFG/BUFGMUXs0160% 
Number of DCM/DCM_CLKGENs040% 
Number of ILOGIC2/ISERDES2s02480% 
Number of IODELAY2/IODRP2/IODRP2_MCBs02480% 
Number of OLOGIC2/OSERDES2s02480% 
Number of BSCANs040% 
Number of BUFHs01280% 
Number of BUFPLLs080% 
Number of BUFPLL_MCBs040% 
Number of DSP48A1s0320% 
Number of ICAPs010% 
Number of MCBs020% 
Number of PCILOGICSEs020% 
Number of PLL_ADVs020% 
Number of PMVs010% 
Number of STARTUPs010% 
Number of SUSPEND_SYNCs010% 
Average Fanout of Non-Clock Nets3.32   
+ + + + 
+ + + + + + + + + + + + + + + + + +
Performance Summary [-]
Final Timing Score:0 (Setup: 0, Hold: 0)Pinout Data:Pinout Report
Routing Results: +All Signals Completely RoutedClock Data:Clock Report
Timing Constraints:   
+ + + + 
+ + + + + + + + + + +
Detailed Reports [-]
Report NameStatusGeneratedErrorsWarningsInfos
Synthesis ReportCurrentWed Feb 15 18:59:45 201202 Warnings (0 new)0
Translation ReportCurrentWed Feb 15 18:59:45 2012000
Map ReportCurrentWed Feb 15 18:59:45 2012006 Infos (6 new)
Place and Route ReportCurrentWed Feb 15 18:59:46 2012002 Infos (2 new)
Power Report     
Post-PAR Static Timing ReportCurrentWed Feb 15 18:59:46 2012003 Infos (3 new)
Bitgen Report     
+ 
+ + + + +
Secondary Reports [-]
Report NameStatusGenerated
WebTalk ReportCurrentWed Feb 15 18:59:48 2012
WebTalk Log FileCurrentWed Feb 15 18:59:48 2012
+ + +
Date Generated: 02/15/2012 - 19:01:09
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