From 57738e75e221fe61a8f87270b430c0f1c0b8ead5 Mon Sep 17 00:00:00 2001
From: Michael Abed <michaelabed@gmail.com>
Date: Thu, 16 Feb 2012 15:46:19 -0500
Subject: initial commit

---
 Divide_3.vf | 44 ++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 44 insertions(+)
 create mode 100755 Divide_3.vf

(limited to 'Divide_3.vf')

diff --git a/Divide_3.vf b/Divide_3.vf
new file mode 100755
index 0000000..7a443d9
--- /dev/null
+++ b/Divide_3.vf
@@ -0,0 +1,44 @@
+////////////////////////////////////////////////////////////////////////////////
+// Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved.
+////////////////////////////////////////////////////////////////////////////////
+//   ____  ____ 
+//  /   /\/   / 
+// /___/  \  /    Vendor: Xilinx 
+// \   \   \/     Version : 13.3
+//  \   \         Application : sch2hdl
+//  /   /         Filename : Divide_3.vf
+// /___/   /\     Timestamp : 02/15/2012 15:00:07
+// \   \  /  \ 
+//  \___\/\___\ 
+//
+//Command: sch2hdl -intstyle ise -family spartan6 -verilog "X:/My Documents/ec311/lab1/Divide_3.vf" -w "X:/My Documents/ec311/lab1/Divide_3.sch"
+//Design Name: Divide_3
+//Device: spartan6
+//Purpose:
+//    This verilog netlist is translated from an ECS schematic.It can be 
+//    synthesized and simulated, but it should not be modified. 
+//
+`timescale 1ns / 1ps
+
+module Divide_3(b0, 
+                b1, 
+                b2, 
+                b3, 
+                result);
+
+    input b0;
+    input b1;
+    input b2;
+    input b3;
+   output result;
+   
+   wire XLXN_2;
+   
+   AND2  XLXI_2 (.I0(XLXN_2), 
+                .I1(b3), 
+                .O(result));
+   NOR3  XLXI_3 (.I0(b0), 
+                .I1(b1), 
+                .I2(b2), 
+                .O(XLXN_2));
+endmodule
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