From 70b77304f37d9681aa3bfa0eb57df0bcfd1aef81 Mon Sep 17 00:00:00 2001
From: Michael Abed <michaelabed@gmail.com>
Date: Fri, 17 Feb 2012 12:08:05 -0500
Subject: make it work

---
 Modulo.vf | 91 +++++++++++++++++++++++++++++++++++++--------------------------
 1 file changed, 54 insertions(+), 37 deletions(-)

(limited to 'Modulo.vf')

diff --git a/Modulo.vf b/Modulo.vf
index 045ae26..0007fe1 100755
--- a/Modulo.vf
+++ b/Modulo.vf
@@ -7,11 +7,11 @@
 // \   \   \/     Version : 13.3
 //  \   \         Application : sch2hdl
 //  /   /         Filename : Modulo.vf
-// /___/   /\     Timestamp : 02/15/2012 15:00:07
+// /___/   /\     Timestamp : 02/16/2012 19:52:31
 // \   \  /  \ 
 //  \___\/\___\ 
 //
-//Command: sch2hdl -intstyle ise -family spartan6 -verilog "X:/My Documents/ec311/lab1/Modulo.vf" -w "X:/My Documents/ec311/lab1/Modulo.sch"
+//Command: sch2hdl -intstyle ise -family spartan6 -verilog "X:/My Documents/ec311/ec311-lab1/Modulo.vf" -w "X:/My Documents/ec311/ec311-lab1/Modulo.sch"
 //Design Name: Modulo
 //Device: spartan6
 //Purpose:
@@ -35,23 +35,40 @@ module Modulo_0_MUSER_Modulo(b0,
    wire XLXN_1;
    wire XLXN_3;
    wire XLXN_4;
-   wire XLXN_5;
+   wire XLXN_12;
+   wire XLXN_14;
+   wire XLXN_15;
+   wire XLXN_16;
+   wire XLXN_27;
+   wire XLXN_28;
    
-   XNOR2  XLXI_1 (.I0(b0), 
-                 .I1(b1), 
-                 .O(XLXN_1));
    AND2  XLXI_2 (.I0(XLXN_1), 
                 .I1(b2), 
                 .O(XLXN_4));
-   NAND3  XLXI_3 (.I0(XLXN_5), 
-                 .I1(b1), 
-                 .I2(b2), 
-                 .O(XLXN_3));
    OR2  XLXI_4 (.I0(XLXN_4), 
                .I1(XLXN_3), 
                .O(result));
-   INV  XLXI_5 (.I(b0), 
-               .O(XLXN_5));
+   INV  XLXI_9 (.I(b1), 
+               .O(XLXN_15));
+   INV  XLXI_10 (.I(b0), 
+                .O(XLXN_16));
+   AND3  XLXI_11 (.I0(b0), 
+                 .I1(XLXN_28), 
+                 .I2(XLXN_27), 
+                 .O(XLXN_3));
+   INV  XLXI_12 (.I(b2), 
+                .O(XLXN_27));
+   INV  XLXI_13 (.I(b1), 
+                .O(XLXN_28));
+   OR2  XLXI_14 (.I0(XLXN_14), 
+                .I1(XLXN_12), 
+                .O(XLXN_1));
+   AND2  XLXI_15 (.I0(b0), 
+                 .I1(b1), 
+                 .O(XLXN_12));
+   AND2  XLXI_16 (.I0(XLXN_16), 
+                 .I1(XLXN_15), 
+                 .O(XLXN_14));
 endmodule
 `timescale 1ns / 1ps
 
@@ -67,24 +84,24 @@ module Modulo_1_MUSER_Modulo(b0,
     input b3;
    output result;
    
-   wire XLXN_1;
    wire XLXN_2;
    wire XLXN_3;
    wire XLXN_5;
    wire XLXN_6;
    wire XLXN_7;
-   wire XLXN_18;
-   wire XLXN_19;
-   wire XLXN_20;
-   wire XLXN_21;
-   wire XLXN_22;
    wire XLXN_23;
    wire XLXN_24;
+   wire XLXN_50;
+   wire XLXN_51;
+   wire XLXN_54;
+   wire XLXN_55;
+   wire XLXN_56;
+   wire XLXN_57;
    
    AND3  XLXI_1 (.I0(b1), 
                 .I1(b2), 
                 .I2(b3), 
-                .O(XLXN_1));
+                .O(XLXN_55));
    AND3  XLXI_2 (.I0(XLXN_6), 
                 .I1(XLXN_5), 
                 .I2(b3), 
@@ -93,38 +110,38 @@ module Modulo_1_MUSER_Modulo(b0,
                 .I1(XLXN_7), 
                 .I2(b3), 
                 .O(XLXN_3));
-   OR3  XLXI_4 (.I0(XLXN_3), 
-               .I1(XLXN_2), 
-               .I2(XLXN_1), 
-               .O(XLXN_21));
    INV  XLXI_5 (.I(b1), 
                .O(XLXN_5));
    INV  XLXI_6 (.I(b0), 
                .O(XLXN_6));
    INV  XLXI_7 (.I(b2), 
                .O(XLXN_7));
-   OR2  XLXI_9 (.I0(XLXN_20), 
-               .I1(XLXN_21), 
-               .O(result));
    AND4  XLXI_11 (.I0(b0), 
                  .I1(XLXN_24), 
                  .I2(b2), 
                  .I3(XLXN_23), 
-                 .O(XLXN_19));
-   OR2  XLXI_12 (.I0(XLXN_19), 
-                .I1(XLXN_18), 
-                .O(XLXN_20));
-   NAND4  XLXI_13 (.I0(b0), 
-                  .I1(XLXN_22), 
-                  .I2(b2), 
-                  .I3(b3), 
-                  .O(XLXN_18));
-   INV  XLXI_14 (.I(b1), 
-                .O(XLXN_22));
+                 .O(XLXN_57));
    INV  XLXI_15 (.I(b3), 
                 .O(XLXN_23));
    INV  XLXI_16 (.I(b1), 
                 .O(XLXN_24));
+   AND4  XLXI_18 (.I0(XLXN_54), 
+                 .I1(b1), 
+                 .I2(XLXN_50), 
+                 .I3(XLXN_51), 
+                 .O(XLXN_56));
+   INV  XLXI_19 (.I(b2), 
+                .O(XLXN_50));
+   INV  XLXI_20 (.I(b3), 
+                .O(XLXN_51));
+   INV  XLXI_21 (.I(b0), 
+                .O(XLXN_54));
+   OR5  XLXI_22 (.I0(XLXN_57), 
+                .I1(XLXN_56), 
+                .I2(XLXN_3), 
+                .I3(XLXN_2), 
+                .I4(XLXN_55), 
+                .O(result));
 endmodule
 `timescale 1ns / 1ps
 
-- 
cgit v1.2.3-54-g00ecf