From 57738e75e221fe61a8f87270b430c0f1c0b8ead5 Mon Sep 17 00:00:00 2001
From: Michael Abed <michaelabed@gmail.com>
Date: Thu, 16 Feb 2012 15:46:19 -0500
Subject: initial commit

---
 Modulo_1.vf | 93 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 93 insertions(+)
 create mode 100755 Modulo_1.vf

(limited to 'Modulo_1.vf')

diff --git a/Modulo_1.vf b/Modulo_1.vf
new file mode 100755
index 0000000..8232c5f
--- /dev/null
+++ b/Modulo_1.vf
@@ -0,0 +1,93 @@
+////////////////////////////////////////////////////////////////////////////////
+// Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved.
+////////////////////////////////////////////////////////////////////////////////
+//   ____  ____ 
+//  /   /\/   / 
+// /___/  \  /    Vendor: Xilinx 
+// \   \   \/     Version : 13.3
+//  \   \         Application : sch2hdl
+//  /   /         Filename : Modulo_1.vf
+// /___/   /\     Timestamp : 02/15/2012 15:00:10
+// \   \  /  \ 
+//  \___\/\___\ 
+//
+//Command: sch2hdl -intstyle ise -family spartan6 -verilog "X:/My Documents/ec311/lab1/Modulo_1.vf" -w "X:/My Documents/ec311/lab1/Modulo_1.sch"
+//Design Name: Modulo_1
+//Device: spartan6
+//Purpose:
+//    This verilog netlist is translated from an ECS schematic.It can be 
+//    synthesized and simulated, but it should not be modified. 
+//
+`timescale 1ns / 1ps
+
+module Modulo_1(b0, 
+                b1, 
+                b2, 
+                b3, 
+                result);
+
+    input b0;
+    input b1;
+    input b2;
+    input b3;
+   output result;
+   
+   wire XLXN_1;
+   wire XLXN_2;
+   wire XLXN_3;
+   wire XLXN_5;
+   wire XLXN_6;
+   wire XLXN_7;
+   wire XLXN_18;
+   wire XLXN_19;
+   wire XLXN_20;
+   wire XLXN_21;
+   wire XLXN_22;
+   wire XLXN_23;
+   wire XLXN_24;
+   
+   AND3  XLXI_1 (.I0(b1), 
+                .I1(b2), 
+                .I2(b3), 
+                .O(XLXN_1));
+   AND3  XLXI_2 (.I0(XLXN_6), 
+                .I1(XLXN_5), 
+                .I2(b3), 
+                .O(XLXN_2));
+   AND3  XLXI_3 (.I0(b0), 
+                .I1(XLXN_7), 
+                .I2(b3), 
+                .O(XLXN_3));
+   OR3  XLXI_4 (.I0(XLXN_3), 
+               .I1(XLXN_2), 
+               .I2(XLXN_1), 
+               .O(XLXN_21));
+   INV  XLXI_5 (.I(b1), 
+               .O(XLXN_5));
+   INV  XLXI_6 (.I(b0), 
+               .O(XLXN_6));
+   INV  XLXI_7 (.I(b2), 
+               .O(XLXN_7));
+   OR2  XLXI_9 (.I0(XLXN_20), 
+               .I1(XLXN_21), 
+               .O(result));
+   AND4  XLXI_11 (.I0(b0), 
+                 .I1(XLXN_24), 
+                 .I2(b2), 
+                 .I3(XLXN_23), 
+                 .O(XLXN_19));
+   OR2  XLXI_12 (.I0(XLXN_19), 
+                .I1(XLXN_18), 
+                .O(XLXN_20));
+   NAND4  XLXI_13 (.I0(b0), 
+                  .I1(XLXN_22), 
+                  .I2(b2), 
+                  .I3(b3), 
+                  .O(XLXN_18));
+   INV  XLXI_14 (.I(b1), 
+                .O(XLXN_22));
+   INV  XLXI_15 (.I(b3), 
+                .O(XLXN_23));
+   INV  XLXI_16 (.I(b1), 
+                .O(XLXN_24));
+endmodule
-- 
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