From 57738e75e221fe61a8f87270b430c0f1c0b8ead5 Mon Sep 17 00:00:00 2001 From: Michael Abed Date: Thu, 16 Feb 2012 15:46:19 -0500 Subject: initial commit --- Negate_1.vf | 62 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 62 insertions(+) create mode 100755 Negate_1.vf (limited to 'Negate_1.vf') diff --git a/Negate_1.vf b/Negate_1.vf new file mode 100755 index 0000000..23a40c7 --- /dev/null +++ b/Negate_1.vf @@ -0,0 +1,62 @@ +//////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. +//////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version : 13.3 +// \ \ Application : sch2hdl +// / / Filename : Negate_1.vf +// /___/ /\ Timestamp : 02/15/2012 15:00:09 +// \ \ / \ +// \___\/\___\ +// +//Command: sch2hdl -intstyle ise -family spartan6 -verilog "X:/My Documents/ec311/lab1/Negate_1.vf" -w "X:/My Documents/ec311/lab1/Negate_1.sch" +//Design Name: Negate_1 +//Device: spartan6 +//Purpose: +// This verilog netlist is translated from an ECS schematic.It can be +// synthesized and simulated, but it should not be modified. +// +`timescale 1ns / 1ps + +module Negate_1(b0, + b1, + b2, + b3, + result); + + input b0; + input b1; + input b2; + input b3; + output result; + + wire XLXN_1; + wire XLXN_2; + wire XLXN_3; + wire XLXN_4; + wire XLXN_5; + wire XLXN_6; + + AND2 XLXI_1 (.I0(b1), + .I1(XLXN_6), + .O(XLXN_2)); + AND2 XLXI_2 (.I0(XLXN_5), + .I1(b0), + .O(XLXN_1)); + AND3 XLXI_3 (.I0(XLXN_4), + .I1(XLXN_5), + .I2(b3), + .O(XLXN_3)); + OR3 XLXI_4 (.I0(XLXN_3), + .I1(XLXN_1), + .I2(XLXN_2), + .O(result)); + INV XLXI_5 (.I(b2), + .O(XLXN_4)); + INV XLXI_6 (.I(b1), + .O(XLXN_5)); + INV XLXI_7 (.I(b0), + .O(XLXN_6)); +endmodule -- cgit v1.2.3