From 57738e75e221fe61a8f87270b430c0f1c0b8ead5 Mon Sep 17 00:00:00 2001 From: Michael Abed Date: Thu, 16 Feb 2012 15:46:19 -0500 Subject: initial commit --- Negate_2.vf | 62 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 62 insertions(+) create mode 100755 Negate_2.vf (limited to 'Negate_2.vf') diff --git a/Negate_2.vf b/Negate_2.vf new file mode 100755 index 0000000..6ce41b2 --- /dev/null +++ b/Negate_2.vf @@ -0,0 +1,62 @@ +//////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. +//////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version : 13.3 +// \ \ Application : sch2hdl +// / / Filename : Negate_2.vf +// /___/ /\ Timestamp : 02/15/2012 15:00:09 +// \ \ / \ +// \___\/\___\ +// +//Command: sch2hdl -intstyle ise -family spartan6 -verilog "X:/My Documents/ec311/lab1/Negate_2.vf" -w "X:/My Documents/ec311/lab1/Negate_2.sch" +//Design Name: Negate_2 +//Device: spartan6 +//Purpose: +// This verilog netlist is translated from an ECS schematic.It can be +// synthesized and simulated, but it should not be modified. +// +`timescale 1ns / 1ps + +module Negate_2(b0, + b1, + b2, + b3, + result); + + input b0; + input b1; + input b2; + input b3; + output result; + + wire XLXN_7; + wire XLXN_9; + wire XLXN_10; + wire XLXN_12; + wire XLXN_16; + wire XLXN_17; + + AND2 XLXI_1 (.I0(XLXN_7), + .I1(b3), + .O(XLXN_9)); + AND3 XLXI_2 (.I0(b2), + .I1(XLXN_16), + .I2(XLXN_17), + .O(XLXN_10)); + OR2 XLXI_3 (.I0(XLXN_10), + .I1(XLXN_9), + .O(result)); + OR3 XLXI_4 (.I0(XLXN_12), + .I1(b1), + .I2(b0), + .O(XLXN_7)); + INV XLXI_5 (.I(b2), + .O(XLXN_12)); + INV XLXI_6 (.I(b1), + .O(XLXN_16)); + INV XLXI_7 (.I(b0), + .O(XLXN_17)); +endmodule -- cgit v1.2.3