From 57738e75e221fe61a8f87270b430c0f1c0b8ead5 Mon Sep 17 00:00:00 2001 From: Michael Abed Date: Thu, 16 Feb 2012 15:46:19 -0500 Subject: initial commit --- pa.fromHdl.tcl | 58 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 58 insertions(+) create mode 100755 pa.fromHdl.tcl (limited to 'pa.fromHdl.tcl') diff --git a/pa.fromHdl.tcl b/pa.fromHdl.tcl new file mode 100755 index 0000000..68516e9 --- /dev/null +++ b/pa.fromHdl.tcl @@ -0,0 +1,58 @@ + +# PlanAhead Launch Script for Pre-Synthesis Floorplanning, created by Project Navigator + +create_project -name lab1 -dir "X:/My Documents/ec311/lab1/planAhead_run_1" -part xc6slx16csg324-3 +set_param project.pinAheadLayout yes +set srcset [get_property srcset [current_run -impl]] +set_property top ALU $srcset +set_property target_constrs_file "ALU.ucf" [current_fileset -constrset] +set hdlfile [add_files [list {Negate_3.vf}]] +set_property file_type Verilog $hdlfile +set_property library work $hdlfile +set hdlfile [add_files [list {Negate_2.vf}]] +set_property file_type Verilog $hdlfile +set_property library work $hdlfile +set hdlfile [add_files [list {Negate_1.vf}]] +set_property file_type Verilog $hdlfile +set_property library work $hdlfile +set hdlfile [add_files [list {Negate_0.vf}]] +set_property file_type Verilog $hdlfile +set_property library work $hdlfile +set hdlfile [add_files [list {Modulo_3.vf}]] +set_property file_type Verilog $hdlfile +set_property library work $hdlfile +set hdlfile [add_files [list {Modulo_1.vf}]] +set_property file_type Verilog $hdlfile +set_property library work $hdlfile +set hdlfile [add_files [list {Modulo_0.vf}]] +set_property file_type Verilog $hdlfile +set_property library work $hdlfile +set hdlfile [add_files [list {Divide_3.vf}]] +set_property file_type Verilog $hdlfile +set_property library work $hdlfile +set hdlfile [add_files [list {Divide_2.vf}]] +set_property file_type Verilog $hdlfile +set_property library work $hdlfile +set hdlfile [add_files [list {Divide_1.vf}]] +set_property file_type Verilog $hdlfile +set_property library work $hdlfile +set hdlfile [add_files [list {Divide_0.vf}]] +set_property file_type Verilog $hdlfile +set_property library work $hdlfile +set hdlfile [add_files [list {sev_seg_disp.vf}]] +set_property file_type Verilog $hdlfile +set_property library work $hdlfile +set hdlfile [add_files [list {Negate.vf}]] +set_property file_type Verilog $hdlfile +set_property library work $hdlfile +set hdlfile [add_files [list {Modulo.vf}]] +set_property file_type Verilog $hdlfile +set_property library work $hdlfile +set hdlfile [add_files [list {Divide.vf}]] +set_property file_type Verilog $hdlfile +set_property library work $hdlfile +set hdlfile [add_files [list {ALU.vf}]] +set_property file_type Verilog $hdlfile +set_property library work $hdlfile +add_files [list {ALU.ucf}] -fileset [get_property constrset [current_run]] +open_rtl_design -part xc6slx16csg324-3 -- cgit v1.2.3