Release 13.3 - xst O.76xd (nt64) Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. --> Parameter TMPDIR set to xst/projnav.tmp Total REAL time to Xst completion: 0.00 secs Total CPU time to Xst completion: 0.11 secs --> Parameter xsthdpdir set to xst Total REAL time to Xst completion: 0.00 secs Total CPU time to Xst completion: 0.11 secs --> Reading design: ALU.prj TABLE OF CONTENTS 1) Synthesis Options Summary 2) HDL Parsing 3) HDL Elaboration 4) HDL Synthesis 4.1) HDL Synthesis Report 5) Advanced HDL Synthesis 5.1) Advanced HDL Synthesis Report 6) Low Level Synthesis 7) Partition Report 8) Design Summary 8.1) Primitive and Black Box Usage 8.2) Device utilization summary 8.3) Partition Resource Summary 8.4) Timing Report 8.4.1) Clock Information 8.4.2) Asynchronous Control Signals Information 8.4.3) Timing Summary 8.4.4) Timing Details 8.4.5) Cross Clock Domains Report ========================================================================= * Synthesis Options Summary * ========================================================================= ---- Source Parameters Input File Name : "ALU.prj" Ignore Synthesis Constraint File : NO ---- Target Parameters Output File Name : "ALU" Output Format : NGC Target Device : xc6slx16-3-csg324 ---- Source Options Top Module Name : ALU Automatic FSM Extraction : YES FSM Encoding Algorithm : Auto Safe Implementation : No FSM Style : LUT RAM Extraction : Yes RAM Style : Auto ROM Extraction : Yes Shift Register Extraction : YES ROM Style : Auto Resource Sharing : YES Asynchronous To Synchronous : NO Shift Register Minimum Size : 2 Use DSP Block : Auto Automatic Register Balancing : No ---- Target Options LUT Combining : Auto Reduce Control Sets : Auto Add IO Buffers : YES Global Maximum Fanout : 100000 Add Generic Clock Buffer(BUFG) : 16 Register Duplication : YES Optimize Instantiated Primitives : NO Use Clock Enable : Auto Use Synchronous Set : Auto Use Synchronous Reset : Auto Pack IO Registers into IOBs : Auto Equivalent register Removal : YES ---- General Options Optimization Goal : Speed Optimization Effort : 1 Power Reduction : NO Keep Hierarchy : No Netlist Hierarchy : As_Optimized RTL Output : Yes Global Optimization : AllClockNets Read Cores : YES Write Timing Constraints : NO Cross Clock Analysis : NO Hierarchy Separator : / Bus Delimiter : <> Case Specifier : Maintain Slice Utilization Ratio : 100 BRAM Utilization Ratio : 100 DSP48 Utilization Ratio : 100 Auto BRAM Packing : NO Slice Utilization Ratio Delta : 5 ========================================================================= ========================================================================= * HDL Parsing * ========================================================================= Analyzing Verilog file "\\ad\eng\users\m\g\mgabed\My Documents\ec311\ec311-lab1\Negate_3.vf" into library work Parsing module . Analyzing Verilog file "\\ad\eng\users\m\g\mgabed\My Documents\ec311\ec311-lab1\Negate_2.vf" into library work Parsing module . Analyzing Verilog file "\\ad\eng\users\m\g\mgabed\My Documents\ec311\ec311-lab1\Negate_1.vf" into library work Parsing module . Analyzing Verilog file "\\ad\eng\users\m\g\mgabed\My Documents\ec311\ec311-lab1\Negate_0.vf" into library work Parsing module . Analyzing Verilog file "\\ad\eng\users\m\g\mgabed\My Documents\ec311\ec311-lab1\Modulo_3.vf" into library work Parsing module . Analyzing Verilog file "\\ad\eng\users\m\g\mgabed\My Documents\ec311\ec311-lab1\Modulo_1.vf" into library work Parsing module . Analyzing Verilog file "\\ad\eng\users\m\g\mgabed\My Documents\ec311\ec311-lab1\Modulo_0.vf" into library work Parsing module . Analyzing Verilog file "\\ad\eng\users\m\g\mgabed\My Documents\ec311\ec311-lab1\Divide_3.vf" into library work Parsing module . Analyzing Verilog file "\\ad\eng\users\m\g\mgabed\My Documents\ec311\ec311-lab1\Divide_2.vf" into library work Parsing module . Analyzing Verilog file "\\ad\eng\users\m\g\mgabed\My Documents\ec311\ec311-lab1\Divide_1.vf" into library work Parsing module . Analyzing Verilog file "\\ad\eng\users\m\g\mgabed\My Documents\ec311\ec311-lab1\Divide_0.vf" into library work Parsing module . Analyzing Verilog file "\\ad\eng\users\m\g\mgabed\My Documents\ec311\ec311-lab1\sev_seg_disp.vf" into library work Parsing module . Analyzing Verilog file "\\ad\eng\users\m\g\mgabed\My Documents\ec311\ec311-lab1\Negate.vf" into library work Parsing module . Parsing module . Parsing module . Parsing module . Parsing module . Analyzing Verilog file "\\ad\eng\users\m\g\mgabed\My Documents\ec311\ec311-lab1\Modulo.vf" into library work Parsing module . Parsing module . Parsing module . Parsing module . Analyzing Verilog file "\\ad\eng\users\m\g\mgabed\My Documents\ec311\ec311-lab1\Divide.vf" into library work Parsing module . Parsing module . Parsing module . Parsing module . Parsing module . Analyzing Verilog file "\\ad\eng\users\m\g\mgabed\My Documents\ec311\ec311-lab1\ALU.vf" into library work Parsing module . Parsing module . Parsing module . Parsing module . Parsing module . Parsing module . Parsing module . Parsing module . Parsing module . Parsing module . Parsing module . Parsing module . Parsing module . Parsing module . Parsing module . Parsing module . Parsing module . ========================================================================= * HDL Elaboration * ========================================================================= Elaborating module . Elaborating module . Elaborating module . Elaborating module . Elaborating module . Elaborating module . Elaborating module . Elaborating module . Elaborating module . Elaborating module . Elaborating module . Elaborating module . Elaborating module . Elaborating module . Elaborating module . Elaborating module . Elaborating module . Elaborating module . Elaborating module . Elaborating module . Elaborating module . Elaborating module . Elaborating module . Elaborating module . Elaborating module . Elaborating module . Elaborating module . Elaborating module . Elaborating module . Elaborating module . ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit . Related source file is "//ad/eng/users/m/g/mgabed/my documents/ec311/ec311-lab1/alu.vf". Set property "HU_SET = XLXI_4_0" for instance . Set property "HU_SET = XLXI_5_1" for instance . Set property "HU_SET = XLXI_6_2" for instance . Set property "HU_SET = XLXI_7_3" for instance . Summary: no macro. Unit synthesized. Synthesizing Unit . Related source file is "//ad/eng/users/m/g/mgabed/my documents/ec311/ec311-lab1/alu.vf". Summary: no macro. Unit synthesized. Synthesizing Unit . Related source file is "//ad/eng/users/m/g/mgabed/my documents/ec311/ec311-lab1/alu.vf". Summary: no macro. Unit synthesized. Synthesizing Unit . Related source file is "//ad/eng/users/m/g/mgabed/my documents/ec311/ec311-lab1/alu.vf". Summary: no macro. Unit synthesized. Synthesizing Unit . Related source file is "//ad/eng/users/m/g/mgabed/my documents/ec311/ec311-lab1/alu.vf". Summary: no macro. Unit synthesized. Synthesizing Unit . Related source file is "//ad/eng/users/m/g/mgabed/my documents/ec311/ec311-lab1/alu.vf". WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. Summary: no macro. Unit synthesized. Synthesizing Unit . Related source file is "//ad/eng/users/m/g/mgabed/my documents/ec311/ec311-lab1/alu.vf". Summary: no macro. Unit synthesized. Synthesizing Unit . Related source file is "//ad/eng/users/m/g/mgabed/my documents/ec311/ec311-lab1/alu.vf". Summary: no macro. Unit synthesized. Synthesizing Unit . Related source file is "//ad/eng/users/m/g/mgabed/my documents/ec311/ec311-lab1/alu.vf". Summary: no macro. Unit synthesized. Synthesizing Unit . Related source file is "//ad/eng/users/m/g/mgabed/my documents/ec311/ec311-lab1/alu.vf". WARNING:Xst:647 - Input is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. Summary: no macro. Unit synthesized. Synthesizing Unit . Related source file is "//ad/eng/users/m/g/mgabed/my documents/ec311/ec311-lab1/alu.vf". Summary: no macro. Unit synthesized. Synthesizing Unit . Related source file is "//ad/eng/users/m/g/mgabed/my documents/ec311/ec311-lab1/alu.vf". Summary: no macro. Unit synthesized. Synthesizing Unit . Related source file is "//ad/eng/users/m/g/mgabed/my documents/ec311/ec311-lab1/alu.vf". Summary: no macro. Unit synthesized. Synthesizing Unit . Related source file is "//ad/eng/users/m/g/mgabed/my documents/ec311/ec311-lab1/alu.vf". Summary: no macro. Unit synthesized. Synthesizing Unit . Related source file is "//ad/eng/users/m/g/mgabed/my documents/ec311/ec311-lab1/alu.vf". Summary: no macro. Unit synthesized. Synthesizing Unit . Related source file is "//ad/eng/users/m/g/mgabed/my documents/ec311/ec311-lab1/alu.vf". Found 1-bit 4-to-1 multiplexer for signal created at line 44. Summary: inferred 2 Multiplexer(s). Unit synthesized. Synthesizing Unit . Related source file is "//ad/eng/users/m/g/mgabed/my documents/ec311/ec311-lab1/alu.vf". Summary: no macro. Unit synthesized. ========================================================================= HDL Synthesis Report Macro Statistics # Multiplexers : 8 1-bit 2-to-1 multiplexer : 4 1-bit 4-to-1 multiplexer : 4 ========================================================================= ========================================================================= * Advanced HDL Synthesis * ========================================================================= ========================================================================= Advanced HDL Synthesis Report Macro Statistics # Multiplexers : 8 1-bit 2-to-1 multiplexer : 4 1-bit 4-to-1 multiplexer : 4 ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... Optimizing unit ... Optimizing unit ... Optimizing unit ... Mapping all equations... Building and optimizing final netlist ... Found area constraint ratio of 100 (+ 5) on block ALU, actual ratio is 0. Final Macro Processing ... ========================================================================= Final Register Report Found no macro ========================================================================= ========================================================================= * Partition Report * ========================================================================= Partition Implementation Status ------------------------------- No Partitions were found in this design. ------------------------------- ========================================================================= * Design Summary * ========================================================================= Top Level Output File Name : ALU.ngc Primitive and Black Box Usage: ------------------------------ # BELS : 138 # AND2 : 28 # AND3 : 21 # AND4 : 3 # BUF : 4 # GND : 1 # INV : 53 # LUT6 : 4 # OR2 : 5 # OR3 : 9 # OR4 : 5 # OR5 : 2 # VCC : 1 # XNOR2 : 1 # XOR2 : 1 # IO Buffers : 18 # IBUF : 6 # OBUF : 12 Device utilization summary: --------------------------- Selected Device : 6slx16csg324-3 Slice Logic Utilization: Number of Slice LUTs: 57 out of 9112 0% Number used as Logic: 57 out of 9112 0% Slice Logic Distribution: Number of LUT Flip Flop pairs used: 57 Number with an unused Flip Flop: 57 out of 57 100% Number with an unused LUT: 0 out of 57 0% Number of fully used LUT-FF pairs: 0 out of 57 0% Number of unique control sets: 0 IO Utilization: Number of IOs: 18 Number of bonded IOBs: 18 out of 232 7% Specific Feature Utilization: --------------------------- Partition Resource Summary: --------------------------- No Partitions were found in this design. --------------------------- ========================================================================= Timing Report NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE. FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT GENERATED AFTER PLACE-and-ROUTE. Clock Information: ------------------ No clock signals found in this design Asynchronous Control Signals Information: ---------------------------------------- No asynchronous control signals found in this design Timing Summary: --------------- Speed Grade: -3 Minimum period: No path found Minimum input arrival time before clock: No path found Maximum output required time after clock: No path found Maximum combinational path delay: 16.900ns Timing Details: --------------- All values displayed in nanoseconds (ns) ========================================================================= Timing constraint: Default path analysis Total number of paths / destination ports: 1539 / 8 ------------------------------------------------------------------------- Delay: 16.900ns (Levels of Logic = 13) Source: C (PAD) Destination: d_out (PAD) Data Path: C to d_out Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ IBUF:I->O 26 1.222 1.206 C_IBUF (C_IBUF) INV:I->O 1 0.568 0.924 XLXI_2/XLXI_4/XLXI_9 (XLXI_2/XLXI_4/XLXN_15) AND2:I1->O 1 0.223 0.944 XLXI_2/XLXI_4/XLXI_16 (XLXI_2/XLXI_4/XLXN_14) OR2:I0->O 1 0.203 0.944 XLXI_2/XLXI_4/XLXI_14 (XLXI_2/XLXI_4/XLXN_1) AND2:I0->O 1 0.203 0.944 XLXI_2/XLXI_4/XLXI_2 (XLXI_2/XLXI_4/XLXN_4) OR2:I0->O 1 0.203 0.924 XLXI_2/XLXI_4/XLXI_4 (XLXN_37) begin scope: 'XLXI_7:D3' LUT6:I1->O 6 0.203 0.744 Mmux_O11 (O) end scope: 'XLXI_7:O' INV:I->O 9 0.568 1.194 XLXI_9/XLXI_40 (XLXI_9/D_BAR) AND2:I0->O 2 0.203 0.845 XLXI_9/XLXI_48 (XLXI_9/XLXN_125) OR4:I3->O 1 0.339 0.579 XLXI_9/XLXI_52 (XLXI_9/XLXN_156) INV:I->O 1 0.568 0.579 XLXI_9/XLXI_69 (d_out_OBUF) OBUF:I->O 2.571 d_out_OBUF (d_out) ---------------------------------------- Total 16.900ns (7.074ns logic, 9.826ns route) (41.9% logic, 58.1% route) ========================================================================= Cross Clock Domains Report: -------------------------- ========================================================================= Total REAL time to Xst completion: 8.00 secs Total CPU time to Xst completion: 7.36 secs --> Total memory usage is 252544 kilobytes Number of errors : 0 ( 0 filtered) Number of warnings : 2 ( 0 filtered) Number of infos : 0 ( 0 filtered)