Release 13.3 Map O.76xd (nt64) Xilinx Mapping Report File for Design 'ALU' Design Information ------------------ Command Line : map -intstyle ise -p xc6slx16-csg324-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o ALU_map.ncd ALU.ngd ALU.pcf Target Device : xc6slx16 Target Package : csg324 Target Speed : -3 Mapper Version : spartan6 -- $Revision: 1.55 $ Mapped Date : Thu Feb 16 19:52:56 2012 Design Summary -------------- Number of errors: 0 Number of warnings: 0 Slice Logic Utilization: Number of Slice Registers: 0 out of 18,224 0% Number of Slice LUTs: 13 out of 9,112 1% Number used as logic: 13 out of 9,112 1% Number using O6 output only: 13 Number using O5 output only: 0 Number using O5 and O6: 0 Number used as ROM: 0 Number used as Memory: 0 out of 2,176 0% Slice Logic Distribution: Number of occupied Slices: 6 out of 2,278 1% Nummber of MUXCYs used: 0 out of 4,556 0% Number of LUT Flip Flop pairs used: 13 Number with an unused Flip Flop: 13 out of 13 100% Number with an unused LUT: 0 out of 13 0% Number of fully used LUT-FF pairs: 0 out of 13 0% Number of slice register sites lost to control set restrictions: 0 out of 18,224 0% A LUT Flip Flop pair for this architecture represents one LUT paired with one Flip Flop within a slice. A control set is a unique combination of clock, reset, set, and enable signals for a registered element. The Slice Logic Distribution report is not meaningful if the design is over-mapped for a non-slice resource or if Placement fails. IO Utilization: Number of bonded IOBs: 18 out of 232 7% Number of LOCed IOBs: 18 out of 18 100% Specific Feature Utilization: Number of RAMB16BWERs: 0 out of 32 0% Number of RAMB8BWERs: 0 out of 64 0% Number of BUFIO2/BUFIO2_2CLKs: 0 out of 32 0% Number of BUFIO2FB/BUFIO2FB_2CLKs: 0 out of 32 0% Number of BUFG/BUFGMUXs: 0 out of 16 0% Number of DCM/DCM_CLKGENs: 0 out of 4 0% Number of ILOGIC2/ISERDES2s: 0 out of 248 0% Number of IODELAY2/IODRP2/IODRP2_MCBs: 0 out of 248 0% Number of OLOGIC2/OSERDES2s: 0 out of 248 0% Number of BSCANs: 0 out of 4 0% Number of BUFHs: 0 out of 128 0% Number of BUFPLLs: 0 out of 8 0% Number of BUFPLL_MCBs: 0 out of 4 0% Number of DSP48A1s: 0 out of 32 0% Number of ICAPs: 0 out of 1 0% Number of MCBs: 0 out of 2 0% Number of PCILOGICSEs: 0 out of 2 0% Number of PLL_ADVs: 0 out of 2 0% Number of PMVs: 0 out of 1 0% Number of STARTUPs: 0 out of 1 0% Number of SUSPEND_SYNCs: 0 out of 1 0% Average Fanout of Non-Clock Nets: 3.32 Peak Memory Usage: 351 MB Total REAL time to MAP completion: 8 secs Total CPU time to MAP completion: 6 secs Table of Contents ----------------- Section 1 - Errors Section 2 - Warnings Section 3 - Informational Section 4 - Removed Logic Summary Section 5 - Removed Logic Section 6 - IOB Properties Section 7 - RPMs Section 8 - Guide Report Section 9 - Area Group and Partition Summary Section 10 - Timing Report Section 11 - Configuration String Information Section 12 - Control Set Information Section 13 - Utilization by Hierarchy Section 1 - Errors ------------------ Section 2 - Warnings -------------------- Section 3 - Informational ------------------------- INFO:MapLib:562 - No environment variables are currently set. INFO:LIT:244 - All of the single ended outputs in this design are using slew rate limited output drivers. The delay on speed critical single ended outputs can be dramatically reduced by designating them as fast outputs. INFO:Pack:1716 - Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius) INFO:Pack:1720 - Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts) INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report (.mrp). INFO:Pack:1650 - Map created a placed design. Section 4 - Removed Logic Summary --------------------------------- 6 block(s) optimized away Section 5 - Removed Logic ------------------------- Optimized Block(s): TYPE BLOCK VCC XLXI_8 BUF XLXI_9/XLXI_5 BUF XLXI_9/XLXI_6 BUF XLXI_9/XLXI_7 BUF XLXI_9/XLXI_8 GND XST_GND To enable printing of redundant blocks removed and signals merged, set the detailed map report option and rerun map. Section 6 - IOB Properties -------------------------- +---------------------------------------------------------------------------------------------------------------------------------------------------------+ | IOB Name | Type | Direction | IO Standard | Diff | Drive | Slew | Reg (s) | Resistor | IOB | | | | | | Term | Strength | Rate | | | Delay | +---------------------------------------------------------------------------------------------------------------------------------------------------------+ | A | IOB | INPUT | LVCMOS25 | | | | | | | | AN0 | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | | AN1 | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | | AN2 | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | | AN3 | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | | B | IOB | INPUT | LVCMOS25 | | | | | | | | C | IOB | INPUT | LVCMOS25 | | | | | | | | D | IOB | INPUT | LVCMOS25 | | | | | | | | S0 | IOB | INPUT | LVCMOS25 | | | | | | | | S1 | IOB | INPUT | LVCMOS25 | | | | | | | | a_out | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | | b_out | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | | c_out | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | | d_out | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | | e_out | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | | f_out | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | | g_out | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | | sign | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +---------------------------------------------------------------------------------------------------------------------------------------------------------+ Section 7 - RPMs ---------------- Section 8 - Guide Report ------------------------ Guide not run on this design. Section 9 - Area Group and Partition Summary -------------------------------------------- Partition Implementation Status ------------------------------- No Partitions were found in this design. ------------------------------- Area Group Information ---------------------- No area groups were found in this design. ---------------------- Section 10 - Timing Report -------------------------- A logic-level (pre-route) timing report can be generated by using Xilinx static timing analysis tools, Timing Analyzer (GUI) or TRCE (command line), with the mapped NCD and PCF files. Please note that this timing report will be generated using estimated delay information. For accurate numbers, please generate a timing report with the post Place and Route NCD file. For more information about the Timing Analyzer, consult the Xilinx Timing Analyzer Reference Manual; for more information about TRCE, consult the Xilinx Command Line Tools User Guide "TRACE" chapter. Section 11 - Configuration String Details ----------------------------------------- Use the "-detail" map option to print out Configuration Strings Section 12 - Control Set Information ------------------------------------ Use the "-detail" map option to print out Control Set Information. Section 13 - Utilization by Hierarchy ------------------------------------- Use the "-detail" map option to print out the Utilization by Hierarchy section.