////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved.
////////////////////////////////////////////////////////////////////////////////
//   ____  ____ 
//  /   /\/   / 
// /___/  \  /    Vendor: Xilinx 
// \   \   \/     Version : 13.3
//  \   \         Application : sch2hdl
//  /   /         Filename : Divide_1.vf
// /___/   /\     Timestamp : 02/16/2012 18:40:35
// \   \  /  \ 
//  \___\/\___\ 
//
//Command: sch2hdl -intstyle ise -family spartan6 -verilog "X:/My Documents/ec311/ec311-lab1/Divide_1.vf" -w "X:/My Documents/ec311/ec311-lab1/Divide_1.sch"
//Design Name: Divide_1
//Device: spartan6
//Purpose:
//    This verilog netlist is translated from an ECS schematic.It can be 
//    synthesized and simulated, but it should not be modified. 
//
`timescale 1ns / 1ps

module Divide_1(b0, 
                b1, 
                b2, 
                b3, 
                result);

    input b0;
    input b1;
    input b2;
    input b3;
   output result;
   
   wire XLXN_1;
   wire XLXN_2;
   wire XLXN_4;
   wire XLXN_5;
   wire XLXN_8;
   wire XLXN_13;
   wire XLXN_16;
   wire XLXN_17;
   
   AND4  XLXI_1 (.I0(b3), 
                .I1(b1), 
                .I2(XLXN_8), 
                .I3(b0), 
                .O(XLXN_5));
   OR3  XLXI_2 (.I0(XLXN_16), 
               .I1(XLXN_1), 
               .I2(XLXN_13), 
               .O(XLXN_2));
   AND2  XLXI_3 (.I0(XLXN_17), 
                .I1(b1), 
                .O(XLXN_1));
   AND2  XLXI_4 (.I0(XLXN_2), 
                .I1(b2), 
                .O(XLXN_4));
   OR2  XLXI_5 (.I0(XLXN_5), 
               .I1(XLXN_4), 
               .O(result));
   INV  XLXI_6 (.I(b2), 
               .O(XLXN_8));
   INV  XLXI_7 (.I(b3), 
               .O(XLXN_13));
   INV  XLXI_8 (.I(b1), 
               .O(XLXN_16));
   INV  XLXI_9 (.I(b0), 
               .O(XLXN_17));
endmodule