////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved.
////////////////////////////////////////////////////////////////////////////////
//   ____  ____ 
//  /   /\/   / 
// /___/  \  /    Vendor: Xilinx 
// \   \   \/     Version : 13.3
//  \   \         Application : sch2hdl
//  /   /         Filename : Divide_2.vf
// /___/   /\     Timestamp : 02/16/2012 19:28:08
// \   \  /  \ 
//  \___\/\___\ 
//
//Command: sch2hdl -intstyle ise -family spartan6 -verilog "X:/My Documents/ec311/ec311-lab1/Divide_2.vf" -w "X:/My Documents/ec311/ec311-lab1/Divide_2.sch"
//Design Name: Divide_2
//Device: spartan6
//Purpose:
//    This verilog netlist is translated from an ECS schematic.It can be 
//    synthesized and simulated, but it should not be modified. 
//
`timescale 1ns / 1ps

module Divide_2(b0, 
                b1, 
                b2, 
                b3, 
                result);

    input b0;
    input b1;
    input b2;
    input b3;
   output result;
   
   wire XLXN_9;
   wire XLXN_13;
   wire XLXN_14;
   wire XLXN_15;
   
   AND2  XLXI_10 (.I0(XLXN_9), 
                 .I1(b3), 
                 .O(result));
   OR3  XLXI_12 (.I0(XLXN_15), 
                .I1(XLXN_14), 
                .I2(XLXN_13), 
                .O(XLXN_9));
   INV  XLXI_13 (.I(b0), 
                .O(XLXN_13));
   INV  XLXI_15 (.I(b1), 
                .O(XLXN_14));
   INV  XLXI_16 (.I(b2), 
                .O(XLXN_15));
endmodule