//////////////////////////////////////////////////////////////////////////////// // Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. //////////////////////////////////////////////////////////////////////////////// // ____ ____ // / /\/ / // /___/ \ / Vendor: Xilinx // \ \ \/ Version : 13.3 // \ \ Application : sch2hdl // / / Filename : Modulo_1.vf // /___/ /\ Timestamp : 02/16/2012 19:44:03 // \ \ / \ // \___\/\___\ // //Command: sch2hdl -intstyle ise -family spartan6 -verilog "X:/My Documents/ec311/ec311-lab1/Modulo_1.vf" -w "X:/My Documents/ec311/ec311-lab1/Modulo_1.sch" //Design Name: Modulo_1 //Device: spartan6 //Purpose: // This verilog netlist is translated from an ECS schematic.It can be // synthesized and simulated, but it should not be modified. // `timescale 1ns / 1ps module Modulo_1(b0, b1, b2, b3, result); input b0; input b1; input b2; input b3; output result; wire XLXN_2; wire XLXN_3; wire XLXN_5; wire XLXN_6; wire XLXN_7; wire XLXN_23; wire XLXN_24; wire XLXN_50; wire XLXN_51; wire XLXN_54; wire XLXN_55; wire XLXN_56; wire XLXN_57; AND3 XLXI_1 (.I0(b1), .I1(b2), .I2(b3), .O(XLXN_55)); AND3 XLXI_2 (.I0(XLXN_6), .I1(XLXN_5), .I2(b3), .O(XLXN_2)); AND3 XLXI_3 (.I0(b0), .I1(XLXN_7), .I2(b3), .O(XLXN_3)); INV XLXI_5 (.I(b1), .O(XLXN_5)); INV XLXI_6 (.I(b0), .O(XLXN_6)); INV XLXI_7 (.I(b2), .O(XLXN_7)); AND4 XLXI_11 (.I0(b0), .I1(XLXN_24), .I2(b2), .I3(XLXN_23), .O(XLXN_57)); INV XLXI_15 (.I(b3), .O(XLXN_23)); INV XLXI_16 (.I(b1), .O(XLXN_24)); AND4 XLXI_18 (.I0(XLXN_54), .I1(b1), .I2(XLXN_50), .I3(XLXN_51), .O(XLXN_56)); INV XLXI_19 (.I(b2), .O(XLXN_50)); INV XLXI_20 (.I(b3), .O(XLXN_51)); INV XLXI_21 (.I(b0), .O(XLXN_54)); OR5 XLXI_22 (.I0(XLXN_57), .I1(XLXN_56), .I2(XLXN_3), .I3(XLXN_2), .I4(XLXN_55), .O(result)); endmodule