//////////////////////////////////////////////////////////////////////////////// // Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. //////////////////////////////////////////////////////////////////////////////// // ____ ____ // / /\/ / // /___/ \ / Vendor: Xilinx // \ \ \/ Version : 13.3 // \ \ Application : sch2hdl // / / Filename : Modulo_3.vf // /___/ /\ Timestamp : 02/16/2012 18:40:31 // \ \ / \ // \___\/\___\ // //Command: sch2hdl -intstyle ise -family spartan6 -verilog "X:/My Documents/ec311/ec311-lab1/Modulo_3.vf" -w "X:/My Documents/ec311/ec311-lab1/Modulo_3.sch" //Design Name: Modulo_3 //Device: spartan6 //Purpose: // This verilog netlist is translated from an ECS schematic.It can be // synthesized and simulated, but it should not be modified. // `timescale 1ns / 1ps module Modulo_3(b0, b1, b2, b3, result); input b0; input b1; input b2; input b3; output result; wire XLXN_1; wire XLXN_2; wire XLXN_3; wire XLXN_5; wire XLXN_6; wire XLXN_7; AND3 XLXI_1 (.I0(b1), .I1(b2), .I2(b3), .O(XLXN_1)); AND3 XLXI_2 (.I0(XLXN_6), .I1(XLXN_5), .I2(b3), .O(XLXN_2)); AND3 XLXI_3 (.I0(b0), .I1(XLXN_7), .I2(b3), .O(XLXN_3)); OR3 XLXI_4 (.I0(XLXN_3), .I1(XLXN_2), .I2(XLXN_1), .O(result)); INV XLXI_5 (.I(b1), .O(XLXN_5)); INV XLXI_6 (.I(b0), .O(XLXN_6)); INV XLXI_7 (.I(b2), .O(XLXN_7)); endmodule