#----------------------------------------------------------- # PlanAhead v13.3 (64-bit) # Build 147507 by hdbuild on Tue Oct 4 19:13:50 MDT 2011 # Start of session at: Thu Feb 16 18:17:07 2012 # Process ID: 1252 # Log file: X:/My Documents/ec311/ec311-lab1/planAhead_run_1/planAhead.log # Journal file: X:/My Documents/ec311/ec311-lab1/planAhead_run_1/planAhead.jou #----------------------------------------------------------- INFO: [Common-78] Attempting to get a license: PlanAhead INFO: [Common-82] Got a license: PlanAhead INFO: [Device-25] Loading parts and site information from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts\arch.xmlParsing RTL primitives file [C:/Xilinx/13.3/ISE_DS/PlanAhead\parts\xilinx\rtl\prims\rtl_prims.xml] Finished parsing RTL primitives file [C:/Xilinx/13.3/ISE_DS/PlanAhead\parts\xilinx\rtl\prims\rtl_prims.xml] start_gui source {X:/My Documents/ec311/ec311-lab1/pa.fromNetlist.tcl} # create_project -name lab1 -dir "X:/My Documents/ec311/ec311-lab1/planAhead_run_1" -part xc6slx16csg324-3 Parsing template File [C:/Xilinx/13.3/ISE_DS/ISE\data\projnav\templates\verilog.xml]. Finished parsing template File [C:/Xilinx/13.3/ISE_DS/ISE\data\projnav\templates\verilog.xml]. Parsing template File [C:/Xilinx/13.3/ISE_DS/ISE\data\projnav\templates\vhdl.xml]. Finished parsing template File [C:/Xilinx/13.3/ISE_DS/ISE\data\projnav\templates\vhdl.xml]. Parsing template File [C:/Xilinx/13.3/ISE_DS/ISE\data\projnav\templates\ucf.xml]. Finished parsing template File [C:/Xilinx/13.3/ISE_DS/ISE\data\projnav\templates\ucf.xml]. # set_property design_mode GateLvl [get_property srcset [current_run -impl]] # set_property edif_top_file "X:/My Documents/ec311/ec311-lab1/ALU.ngc" [ get_property srcset [ current_run ] ] # add_files -norecurse { {X:/My Documents/ec311/ec311-lab1} } # set_param project.pinAheadLayout yes # set_property target_constrs_file "ALU.ucf" [current_fileset -constrset] Adding file 'X:\My Documents\ec311\ec311-lab1\ALU.ucf' to fileset 'constrs_1' # add_files [list {ALU.ucf}] -fileset [get_property constrset [current_run]] # open_netlist_design Design is defaulting to srcset: sources_1 Design is defaulting to constrset: constrs_1 Design is defaulting to part: xc6slx16csg324-3 Release 13.3 - ngc2edif O.76xd (nt64) Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. Reading design ALU.ngc ... WARNING:NetListWriters:298 - No output is written to ALU.xncf, ignored. Processing design ... Preping design's networks ... Preping design's macros ... finished :Prep Writing EDIF netlist file ALU.edif ... ngc2edif: Total memory usage is 91624 kilobytes Parsing EDIF File [.\planAhead_run_1\lab1.data\cache\ALU_ngc_c04f956c.edif] Finished Parsing EDIF File [.\planAhead_run_1\lab1.data\cache\ALU_ngc_c04f956c.edif] Loading clock regions from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts/xilinx/spartan6/spartan6lx/xc6slx16/ClockRegion.xml Loading clock buffers from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts/xilinx/spartan6/spartan6lx/xc6slx16/ClockBuffers.xml Loading package pin functions from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts\xilinx\spartan6/PinFunctions.xml... Loading package from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts/xilinx/spartan6/spartan6lx/xc6slx16/csg324/Package.xml Loading io standards from C:/Xilinx/13.3/ISE_DS/PlanAhead\./parts/xilinx/spartan6/IOStandards.xml Loading device configuration modes from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts\xilinx\spartan6/ConfigModes.xml Loading list of drcs for the architecture : C:/Xilinx/13.3/ISE_DS/PlanAhead\./parts/xilinx/spartan6/drc.xml Parsing UCF File [X:\My Documents\ec311\ec311-lab1\ALU.ucf] Finished Parsing UCF File [X:\My Documents\ec311\ec311-lab1\ALU.ucf] INFO: [PlanAhead-566] Unisim Transformation Summary: No Unisim elements were transformed.open_netlist_design: Time (s): 13.291w. Memory (MB): 734.672p 186.648g startgroup startgroup set_property loc PAD2 [get_ports A] set_property loc PAD2 [get_ports A] endgroup endgroup startgroup startgroup set_property loc PAD30 [get_ports D] set_property loc PAD30 [get_ports D] endgroup endgroup startgroup startgroup set_property loc PAD29 [get_ports C] set_property loc PAD29 [get_ports C] endgroup endgroup save_design