****** PlanAhead v13.3 (64-bit)
  **** Build 147507 by hdbuild on Tue Oct  4 19:13:50 MDT 2011
    ** Copyright 1986-1999, 2001-2011 Xilinx, Inc. All Rights Reserved.

INFO: [Common-78] Attempting to get a license: PlanAhead
INFO: [Common-82] Got a license: PlanAhead
INFO: [Device-25] Loading parts and site information from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts\arch.xmlParsing RTL primitives file [C:/Xilinx/13.3/ISE_DS/PlanAhead\parts\xilinx\rtl\prims\rtl_prims.xml]
Finished parsing RTL primitives file [C:/Xilinx/13.3/ISE_DS/PlanAhead\parts\xilinx\rtl\prims\rtl_prims.xml]
start_gui
starting gui ...
source {X:/My Documents/ec311/lab1/pa.fromHdl.tcl}
# create_project -name lab1 -dir "X:/My Documents/ec311/lab1/planAhead_run_1" -part xc6slx16csg324-3
Parsing template File [C:/Xilinx/13.3/ISE_DS/ISE\data\projnav\templates\verilog.xml].
Finished parsing template File [C:/Xilinx/13.3/ISE_DS/ISE\data\projnav\templates\verilog.xml].
Parsing template File [C:/Xilinx/13.3/ISE_DS/ISE\data\projnav\templates\vhdl.xml].
Finished parsing template File [C:/Xilinx/13.3/ISE_DS/ISE\data\projnav\templates\vhdl.xml].
Parsing template File [C:/Xilinx/13.3/ISE_DS/ISE\data\projnav\templates\ucf.xml].
Finished parsing template File [C:/Xilinx/13.3/ISE_DS/ISE\data\projnav\templates\ucf.xml].
# set_param project.pinAheadLayout yes
# set srcset [get_property srcset [current_run -impl]]
# set_property top ALU $srcset
# set_property target_constrs_file "ALU.ucf" [current_fileset -constrset]
Adding file 'X:\My Documents\ec311\lab1\ALU.ucf' to fileset 'constrs_1'
# set hdlfile [add_files [list {Negate_3.vf}]]
# set_property file_type Verilog $hdlfile
# set_property library work $hdlfile
# set hdlfile [add_files [list {Negate_2.vf}]]
# set_property file_type Verilog $hdlfile
# set_property library work $hdlfile
# set hdlfile [add_files [list {Negate_1.vf}]]
# set_property file_type Verilog $hdlfile
# set_property library work $hdlfile
# set hdlfile [add_files [list {Negate_0.vf}]]
# set_property file_type Verilog $hdlfile
# set_property library work $hdlfile
# set hdlfile [add_files [list {Modulo_3.vf}]]
# set_property file_type Verilog $hdlfile
# set_property library work $hdlfile
# set hdlfile [add_files [list {Modulo_1.vf}]]
# set_property file_type Verilog $hdlfile
# set_property library work $hdlfile
# set hdlfile [add_files [list {Modulo_0.vf}]]
# set_property file_type Verilog $hdlfile
# set_property library work $hdlfile
# set hdlfile [add_files [list {Divide_3.vf}]]
# set_property file_type Verilog $hdlfile
# set_property library work $hdlfile
# set hdlfile [add_files [list {Divide_2.vf}]]
# set_property file_type Verilog $hdlfile
# set_property library work $hdlfile
# set hdlfile [add_files [list {Divide_1.vf}]]
# set_property file_type Verilog $hdlfile
# set_property library work $hdlfile
# set hdlfile [add_files [list {Divide_0.vf}]]
# set_property file_type Verilog $hdlfile
# set_property library work $hdlfile
# set hdlfile [add_files [list {sev_seg_disp.vf}]]
# set_property file_type Verilog $hdlfile
# set_property library work $hdlfile
# set hdlfile [add_files [list {Negate.vf}]]
# set_property file_type Verilog $hdlfile
# set_property library work $hdlfile
# set hdlfile [add_files [list {Modulo.vf}]]
# set_property file_type Verilog $hdlfile
# set_property library work $hdlfile
# set hdlfile [add_files [list {Divide.vf}]]
# set_property file_type Verilog $hdlfile
# set_property library work $hdlfile
# set hdlfile [add_files [list {ALU.vf}]]
# set_property file_type Verilog $hdlfile
# set_property library work $hdlfile
# add_files [list {ALU.ucf}] -fileset [get_property constrset [current_run]]
# open_rtl_design -part xc6slx16csg324-3
INFO: [PlanAhead-58] Using Verific elaboration
Parsing VHDL file "C:/Xilinx/13.3/ISE_DS/PlanAhead\parts\xilinx\rtl\lib\synplify\synattr.vhd" into library synplify
Analyzing Verilog file "X:\My Documents\ec311\lab1\Negate.vf" into library work
Loading clock regions from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts/xilinx/spartan6/spartan6lx/xc6slx16/ClockRegion.xml
Loading clock buffers from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts/xilinx/spartan6/spartan6lx/xc6slx16/ClockBuffers.xml
Loading package pin functions from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts\xilinx\spartan6/PinFunctions.xml...
Loading package from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts/xilinx/spartan6/spartan6lx/xc6slx16/csg324/Package.xml
Loading io standards from C:/Xilinx/13.3/ISE_DS/PlanAhead\./parts/xilinx/spartan6/IOStandards.xml
Loading device configuration modes from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts\xilinx\spartan6/ConfigModes.xml
Loading list of drcs for the architecture : C:/Xilinx/13.3/ISE_DS/PlanAhead\./parts/xilinx/spartan6/drc.xml
Parsing UCF File [X:\My Documents\ec311\lab1\ALU.ucf]
Finished Parsing UCF File [X:\My Documents\ec311\lab1\ALU.ucf]
INFO: [Designutils-20] Invalid constraints found, use command 'write_ucf -constraints invalid <file>' to save all the invalid constraints to a file
INFO: [PlanAhead-566] Unisim Transformation Summary:
No Unisim elements were transformed.open_rtl_design: Time (s): 13.288w.  Memory (MB): 788.289p 223.703g
exit
stop_gui
INFO: [PlanAhead-261] Exiting PlanAhead...
INFO: [Common-83] Releasing license: PlanAhead