From 0bdf2f0b18f7e2986336f8afc67fe18b8b382e7a Mon Sep 17 00:00:00 2001 From: Michael Abed Date: Thu, 16 Feb 2012 15:46:55 -0500 Subject: initial commit --- ALU.cmd_log | 10 + ALU.spl | 9 + ALU.sym | 22 + ALU.ucf | 0 ALU.v | 38 + ALUSHOW.cmd_log | 1 + ALUSHOW.jhd | 5 + ALUSHOW.lso | 1 + ALUSHOW.prj | 3 + ALUSHOW.sch | 189 +++++ ALUSHOW.syr | 122 +++ ALUSHOW.ucf | 0 ALUSHOW.vf | 286 +++++++ ALUSHOW.xst | 52 ++ ALUSHOW_envsettings.html | 395 ++++++++++ ALUSHOW_summary.html | 84 ++ ALUSHOW_xst.xrpt | 115 +++ ALU_summary.html | 79 ++ _xmsgs/pn_parser.xmsgs | 12 + _xmsgs/xst.xmsgs | 15 + iseconfig/ALU.xreport | 215 ++++++ iseconfig/ALUSHOW.xreport | 215 ++++++ iseconfig/lab2.projectmgr | 106 +++ lab2.gise | 98 +++ lab2.xise | 370 +++++++++ pa.fromHdl.tcl | 19 + planAhead_run_1/planAhead.jou | 12 + planAhead_run_1/planAhead.log | 57 ++ planAhead_run_1/planAhead_run.log | 54 ++ planAhead_run_2/lab2.data/constrs_1/fileset.xml | 25 + planAhead_run_2/lab2.data/sources_1/fileset.xml | 51 ++ planAhead_run_2/lab2.data/wt/webtalk_pa.xml | 30 + planAhead_run_2/lab2.ppr | 13 + sch2HdlBatchFile | 2 + sev_seg_disp.jhd | 1 + sev_seg_disp.sch | 976 ++++++++++++++++++++++++ sev_seg_disp.sym | 57 ++ sev_seg_disp.vf | 236 ++++++ webtalk_pn.xml | 43 ++ 39 files changed, 4018 insertions(+) create mode 100755 ALU.cmd_log create mode 100755 ALU.spl create mode 100644 ALU.sym create mode 100755 ALU.ucf create mode 100755 ALU.v create mode 100755 ALUSHOW.cmd_log create mode 100755 ALUSHOW.jhd create mode 100755 ALUSHOW.lso create mode 100755 ALUSHOW.prj create mode 100755 ALUSHOW.sch create mode 100755 ALUSHOW.syr create mode 100755 ALUSHOW.ucf create mode 100644 ALUSHOW.vf create mode 100755 ALUSHOW.xst create mode 100644 ALUSHOW_envsettings.html create mode 100644 ALUSHOW_summary.html create mode 100755 ALUSHOW_xst.xrpt create mode 100755 ALU_summary.html create mode 100755 _xmsgs/pn_parser.xmsgs create mode 100755 _xmsgs/xst.xmsgs create mode 100755 iseconfig/ALU.xreport create mode 100644 iseconfig/ALUSHOW.xreport create mode 100755 iseconfig/lab2.projectmgr create mode 100755 lab2.gise create mode 100755 lab2.xise create mode 100755 pa.fromHdl.tcl create mode 100644 planAhead_run_1/planAhead.jou create mode 100644 planAhead_run_1/planAhead.log create mode 100644 planAhead_run_1/planAhead_run.log create mode 100644 planAhead_run_2/lab2.data/constrs_1/fileset.xml create mode 100644 planAhead_run_2/lab2.data/sources_1/fileset.xml create mode 100644 planAhead_run_2/lab2.data/wt/webtalk_pa.xml create mode 100644 planAhead_run_2/lab2.ppr create mode 100644 sch2HdlBatchFile create mode 100755 sev_seg_disp.jhd create mode 100755 sev_seg_disp.sch create mode 100755 sev_seg_disp.sym create mode 100644 sev_seg_disp.vf create mode 100755 webtalk_pn.xml diff --git a/ALU.cmd_log b/ALU.cmd_log new file mode 100755 index 0000000..044741b --- /dev/null +++ b/ALU.cmd_log @@ -0,0 +1,10 @@ +vhdtdtfi -lib work {X:/My Documents/ec311/lab2/ALU.v} -lang verilog -prj lab2 -o ALU.spl -module ALU -template C:/Xilinx/13.3/ISE_DS/ISE//data/splveri.tft -deleteonerror +spl2sym -intstyle ise -family spartan6 ALU.spl {X:/My Documents/ec311/lab2/ALU.sym} +vhdtdtfi -lib work {X:/My Documents/ec311/lab2/ALU.v} -lang verilog -prj lab2 -o ALU.spl -module ALU -template C:/Xilinx/13.3/ISE_DS/ISE//data/splveri.tft -deleteonerror +spl2sym -intstyle ise -family spartan6 ALU.spl {X:/My Documents/ec311/lab2/ALU.sym} +vhdtdtfi -lib work /home/michael/Documents/School/EC311/lab2/ALU.v -lang verilog -prj lab2 -o ALU.spl -module ALU -template /home/michael/opt/Xilinx/13.4/ISE_DS/ISE//data/splveri.tft -deleteonerror +spl2sym -intstyle ise -family spartan6 ALU.spl /home/michael/Documents/School/EC311/lab2/ALU.sym +vhdtdtfi -lib work /home/michael/Documents/School/EC311/lab2/ALU.v -lang verilog -prj lab2 -o ALU.spl -module ALU -template /home/michael/opt/Xilinx/13.4/ISE_DS/ISE//data/splveri.tft -deleteonerror +spl2sym -intstyle ise -family spartan6 -w ALU.spl /home/michael/Documents/School/EC311/lab2/ALU.sym +vhdtdtfi -lib work /home/michael/Documents/School/EC311/lab2/ALU.v -lang verilog -prj lab2 -o ALU.spl -module ALU -template /home/michael/opt/Xilinx/13.4/ISE_DS/ISE//data/splveri.tft -deleteonerror +spl2sym -intstyle ise -family spartan6 -w ALU.spl /home/michael/Documents/School/EC311/lab2/ALU.sym diff --git a/ALU.spl b/ALU.spl new file mode 100755 index 0000000..f351b27 --- /dev/null +++ b/ALU.spl @@ -0,0 +1,9 @@ +[Inputs] +=s[1:0]= +=a[3:0]= +[Outputs] +=o[3:0]= +[BiDir] +[ATTRIBUTES] +VeriModel ALU + diff --git a/ALU.sym b/ALU.sym new file mode 100644 index 0000000..47dcf06 --- /dev/null +++ b/ALU.sym @@ -0,0 +1,22 @@ + + + BLOCK + 2012-2-16T2:38:45 + + + + + + + + + + + + + + + + + + diff --git a/ALU.ucf b/ALU.ucf new file mode 100755 index 0000000..e69de29 diff --git a/ALU.v b/ALU.v new file mode 100755 index 0000000..86c0372 --- /dev/null +++ b/ALU.v @@ -0,0 +1,38 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 15:30:47 02/15/2012 +// Design Name: +// Module Name: ALU +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module ALU( + input [1:0] s, + input [3:0] a, + output [3:0] o + ); + +reg [3:0] o; + +always @ ( * ) +begin + case ( s ) + 2'd0 : o = a; + 2'd1 : o = ~a+1; + 2'd2 : o = a >> 1; + 2'd3 : o = a % 3; + endcase +end +endmodule diff --git a/ALUSHOW.cmd_log b/ALUSHOW.cmd_log new file mode 100755 index 0000000..bf0d338 --- /dev/null +++ b/ALUSHOW.cmd_log @@ -0,0 +1 @@ +xst -intstyle ise -ifn "X:/My Documents/ec311/lab2/ALUSHOW.xst" -ofn "X:/My Documents/ec311/lab2/ALUSHOW.syr" diff --git a/ALUSHOW.jhd b/ALUSHOW.jhd new file mode 100755 index 0000000..5a366ed --- /dev/null +++ b/ALUSHOW.jhd @@ -0,0 +1,5 @@ +MODULE ALUSHOW + SUBMODULE sev_seg_disp + INSTANCE XLXI_2 + SUBMODULE ALU + INSTANCE XLXI_4 diff --git a/ALUSHOW.lso b/ALUSHOW.lso new file mode 100755 index 0000000..22de730 --- /dev/null +++ b/ALUSHOW.lso @@ -0,0 +1 @@ +work diff --git a/ALUSHOW.prj b/ALUSHOW.prj new file mode 100755 index 0000000..714802f --- /dev/null +++ b/ALUSHOW.prj @@ -0,0 +1,3 @@ +verilog work "sev_seg_disp.vf" +verilog work "ALU.v" +verilog work "ALUSHOW.vf" diff --git a/ALUSHOW.sch b/ALUSHOW.sch new file mode 100755 index 0000000..ba21753 --- /dev/null +++ b/ALUSHOW.sch @@ -0,0 +1,189 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2012-2-15T18:55:28 + + + + + + + + + + + + + + + + + + + + 2012-2-16T2:38:45 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/ALUSHOW.syr b/ALUSHOW.syr new file mode 100755 index 0000000..f10b0f6 --- /dev/null +++ b/ALUSHOW.syr @@ -0,0 +1,122 @@ +Release 13.3 - xst O.76xd (nt64) +Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. +--> Parameter TMPDIR set to xst/projnav.tmp + + +Total REAL time to Xst completion: 0.00 secs +Total CPU time to Xst completion: 0.11 secs + +--> Parameter xsthdpdir set to xst + + +Total REAL time to Xst completion: 0.00 secs +Total CPU time to Xst completion: 0.12 secs + +--> Reading design: ALUSHOW.prj + +TABLE OF CONTENTS + 1) Synthesis Options Summary + 2) HDL Parsing + 3) HDL Elaboration + 4) HDL Synthesis + 4.1) HDL Synthesis Report + 5) Advanced HDL Synthesis + 5.1) Advanced HDL Synthesis Report + 6) Low Level Synthesis + 7) Partition Report + 8) Design Summary + 8.1) Primitive and Black Box Usage + 8.2) Device utilization summary + 8.3) Partition Resource Summary + 8.4) Timing Report + 8.4.1) Clock Information + 8.4.2) Asynchronous Control Signals Information + 8.4.3) Timing Summary + 8.4.4) Timing Details + 8.4.5) Cross Clock Domains Report + + +========================================================================= +* Synthesis Options Summary * +========================================================================= +---- Source Parameters +Input File Name : "ALUSHOW.prj" +Ignore Synthesis Constraint File : NO + +---- Target Parameters +Output File Name : "ALUSHOW" +Output Format : NGC +Target Device : xc6slx16-3-csg324 + +---- Source Options +Top Module Name : ALUSHOW +Automatic FSM Extraction : YES +FSM Encoding Algorithm : Auto +Safe Implementation : No +FSM Style : LUT +RAM Extraction : Yes +RAM Style : Auto +ROM Extraction : Yes +Shift Register Extraction : YES +ROM Style : Auto +Resource Sharing : YES +Asynchronous To Synchronous : NO +Shift Register Minimum Size : 2 +Use DSP Block : Auto +Automatic Register Balancing : No + +---- Target Options +LUT Combining : Auto +Reduce Control Sets : Auto +Add IO Buffers : YES +Global Maximum Fanout : 100000 +Add Generic Clock Buffer(BUFG) : 16 +Register Duplication : YES +Optimize Instantiated Primitives : NO +Use Clock Enable : Auto +Use Synchronous Set : Auto +Use Synchronous Reset : Auto +Pack IO Registers into IOBs : Auto +Equivalent register Removal : YES + +---- General Options +Optimization Goal : Speed +Optimization Effort : 1 +Power Reduction : NO +Keep Hierarchy : No +Netlist Hierarchy : As_Optimized +RTL Output : Yes +Global Optimization : AllClockNets +Read Cores : YES +Write Timing Constraints : NO +Cross Clock Analysis : NO +Hierarchy Separator : / +Bus Delimiter : <> +Case Specifier : Maintain +Slice Utilization Ratio : 100 +BRAM Utilization Ratio : 100 +DSP48 Utilization Ratio : 100 +Auto BRAM Packing : NO +Slice Utilization Ratio Delta : 5 + +========================================================================= + + +========================================================================= +* HDL Parsing * +========================================================================= +Analyzing Verilog file "\\ad\eng\users\m\g\mgabed\My Documents\ec311\lab2\sev_seg_disp.vf" into library work +Parsing module . +Analyzing Verilog file "\\ad\eng\users\m\g\mgabed\My Documents\ec311\lab2\ALU.v" into library work +Parsing module . +ERROR:HDLCompiler:44 - "\\ad\eng\users\m\g\mgabed\My Documents\ec311\lab2\ALU.v" Line 26: out3 is not a constant +ERROR:HDLCompiler:598 - "\\ad\eng\users\m\g\mgabed\My Documents\ec311\lab2\ALU.v" Line 21: Module ignored due to previous errors. +Verilog file \\ad\eng\users\m\g\mgabed\My Documents\ec311\lab2\ALU.v ignored due to errors +--> + +Total memory usage is 201016 kilobytes + +Number of errors : 2 ( 0 filtered) +Number of warnings : 0 ( 0 filtered) +Number of infos : 0 ( 0 filtered) + diff --git a/ALUSHOW.ucf b/ALUSHOW.ucf new file mode 100755 index 0000000..e69de29 diff --git a/ALUSHOW.vf b/ALUSHOW.vf new file mode 100644 index 0000000..8662af8 --- /dev/null +++ b/ALUSHOW.vf @@ -0,0 +1,286 @@ +//////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. +//////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version : 13.4 +// \ \ Application : sch2hdl +// / / Filename : ALUSHOW.vf +// /___/ /\ Timestamp : 02/15/2012 21:35:26 +// \ \ / \ +// \___\/\___\ +// +//Command: sch2hdl -intstyle ise -family spartan6 -verilog /home/michael/Documents/School/EC311/lab2/ALUSHOW.vf -w /home/michael/Documents/School/EC311/lab2/ALUSHOW.sch +//Design Name: ALUSHOW +//Device: spartan6 +//Purpose: +// This verilog netlist is translated from an ECS schematic.It can be +// synthesized and simulated, but it should not be modified. +// +`timescale 1ns / 1ps + +module sev_seg_disp_MUSER_ALUSHOW(A, + B, + C, + D, + AN0, + AN1, + AN2, + AN3, + a_out, + b_out, + c_out, + d_out, + e_out, + f_out, + g_out, + sign); + + input A; + input B; + input C; + input D; + output AN0; + output AN1; + output AN2; + output AN3; + output a_out; + output b_out; + output c_out; + output d_out; + output e_out; + output f_out; + output g_out; + output sign; + + wire A_BAR; + wire B_BAR; + wire C_BAR; + wire D_BAR; + wire XLXN_14; + wire XLXN_24; + wire XLXN_61; + wire XLXN_62; + wire XLXN_63; + wire XLXN_64; + wire XLXN_65; + wire XLXN_91; + wire XLXN_92; + wire XLXN_93; + wire XLXN_94; + wire XLXN_105; + wire XLXN_113; + wire XLXN_114; + wire XLXN_125; + wire XLXN_126; + wire XLXN_128; + wire XLXN_129; + wire XLXN_130; + wire XLXN_131; + wire XLXN_145; + wire XLXN_146; + wire XLXN_147; + wire XLXN_148; + wire XLXN_149; + wire XLXN_151; + wire XLXN_155; + wire XLXN_156; + wire XLXN_158; + wire XLXN_160; + wire XLXN_162; + wire XLXN_165; + + BUF XLXI_5 (.I(XLXN_14), + .O(AN0)); + BUF XLXI_6 (.I(XLXN_14), + .O(AN1)); + BUF XLXI_7 (.I(XLXN_14), + .O(AN2)); + BUF XLXI_8 (.I(XLXN_24), + .O(AN3)); + GND XLXI_11 (.G(XLXN_24)); + VCC XLXI_12 (.P(XLXN_14)); + AND3 XLXI_30 (.I0(B), + .I1(C_BAR), + .I2(D), + .O(XLXN_61)); + AND3 XLXI_31 (.I0(A_BAR), + .I1(D), + .I2(C), + .O(XLXN_62)); + AND2 XLXI_32 (.I0(B_BAR), + .I1(D_BAR), + .O(XLXN_63)); + AND2 XLXI_33 (.I0(C), + .I1(D_BAR), + .O(XLXN_64)); + OR5 XLXI_34 (.I0(XLXN_65), + .I1(XLXN_64), + .I2(XLXN_63), + .I3(XLXN_62), + .I4(XLXN_61), + .O(XLXN_149)); + AND2 XLXI_35 (.I0(B_BAR), + .I1(A), + .O(XLXN_65)); + INV XLXI_37 (.I(A), + .O(A_BAR)); + INV XLXI_38 (.I(B), + .O(B_BAR)); + INV XLXI_39 (.I(C), + .O(C_BAR)); + INV XLXI_40 (.I(D), + .O(D_BAR)); + OR4 XLXI_41 (.I0(XLXN_94), + .I1(XLXN_93), + .I2(XLXN_92), + .I3(XLXN_91), + .O(XLXN_151)); + XNOR2 XLXI_42 (.I0(B), + .I1(A), + .O(XLXN_91)); + AND2 XLXI_43 (.I0(D_BAR), + .I1(C_BAR), + .O(XLXN_92)); + AND2 XLXI_44 (.I0(B_BAR), + .I1(C_BAR), + .O(XLXN_93)); + AND3 XLXI_45 (.I0(A_BAR), + .I1(D), + .I2(C), + .O(XLXN_94)); + XOR2 XLXI_46 (.I0(B), + .I1(A), + .O(XLXN_105)); + OR3 XLXI_47 (.I0(D), + .I1(C_BAR), + .I2(XLXN_105), + .O(XLXN_155)); + AND2 XLXI_48 (.I0(D_BAR), + .I1(C), + .O(XLXN_125)); + AND2 XLXI_49 (.I0(D_BAR), + .I1(B_BAR), + .O(XLXN_126)); + AND2 XLXI_50 (.I0(C), + .I1(B_BAR), + .O(XLXN_113)); + AND3 XLXI_51 (.I0(C_BAR), + .I1(D), + .I2(B), + .O(XLXN_114)); + OR4 XLXI_52 (.I0(XLXN_114), + .I1(XLXN_113), + .I2(XLXN_126), + .I3(XLXN_125), + .O(XLXN_156)); + OR2 XLXI_53 (.I0(XLXN_126), + .I1(XLXN_125), + .O(XLXN_158)); + AND3 XLXI_54 (.I0(C_BAR), + .I1(B), + .I2(A_BAR), + .O(XLXN_128)); + AND3 XLXI_55 (.I0(C), + .I1(B_BAR), + .I2(A), + .O(XLXN_129)); + AND3 XLXI_56 (.I0(D_BAR), + .I1(B), + .I2(A_BAR), + .O(XLXN_130)); + AND2 XLXI_57 (.I0(D_BAR), + .I1(C_BAR), + .O(XLXN_131)); + OR4 XLXI_58 (.I0(XLXN_131), + .I1(XLXN_130), + .I2(XLXN_129), + .I3(XLXN_128), + .O(XLXN_160)); + OR4 XLXI_60 (.I0(XLXN_148), + .I1(XLXN_147), + .I2(XLXN_146), + .I3(XLXN_145), + .O(XLXN_162)); + AND2 XLXI_61 (.I0(C_BAR), + .I1(B), + .O(XLXN_145)); + AND2 XLXI_62 (.I0(D_BAR), + .I1(C), + .O(XLXN_146)); + AND2 XLXI_63 (.I0(B_BAR), + .I1(C), + .O(XLXN_147)); + AND2 XLXI_64 (.I0(D_BAR), + .I1(A), + .O(XLXN_148)); + INV XLXI_65 (.I(XLXN_149), + .O(a_out)); + INV XLXI_66 (.I(XLXN_151), + .O(b_out)); + INV XLXI_67 (.I(XLXN_155), + .O(c_out)); + INV XLXI_68 (.I(XLXN_158), + .O(e_out)); + INV XLXI_69 (.I(XLXN_156), + .O(d_out)); + INV XLXI_70 (.I(XLXN_160), + .O(f_out)); + INV XLXI_71 (.I(XLXN_162), + .O(g_out)); + INV XLXI_72 (.I(A_BAR), + .O(XLXN_165)); + INV XLXI_73 (.I(XLXN_165), + .O(sign)); +endmodule +`timescale 1ns / 1ps + +module ALUSHOW(AN0, + AN1, + AN2, + AN3, + ao, + bo, + co, + do, + eo, + fo, + go, + sign); + + output AN0; + output AN1; + output AN2; + output AN3; + output ao; + output bo; + output co; + output do; + output eo; + output fo; + output go; + output sign; + + wire [3:0] ALU_OUT; + + sev_seg_disp_MUSER_ALUSHOW XLXI_2 (.A(ALU_OUT[0]), + .B(ALU_OUT[1]), + .C(ALU_OUT[2]), + .D(ALU_OUT[3]), + .AN0(AN0), + .AN1(AN1), + .AN2(AN2), + .AN3(AN3), + .a_out(ao), + .b_out(bo), + .c_out(co), + .d_out(do), + .e_out(eo), + .f_out(fo), + .g_out(go), + .sign(sign)); + ALU XLXI_4 (.a(), + .s(), + .o(ALU_OUT[3:0])); +endmodule diff --git a/ALUSHOW.xst b/ALUSHOW.xst new file mode 100755 index 0000000..bc4d1a5 --- /dev/null +++ b/ALUSHOW.xst @@ -0,0 +1,52 @@ +set -tmpdir "xst/projnav.tmp" +set -xsthdpdir "xst" +run +-ifn ALUSHOW.prj +-ofn ALUSHOW +-ofmt NGC +-p xc6slx16-3-csg324 +-top ALUSHOW +-opt_mode Speed +-opt_level 1 +-power NO +-iuc NO +-keep_hierarchy No +-netlist_hierarchy As_Optimized +-rtlview Yes +-glob_opt AllClockNets +-read_cores YES +-write_timing_constraints NO +-cross_clock_analysis NO +-hierarchy_separator / +-bus_delimiter <> +-case Maintain +-slice_utilization_ratio 100 +-bram_utilization_ratio 100 +-dsp_utilization_ratio 100 +-lc Auto +-reduce_control_sets Auto +-fsm_extract YES -fsm_encoding Auto +-safe_implementation No +-fsm_style LUT +-ram_extract Yes +-ram_style Auto +-rom_extract Yes +-shreg_extract YES +-rom_style Auto +-auto_bram_packing NO +-resource_sharing YES +-async_to_sync NO +-shreg_min_size 2 +-use_dsp48 Auto +-iobuf YES +-max_fanout 100000 +-bufg 16 +-register_duplication YES +-register_balancing No +-optimize_primitives NO +-use_clock_enable Auto +-use_sync_set Auto +-use_sync_reset Auto +-iob Auto +-equivalent_register_removal YES +-slice_utilization_ratio_maxmargin 5 diff --git a/ALUSHOW_envsettings.html b/ALUSHOW_envsettings.html new file mode 100644 index 0000000..2c8f42b --- /dev/null +++ b/ALUSHOW_envsettings.html @@ -0,0 +1,395 @@ +Xilinx System Settings Report + +
System Settings

+ + 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Environment Settings
Environment Variablexstngdbuildmappar
PATHC:
\Xilinx\13.3\ISE_DS\ISE\\lib\nt64;C:
\Xilinx\13.3\ISE_DS\ISE\\bin\nt64;C:
\Xilinx\13.3\ISE_DS\PlanAhead\bin;C:
\Xilinx\13.3\ISE_DS\ISE\bin\nt64;C:
\Xilinx\13.3\ISE_DS\ISE\lib\nt64;C:
\Xilinx\13.3\ISE_DS\EDK\bin\nt64;C:
\Xilinx\13.3\ISE_DS\EDK\lib\nt64;C:
\Xilinx\13.3\ISE_DS\EDK\gnu\microblaze\nt64\bin;C:
\Xilinx\13.3\ISE_DS\EDK\gnu\powerpc-eabi\nt64\bin;C:
\Xilinx\13.3\ISE_DS\EDK\gnuwin\bin;C:
\Xilinx\13.3\ISE_DS\common\bin\nt64;C:
\Xilinx\13.3\ISE_DS\common\lib\nt64;C:
\Windows\system32;C:
\Windows;C:
\Windows\System32\Wbem;C:
\Windows\System32\WindowsPowerShell\v1.0\;C:
\Program Files\MATLAB\R2011a\runtime\win64;C:
\Program Files\MATLAB\R2011a\bin;C:
\VXIPNP\WinNT\Bin;C:
\Program Files (x86)\Altium Designer Summer 09\System;C:
\Program Files (x86)\QuickTime\QTSystem\;C:
\Program Files\NetBeans 7.0.1\java\ant\bin;C:
\Program Files\Java\jdk1.6.0_27\bin;C:
\Program Files\TortoiseSVN\bin;C:
\Program Files (x86)\Rational\Rose RealTime\bin\win32;C:
\Program Files (x86)\Rational\common;C:
\Cadence\SPB_16.5\OpenAccess\bin\win32\opt;C:
\Cadence\SPB_16.5\tools\Capture;C:
\Cadence\SPB_16.5\tools\PSpice\Library;C:
\Cadence\SPB_16.5\tools\PSpice;C:
\Cadence\SPB_16.5\tools\specctra\bin;C:
\Cadence\SPB_16.5\tools\fet\bin;C:
\Cadence\SPB_16.5\tools\libutil\bin;C:
\Cadence\SPB_16.5\tools\bin;C:
\Cadence\SPB_16.5\tools\pcb\bin		< data not available >< data not available >< data not available >
PATHEXT.COM;.EXE;.BAT;.CMD;.VBS;.VBE;.JS;.JSE;.WSF;.WSH;.MSC< data not available >< data not available >< data not available >
XILINXC:
\Xilinx\13.3\ISE_DS\ISE\		< data not available >< data not available >< data not available >
XILINXD_LICENSE_FILE2100@XilinxLM.bu.edu< data not available >< data not available >< data not available >
XILINX_DSPC:
\Xilinx\13.3\ISE_DS\ISE		< data not available >< data not available >< data not available >
XILINX_EDKC:
\Xilinx\13.3\ISE_DS\EDK		< data not available >< data not available >< data not available >
XILINX_PLANAHEADC:
\Xilinx\13.3\ISE_DS\PlanAhead		< data not available >< data not available >< data not available >
+ + 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Synthesis Property Settings
Switch NameProperty NameValueDefault Value
-ifn ALUSHOW.prj 
-ofn ALUSHOW 
-ofmt NGCNGC
-p xc6slx16-3-csg324 
-top ALUSHOW 
-opt_modeOptimization GoalSpeedSpeed
-opt_levelOptimization Effort11
-powerPower ReductionNONo
-iucUse synthesis Constraints FileNONo
-keep_hierarchyKeep HierarchyNoNo
-netlist_hierarchyNetlist HierarchyAs_OptimizedAs_Optimized
-rtlviewGenerate RTL SchematicYesNo
-glob_optGlobal Optimization GoalAllClockNetsAllClockNets
-read_coresRead CoresYESYes
-write_timing_constraintsWrite Timing ConstraintsNONo
-cross_clock_analysisCross Clock AnalysisNONo
-bus_delimiterBus Delimiter<><>
-slice_utilization_ratioSlice Utilization Ratio100100
-bram_utilization_ratioBRAM Utilization Ratio100100
-dsp_utilization_ratioDSP Utilization Ratio100100
-reduce_control_sets AutoAuto
-fsm_extract YESYes
-fsm_encoding AutoAuto
-safe_implementation NoNo
-fsm_style LUTLUT
-ram_extract YesYes
-ram_style AutoAuto
-rom_extract YesYes
-shreg_extract YESYes
-rom_style AutoAuto
-auto_bram_packing NONo
-resource_sharing YESYes
-async_to_sync NONo
-use_dsp48 AutoAuto
-iobuf YESYes
-max_fanout 100000100000
-bufg 1616
-register_duplication YESYes
-register_balancing NoNo
-optimize_primitives NONo
-use_clock_enable AutoAuto
-use_sync_set AutoAuto
-use_sync_reset AutoAuto
-iob AutoAuto
-equivalent_register_removal YESYes
-slice_utilization_ratio_maxmargin 50
+ + 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Operating System Information
Operating System Informationxstngdbuildmappar
CPU Architecture/SpeedIntel(R) Core(TM)2 Duo CPU E8200 @ 2.66GHz/2660 MHz<  data not available  ><  data not available  ><  data not available  >
HostECE-PHO115-09<  data not available  ><  data not available  ><  data not available  >
OS NameMicrosoft Windows 7 , 64-bit<  data not available  ><  data not available  ><  data not available  >
OS ReleaseService Pack 1 (build 7601)<  data not available  ><  data not available  ><  data not available  >
+ \ No newline at end of file diff --git a/ALUSHOW_summary.html b/ALUSHOW_summary.html new file mode 100644 index 0000000..56bb337 --- /dev/null +++ b/ALUSHOW_summary.html @@ -0,0 +1,84 @@ +Xilinx Design Summary + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
ALUSHOW Project Status (02/15/2012 - 21:35:26)
Project File:lab2.xiseParser Errors: No Errors
Module Name:ALUSHOWImplementation State:Synthesized
Target Device:xc6slx16-3csg324
  • Errors:
 +X +2 Errors (2 new)
Product Version:ISE 13.4
  • Warnings:
No Warnings
Design Goal:Balanced
  • Routing Results:
 + 
Design Strategy:Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment: + +System Settings +
  • Final Timing Score:
  
+ + + + + + + + + + + + 
+ + + + + + + + + + +
Detailed Reports [-]
Report NameStatusGeneratedErrorsWarningsInfos
Synthesis ReportCurrentWed Feb 15 20:30:08 2012X 2 Errors (2 new)00
Translation Report     
Map Report     
Place and Route Report     
Power Report     
Post-PAR Static Timing Report     
Bitgen Report     
+ 
+ + +
Secondary Reports [-]
Report NameStatusGenerated
+ + +
Date Generated: 02/15/2012 - 21:38:21
+ \ No newline at end of file diff --git a/ALUSHOW_xst.xrpt b/ALUSHOW_xst.xrpt new file mode 100755 index 0000000..ef3c0f8 --- /dev/null +++ b/ALUSHOW_xst.xrpt @@ -0,0 +1,115 @@ + + + + + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + + + + + + + + + + + +
+
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+
+ + + +
+ + + diff --git a/ALU_summary.html b/ALU_summary.html new file mode 100755 index 0000000..4ca0738 --- /dev/null +++ b/ALU_summary.html @@ -0,0 +1,79 @@ +Xilinx Design Summary + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
ALU Project Status
Project File:lab2.xiseParser Errors: No Errors
Module Name:ALUImplementation State:New (Failed)
Target Device:xc6slx16-3csg324
  • Errors:
 
Product Version:ISE 13.3
  • Warnings:
 
Design Goal:Balanced
  • Routing Results:
 + 
Design Strategy:Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment: 
  • Final Timing Score:
  
+ + + + + + + + + + + + 
+ + + + + + + + + + +
Detailed Reports [-]
Report NameStatusGeneratedErrorsWarningsInfos
Synthesis Report     
Translation Report     
Map Report     
Place and Route Report     
Power Report     
Post-PAR Static Timing Report     
Bitgen Report     
+ 
+ + +
Secondary Reports [-]
Report NameStatusGenerated
+ + +
Date Generated: 02/15/2012 - 16:06:19
+ \ No newline at end of file diff --git a/_xmsgs/pn_parser.xmsgs b/_xmsgs/pn_parser.xmsgs new file mode 100755 index 0000000..2211003 --- /dev/null +++ b/_xmsgs/pn_parser.xmsgs @@ -0,0 +1,12 @@ + + + + + + + + + + + + diff --git a/_xmsgs/xst.xmsgs b/_xmsgs/xst.xmsgs new file mode 100755 index 0000000..8233bd5 --- /dev/null +++ b/_xmsgs/xst.xmsgs @@ -0,0 +1,15 @@ + + + +"\\ad\eng\users\m\g\mgabed\My Documents\ec311\lab2\ALU.v" Line 26: out3 is not a constant + + +"\\ad\eng\users\m\g\mgabed\My Documents\ec311\lab2\ALU.v" Line 21: Module <ALU> ignored due to previous errors. + + + + diff --git a/iseconfig/ALU.xreport b/iseconfig/ALU.xreport new file mode 100755 index 0000000..9524671 --- /dev/null +++ b/iseconfig/ALU.xreport @@ -0,0 +1,215 @@ + + +
+ 2012-02-15T15:36:44 + ALU + Unknown + X:/My Documents/ec311/lab2/iseconfig/ALU.xreport + X:/My Documents/ec311/lab2 + 2012-02-15T15:30:47 + false +
+ + + + + + + + + + + + + + + + + + + + + + + + diff --git a/iseconfig/ALUSHOW.xreport b/iseconfig/ALUSHOW.xreport new file mode 100644 index 0000000..4332a20 --- /dev/null +++ b/iseconfig/ALUSHOW.xreport @@ -0,0 +1,215 @@ + + +
+ 2012-02-15T21:38:21 + ALUSHOW + 2012-02-15T21:35:26 + /home/michael/Documents/School/EC311/lab2/iseconfig/ALUSHOW.xreport + /home/michael/Documents/School/EC311/lab2 + 2012-02-15T21:18:06 + false +
+ + + + + + + + + + + + + + + + + + + + + + + + diff --git a/iseconfig/lab2.projectmgr b/iseconfig/lab2.projectmgr new file mode 100755 index 0000000..c48c152 --- /dev/null +++ b/iseconfig/lab2.projectmgr @@ -0,0 +1,106 @@ + + + + + + + + + 2 + + + ALUSHOW (/home/michael/Documents/School/EC311/lab2/ALUSHOW.sch) + + 0 + 0 + 000000ff00000000000000010000000100000000000000000000000000000000020200000001000000010000006400000150000000020000000000000000000000000200000064ffffffff000000810000000300000002000001500000000100000003000000000000000100000003 + true + ALUSHOW (/home/michael/Documents/School/EC311/lab2/ALUSHOW.sch) + + + + 1 + Design Utilities + + + Design Utilities + + 0 + 0 + 000000ff00000000000000010000000100000000000000000000000000000000000000000000000132000000010000000100000000000000000000000064ffffffff000000810000000000000001000001320000000100000000 + false + Design Utilities + + + + 1 + + + 0 + 0 + 000000ff00000000000000010000000000000000010000000000000000000000000000000000000287000000040101000100000000000000000000000064ffffffff000000810000000000000004000000420000000100000000000000240000000100000000000000660000000100000000000001bb0000000100000000 + false + ALU.v + + + + 1 + work + + + 0 + 0 + 000000ff00000000000000010000000000000000010000000000000000000000000000000000000117000000010001000100000000000000000000000064ffffffff000000810000000000000001000001170000000100000000 + false + work + + + + 1 + Configure Target Device + Implement Design + Synthesize - XST + User Constraints + + + Create Schematic Symbol + + 0 + 0 + 000000ff00000000000000010000000100000000000000000000000000000000000000000000000183000000010000000100000000000000000000000064ffffffff000000810000000000000001000001830000000100000000 + false + Create Schematic Symbol + + + + 1 + + + + + 0 + 0 + 000000ff00000000000000010000000100000000000000000000000000000000000000000000000183000000010000000100000000000000000000000064ffffffff000000810000000000000001000001830000000100000000 + false + + + + + 1 + Configure Target Device + Design Utilities + Implement Design + Synthesize - XST + + + + + 0 + 0 + 000000ff00000000000000010000000100000000000000000000000000000000000000000000000183000000010000000100000000000000000000000064ffffffff000000810000000000000001000001830000000100000000 + false + + + 000000ff00000000000000020000011b0000011b01000000050100000002 + Implementation + diff --git a/lab2.gise b/lab2.gise new file mode 100755 index 0000000..ec644a8 --- /dev/null +++ b/lab2.gise @@ -0,0 +1,98 @@ + + + + + + + + + + + + + + + + + + + + 11.1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/lab2.xise b/lab2.xise new file mode 100755 index 0000000..c5e520e --- /dev/null +++ b/lab2.xise @@ -0,0 +1,370 @@ + + + +
+ + + + + + + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/pa.fromHdl.tcl b/pa.fromHdl.tcl new file mode 100755 index 0000000..2112f38 --- /dev/null +++ b/pa.fromHdl.tcl @@ -0,0 +1,19 @@ + +# PlanAhead Launch Script for Pre-Synthesis Floorplanning, created by Project Navigator + +create_project -name lab2 -dir "/home/michael/Documents/School/EC311/lab2/planAhead_run_2" -part xc6slx16csg324-3 +set_param project.pinAheadLayout yes +set srcset [get_property srcset [current_run -impl]] +set_property target_constrs_file "ALUSHOW.ucf" [current_fileset -constrset] +set hdlfile [add_files [list {sev_seg_disp.vf}]] +set_property file_type Verilog $hdlfile +set_property library work $hdlfile +set hdlfile [add_files [list {ALU.v}]] +set_property file_type Verilog $hdlfile +set_property library work $hdlfile +set hdlfile [add_files [list {ALUSHOW.vf}]] +set_property file_type Verilog $hdlfile +set_property library work $hdlfile +set_property top ALUSHOW $srcset +add_files [list {ALUSHOW.ucf}] -fileset [get_property constrset [current_run]] +open_rtl_design -part xc6slx16csg324-3 diff --git a/planAhead_run_1/planAhead.jou b/planAhead_run_1/planAhead.jou new file mode 100644 index 0000000..f233ed4 --- /dev/null +++ b/planAhead_run_1/planAhead.jou @@ -0,0 +1,12 @@ +#----------------------------------------------------------- +# PlanAhead v13.4 (64-bit) +# Build 157570 by hdbuild on Fri Dec 16 12:49:33 MST 2011 +# Start of session at: Wed Feb 15 21:35:38 2012 +# Process ID: 29568 +# Log file: /home/michael/Documents/School/EC311/lab2/planAhead_run_1/planAhead.log +# Journal file: /home/michael/Documents/School/EC311/lab2/planAhead_run_1/planAhead.jou +#----------------------------------------------------------- +start_gui +source /home/michael/Documents/School/EC311/lab2/pa.fromHdl.tcl +exit +stop_gui diff --git a/planAhead_run_1/planAhead.log b/planAhead_run_1/planAhead.log new file mode 100644 index 0000000..469ec29 --- /dev/null +++ b/planAhead_run_1/planAhead.log @@ -0,0 +1,57 @@ +#----------------------------------------------------------- +# PlanAhead v13.4 (64-bit) +# Build 157570 by hdbuild on Fri Dec 16 12:49:33 MST 2011 +# Start of session at: Wed Feb 15 21:35:38 2012 +# Process ID: 29568 +# Log file: /home/michael/Documents/School/EC311/lab2/planAhead_run_1/planAhead.log +# Journal file: /home/michael/Documents/School/EC311/lab2/planAhead_run_1/planAhead.jou +#----------------------------------------------------------- +INFO: [Common-78] Attempting to get a license: PlanAhead +INFO: [Common-82] Got a license: PlanAhead +INFO: [Device-25] Loading parts and site information from /home/michael/opt/Xilinx/13.4/ISE_DS/PlanAhead/parts/arch.xmlParsing RTL primitives file [/home/michael/opt/Xilinx/13.4/ISE_DS/PlanAhead/parts/xilinx/rtl/prims/rtl_prims.xml] +Finished parsing RTL primitives file [/home/michael/opt/Xilinx/13.4/ISE_DS/PlanAhead/parts/xilinx/rtl/prims/rtl_prims.xml] +start_gui +source /home/michael/Documents/School/EC311/lab2/pa.fromHdl.tcl +# create_project -name lab2 -dir "/home/michael/Documents/School/EC311/lab2/planAhead_run_2" -part xc6slx16csg324-3 +Parsing template File [/home/michael/opt/Xilinx/13.4/ISE_DS/ISE/data/projnav/templates/verilog.xml]. +Finished parsing template File [/home/michael/opt/Xilinx/13.4/ISE_DS/ISE/data/projnav/templates/verilog.xml]. +Parsing template File [/home/michael/opt/Xilinx/13.4/ISE_DS/ISE/data/projnav/templates/vhdl.xml]. +Finished parsing template File [/home/michael/opt/Xilinx/13.4/ISE_DS/ISE/data/projnav/templates/vhdl.xml]. +Parsing template File [/home/michael/opt/Xilinx/13.4/ISE_DS/ISE/data/projnav/templates/ucf.xml]. +Finished parsing template File [/home/michael/opt/Xilinx/13.4/ISE_DS/ISE/data/projnav/templates/ucf.xml]. +# set_param project.pinAheadLayout yes +# set srcset [get_property srcset [current_run -impl]] +# set_property target_constrs_file "ALUSHOW.ucf" [current_fileset -constrset] +Adding file '/home/michael/Documents/School/EC311/lab2/ALUSHOW.ucf' to fileset 'constrs_1' +# set hdlfile [add_files [list {sev_seg_disp.vf}]] +# set_property file_type Verilog $hdlfile +# set_property library work $hdlfile +# set hdlfile [add_files [list {ALU.v}]] +# set_property file_type Verilog $hdlfile +# set_property library work $hdlfile +# set hdlfile [add_files [list {ALUSHOW.vf}]] +# set_property file_type Verilog $hdlfile +# set_property library work $hdlfile +# set_property top ALUSHOW $srcset +# add_files [list {ALUSHOW.ucf}] -fileset [get_property constrset [current_run]] +# open_rtl_design -part xc6slx16csg324-3 +INFO: [PlanAhead-58] Using Verific elaboration +Parsing VHDL file "/home/michael/opt/Xilinx/13.4/ISE_DS/PlanAhead/parts/xilinx/rtl/lib/synplify/synattr.vhd" into library synplify +Analyzing Verilog file "/home/michael/Documents/School/EC311/lab2/ALU.v" into library work +Analyzing Verilog file "/home/michael/Documents/School/EC311/lab2/ALUSHOW.vf" into library work +CRITICAL WARNING: [EDIF-96] Could not resolve non-primitive black box cell 'ALU' defined in file 'ALU.v' instantiated as 'XLXI_4'. +Loading clock regions from /home/michael/opt/Xilinx/13.4/ISE_DS/PlanAhead/parts/xilinx/spartan6/spartan6lx/xc6slx16/ClockRegion.xml +Loading clock buffers from /home/michael/opt/Xilinx/13.4/ISE_DS/PlanAhead/parts/xilinx/spartan6/spartan6lx/xc6slx16/ClockBuffers.xml +Loading package pin functions from /home/michael/opt/Xilinx/13.4/ISE_DS/PlanAhead/parts/xilinx/spartan6/PinFunctions.xml... +Loading package from /home/michael/opt/Xilinx/13.4/ISE_DS/PlanAhead/parts/xilinx/spartan6/spartan6lx/xc6slx16/csg324/Package.xml +Loading io standards from /home/michael/opt/Xilinx/13.4/ISE_DS/PlanAhead/./parts/xilinx/spartan6/IOStandards.xml +Loading device configuration modes from /home/michael/opt/Xilinx/13.4/ISE_DS/PlanAhead/parts/xilinx/spartan6/ConfigModes.xml +Loading list of drcs for the architecture : /home/michael/opt/Xilinx/13.4/ISE_DS/PlanAhead/./parts/xilinx/spartan6/drc.xml +Parsing UCF File [/home/michael/Documents/School/EC311/lab2/ALUSHOW.ucf] +Finished Parsing UCF File [/home/michael/Documents/School/EC311/lab2/ALUSHOW.ucf] +INFO: [PlanAhead-566] Unisim Transformation Summary: +No Unisim elements were transformed.open_rtl_design: Time (s): 20.520u 0.570s 28.760w. Memory (MB): 4537.992p 149.031g +exit +stop_gui +INFO: [PlanAhead-261] Exiting PlanAhead... +INFO: [Common-83] Releasing license: PlanAhead diff --git a/planAhead_run_1/planAhead_run.log b/planAhead_run_1/planAhead_run.log new file mode 100644 index 0000000..c3acc99 --- /dev/null +++ b/planAhead_run_1/planAhead_run.log @@ -0,0 +1,54 @@ + +****** PlanAhead v13.4 (64-bit) + **** Build 157570 by hdbuild on Fri Dec 16 12:49:33 MST 2011 + ** Copyright 1986-1999, 2001-2011 Xilinx, Inc. All Rights Reserved. + +INFO: [Common-78] Attempting to get a license: PlanAhead +INFO: [Common-82] Got a license: PlanAhead +INFO: [Device-25] Loading parts and site information from /home/michael/opt/Xilinx/13.4/ISE_DS/PlanAhead/parts/arch.xmlParsing RTL primitives file [/home/michael/opt/Xilinx/13.4/ISE_DS/PlanAhead/parts/xilinx/rtl/prims/rtl_prims.xml] +Finished parsing RTL primitives file [/home/michael/opt/Xilinx/13.4/ISE_DS/PlanAhead/parts/xilinx/rtl/prims/rtl_prims.xml] +start_gui +starting gui ... +source /home/michael/Documents/School/EC311/lab2/pa.fromHdl.tcl +# create_project -name lab2 -dir "/home/michael/Documents/School/EC311/lab2/planAhead_run_2" -part xc6slx16csg324-3 +Parsing template File [/home/michael/opt/Xilinx/13.4/ISE_DS/ISE/data/projnav/templates/verilog.xml]. +Finished parsing template File [/home/michael/opt/Xilinx/13.4/ISE_DS/ISE/data/projnav/templates/verilog.xml]. +Parsing template File [/home/michael/opt/Xilinx/13.4/ISE_DS/ISE/data/projnav/templates/vhdl.xml]. +Finished parsing template File [/home/michael/opt/Xilinx/13.4/ISE_DS/ISE/data/projnav/templates/vhdl.xml]. +Parsing template File [/home/michael/opt/Xilinx/13.4/ISE_DS/ISE/data/projnav/templates/ucf.xml]. +Finished parsing template File [/home/michael/opt/Xilinx/13.4/ISE_DS/ISE/data/projnav/templates/ucf.xml]. +# set_param project.pinAheadLayout yes +# set srcset [get_property srcset [current_run -impl]] +# set_property target_constrs_file "ALUSHOW.ucf" [current_fileset -constrset] +Adding file '/home/michael/Documents/School/EC311/lab2/ALUSHOW.ucf' to fileset 'constrs_1' +# set hdlfile [add_files [list {sev_seg_disp.vf}]] +# set_property file_type Verilog $hdlfile +# set_property library work $hdlfile +# set hdlfile [add_files [list {ALU.v}]] +# set_property file_type Verilog $hdlfile +# set_property library work $hdlfile +# set hdlfile [add_files [list {ALUSHOW.vf}]] +# set_property file_type Verilog $hdlfile +# set_property library work $hdlfile +# set_property top ALUSHOW $srcset +# add_files [list {ALUSHOW.ucf}] -fileset [get_property constrset [current_run]] +# open_rtl_design -part xc6slx16csg324-3 +INFO: [PlanAhead-58] Using Verific elaboration +Parsing VHDL file "/home/michael/opt/Xilinx/13.4/ISE_DS/PlanAhead/parts/xilinx/rtl/lib/synplify/synattr.vhd" into library synplify +Analyzing Verilog file "/home/michael/Documents/School/EC311/lab2/ALU.v" into library work +Analyzing Verilog file "/home/michael/Documents/School/EC311/lab2/ALUSHOW.vf" into library work +Loading clock regions from /home/michael/opt/Xilinx/13.4/ISE_DS/PlanAhead/parts/xilinx/spartan6/spartan6lx/xc6slx16/ClockRegion.xml +Loading clock buffers from /home/michael/opt/Xilinx/13.4/ISE_DS/PlanAhead/parts/xilinx/spartan6/spartan6lx/xc6slx16/ClockBuffers.xml +Loading package pin functions from /home/michael/opt/Xilinx/13.4/ISE_DS/PlanAhead/parts/xilinx/spartan6/PinFunctions.xml... +Loading package from /home/michael/opt/Xilinx/13.4/ISE_DS/PlanAhead/parts/xilinx/spartan6/spartan6lx/xc6slx16/csg324/Package.xml +Loading io standards from /home/michael/opt/Xilinx/13.4/ISE_DS/PlanAhead/./parts/xilinx/spartan6/IOStandards.xml +Loading device configuration modes from /home/michael/opt/Xilinx/13.4/ISE_DS/PlanAhead/parts/xilinx/spartan6/ConfigModes.xml +Loading list of drcs for the architecture : /home/michael/opt/Xilinx/13.4/ISE_DS/PlanAhead/./parts/xilinx/spartan6/drc.xml +Parsing UCF File [/home/michael/Documents/School/EC311/lab2/ALUSHOW.ucf] +Finished Parsing UCF File [/home/michael/Documents/School/EC311/lab2/ALUSHOW.ucf] +INFO: [PlanAhead-566] Unisim Transformation Summary: +No Unisim elements were transformed.open_rtl_design: Time (s): 20.520u 0.570s 28.760w. Memory (MB): 4537.992p 149.031g +exit +stop_gui +INFO: [PlanAhead-261] Exiting PlanAhead... +INFO: [Common-83] Releasing license: PlanAhead diff --git a/planAhead_run_2/lab2.data/constrs_1/fileset.xml b/planAhead_run_2/lab2.data/constrs_1/fileset.xml new file mode 100644 index 0000000..528719e --- /dev/null +++ b/planAhead_run_2/lab2.data/constrs_1/fileset.xml @@ -0,0 +1,25 @@ + + + + + + + + + + + + + + + diff --git a/planAhead_run_2/lab2.data/sources_1/fileset.xml b/planAhead_run_2/lab2.data/sources_1/fileset.xml new file mode 100644 index 0000000..3358a4c --- /dev/null +++ b/planAhead_run_2/lab2.data/sources_1/fileset.xml @@ -0,0 +1,51 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/planAhead_run_2/lab2.data/wt/webtalk_pa.xml b/planAhead_run_2/lab2.data/wt/webtalk_pa.xml new file mode 100644 index 0000000..f06abbd --- /dev/null +++ b/planAhead_run_2/lab2.data/wt/webtalk_pa.xml @@ -0,0 +1,30 @@ + + + + +
+ + +
+
+ + + + + + + + + + + + + + + + +
+ + diff --git a/planAhead_run_2/lab2.ppr b/planAhead_run_2/lab2.ppr new file mode 100644 index 0000000..99df0f9 --- /dev/null +++ b/planAhead_run_2/lab2.ppr @@ -0,0 +1,13 @@ + + + + + + + + + + diff --git a/sch2HdlBatchFile b/sch2HdlBatchFile new file mode 100644 index 0000000..f4ab378 --- /dev/null +++ b/sch2HdlBatchFile @@ -0,0 +1,2 @@ +sch2hdl,-intstyle,ise,-family,spartan6,-verilog,/home/michael/Documents/School/EC311/lab2/ALUSHOW.vf,-w,/home/michael/Documents/School/EC311/lab2/ALUSHOW.sch +sch2hdl,-intstyle,ise,-family,spartan6,-verilog,/home/michael/Documents/School/EC311/lab2/sev_seg_disp.vf,-w,/home/michael/Documents/School/EC311/lab2/sev_seg_disp.sch diff --git a/sev_seg_disp.jhd b/sev_seg_disp.jhd new file mode 100755 index 0000000..30cf3b6 --- /dev/null +++ b/sev_seg_disp.jhd @@ -0,0 +1 @@ +MODULE sev_seg_disp diff --git a/sev_seg_disp.sch b/sev_seg_disp.sch new file mode 100755 index 0000000..58d0e07 --- /dev/null +++ b/sev_seg_disp.sch @@ -0,0 +1,976 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 2000-1-1T10:10:10 + + + + + + + + + + + + + + 2000-1-1T10:10:10 + + + + + + + + + + + + + + 2000-1-1T10:10:10 + + + + + + + + + 2000-1-1T10:10:10 + + + + + + + + + + + + 2000-1-1T10:10:10 + + + + + + + + + + 2000-1-1T10:10:10 + + + + + + + + + + + 2000-1-1T10:10:10 + + + + + + + + + + + + + + + 2000-1-1T10:10:10 + + + + + + + + + + + 2000-1-1T10:10:10 + + + + + + + + + + + + + + + + 2000-1-1T10:10:10 + + + + + + + + 2000-1-1T10:10:10 + + + + + + + + + 2000-1-1T10:10:10 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/sev_seg_disp.sym b/sev_seg_disp.sym new file mode 100755 index 0000000..f408003 --- /dev/null +++ b/sev_seg_disp.sym @@ -0,0 +1,57 @@ + + + BLOCK + 2012-2-8T3:29:18 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/sev_seg_disp.vf b/sev_seg_disp.vf new file mode 100644 index 0000000..abe413c --- /dev/null +++ b/sev_seg_disp.vf @@ -0,0 +1,236 @@ +//////////////////////////////////////////////////////////////////////////////// +// Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. +//////////////////////////////////////////////////////////////////////////////// +// ____ ____ +// / /\/ / +// /___/ \ / Vendor: Xilinx +// \ \ \/ Version : 13.4 +// \ \ Application : sch2hdl +// / / Filename : sev_seg_disp.vf +// /___/ /\ Timestamp : 02/15/2012 21:35:26 +// \ \ / \ +// \___\/\___\ +// +//Command: sch2hdl -intstyle ise -family spartan6 -verilog /home/michael/Documents/School/EC311/lab2/sev_seg_disp.vf -w /home/michael/Documents/School/EC311/lab2/sev_seg_disp.sch +//Design Name: sev_seg_disp +//Device: spartan6 +//Purpose: +// This verilog netlist is translated from an ECS schematic.It can be +// synthesized and simulated, but it should not be modified. +// +`timescale 1ns / 1ps + +module sev_seg_disp(A, + B, + C, + D, + AN0, + AN1, + AN2, + AN3, + a_out, + b_out, + c_out, + d_out, + e_out, + f_out, + g_out, + sign); + + input A; + input B; + input C; + input D; + output AN0; + output AN1; + output AN2; + output AN3; + output a_out; + output b_out; + output c_out; + output d_out; + output e_out; + output f_out; + output g_out; + output sign; + + wire A_BAR; + wire B_BAR; + wire C_BAR; + wire D_BAR; + wire XLXN_14; + wire XLXN_24; + wire XLXN_61; + wire XLXN_62; + wire XLXN_63; + wire XLXN_64; + wire XLXN_65; + wire XLXN_91; + wire XLXN_92; + wire XLXN_93; + wire XLXN_94; + wire XLXN_105; + wire XLXN_113; + wire XLXN_114; + wire XLXN_125; + wire XLXN_126; + wire XLXN_128; + wire XLXN_129; + wire XLXN_130; + wire XLXN_131; + wire XLXN_145; + wire XLXN_146; + wire XLXN_147; + wire XLXN_148; + wire XLXN_149; + wire XLXN_151; + wire XLXN_155; + wire XLXN_156; + wire XLXN_158; + wire XLXN_160; + wire XLXN_162; + wire XLXN_165; + + BUF XLXI_5 (.I(XLXN_14), + .O(AN0)); + BUF XLXI_6 (.I(XLXN_14), + .O(AN1)); + BUF XLXI_7 (.I(XLXN_14), + .O(AN2)); + BUF XLXI_8 (.I(XLXN_24), + .O(AN3)); + GND XLXI_11 (.G(XLXN_24)); + VCC XLXI_12 (.P(XLXN_14)); + AND3 XLXI_30 (.I0(B), + .I1(C_BAR), + .I2(D), + .O(XLXN_61)); + AND3 XLXI_31 (.I0(A_BAR), + .I1(D), + .I2(C), + .O(XLXN_62)); + AND2 XLXI_32 (.I0(B_BAR), + .I1(D_BAR), + .O(XLXN_63)); + AND2 XLXI_33 (.I0(C), + .I1(D_BAR), + .O(XLXN_64)); + OR5 XLXI_34 (.I0(XLXN_65), + .I1(XLXN_64), + .I2(XLXN_63), + .I3(XLXN_62), + .I4(XLXN_61), + .O(XLXN_149)); + AND2 XLXI_35 (.I0(B_BAR), + .I1(A), + .O(XLXN_65)); + INV XLXI_37 (.I(A), + .O(A_BAR)); + INV XLXI_38 (.I(B), + .O(B_BAR)); + INV XLXI_39 (.I(C), + .O(C_BAR)); + INV XLXI_40 (.I(D), + .O(D_BAR)); + OR4 XLXI_41 (.I0(XLXN_94), + .I1(XLXN_93), + .I2(XLXN_92), + .I3(XLXN_91), + .O(XLXN_151)); + XNOR2 XLXI_42 (.I0(B), + .I1(A), + .O(XLXN_91)); + AND2 XLXI_43 (.I0(D_BAR), + .I1(C_BAR), + .O(XLXN_92)); + AND2 XLXI_44 (.I0(B_BAR), + .I1(C_BAR), + .O(XLXN_93)); + AND3 XLXI_45 (.I0(A_BAR), + .I1(D), + .I2(C), + .O(XLXN_94)); + XOR2 XLXI_46 (.I0(B), + .I1(A), + .O(XLXN_105)); + OR3 XLXI_47 (.I0(D), + .I1(C_BAR), + .I2(XLXN_105), + .O(XLXN_155)); + AND2 XLXI_48 (.I0(D_BAR), + .I1(C), + .O(XLXN_125)); + AND2 XLXI_49 (.I0(D_BAR), + .I1(B_BAR), + .O(XLXN_126)); + AND2 XLXI_50 (.I0(C), + .I1(B_BAR), + .O(XLXN_113)); + AND3 XLXI_51 (.I0(C_BAR), + .I1(D), + .I2(B), + .O(XLXN_114)); + OR4 XLXI_52 (.I0(XLXN_114), + .I1(XLXN_113), + .I2(XLXN_126), + .I3(XLXN_125), + .O(XLXN_156)); + OR2 XLXI_53 (.I0(XLXN_126), + .I1(XLXN_125), + .O(XLXN_158)); + AND3 XLXI_54 (.I0(C_BAR), + .I1(B), + .I2(A_BAR), + .O(XLXN_128)); + AND3 XLXI_55 (.I0(C), + .I1(B_BAR), + .I2(A), + .O(XLXN_129)); + AND3 XLXI_56 (.I0(D_BAR), + .I1(B), + .I2(A_BAR), + .O(XLXN_130)); + AND2 XLXI_57 (.I0(D_BAR), + .I1(C_BAR), + .O(XLXN_131)); + OR4 XLXI_58 (.I0(XLXN_131), + .I1(XLXN_130), + .I2(XLXN_129), + .I3(XLXN_128), + .O(XLXN_160)); + OR4 XLXI_60 (.I0(XLXN_148), + .I1(XLXN_147), + .I2(XLXN_146), + .I3(XLXN_145), + .O(XLXN_162)); + AND2 XLXI_61 (.I0(C_BAR), + .I1(B), + .O(XLXN_145)); + AND2 XLXI_62 (.I0(D_BAR), + .I1(C), + .O(XLXN_146)); + AND2 XLXI_63 (.I0(B_BAR), + .I1(C), + .O(XLXN_147)); + AND2 XLXI_64 (.I0(D_BAR), + .I1(A), + .O(XLXN_148)); + INV XLXI_65 (.I(XLXN_149), + .O(a_out)); + INV XLXI_66 (.I(XLXN_151), + .O(b_out)); + INV XLXI_67 (.I(XLXN_155), + .O(c_out)); + INV XLXI_68 (.I(XLXN_158), + .O(e_out)); + INV XLXI_69 (.I(XLXN_156), + .O(d_out)); + INV XLXI_70 (.I(XLXN_160), + .O(f_out)); + INV XLXI_71 (.I(XLXN_162), + .O(g_out)); + INV XLXI_72 (.I(A_BAR), + .O(XLXN_165)); + INV XLXI_73 (.I(XLXN_165), + .O(sign)); +endmodule diff --git a/webtalk_pn.xml b/webtalk_pn.xml new file mode 100755 index 0000000..7067f28 --- /dev/null +++ b/webtalk_pn.xml @@ -0,0 +1,43 @@ + + + + +
+ + + + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + -- cgit v1.2.3-54-g00ecf