From 59d89428d6160fb672c2b6a41339505cc69344d0 Mon Sep 17 00:00:00 2001 From: Michael Abed Date: Fri, 17 Feb 2012 12:10:31 -0500 Subject: finish it --- ALUSHOW_summary.html | 295 +++++++++++++++++++++++++++++++++++++++++++++++---- 1 file changed, 277 insertions(+), 18 deletions(-) (limited to 'ALUSHOW_summary.html') diff --git a/ALUSHOW_summary.html b/ALUSHOW_summary.html index 56bb337..a2e01b8 100644 --- a/ALUSHOW_summary.html +++ b/ALUSHOW_summary.html @@ -2,7 +2,7 @@ - + @@ -13,27 +13,26 @@ - + +No Errors - + - + +All Signals Completely Routed @@ -44,21 +43,279 @@ - +
ALUSHOW Project Status (02/15/2012 - 21:35:26)
ALUSHOW Project Status (02/16/2012 - 20:17:59)
Project File: lab2.xiseModule Name: ALUSHOW Implementation State:SynthesizedPlaced and Routed
Target Device: xc6slx16-3csg324
  • Errors:
 -X -2 Errors (2 new)
Product Version:ISE 13.4Product Version:ISE 13.3
  • Warnings:
No Warnings2 Warnings (0 new)
Design Goal: Balanced
  • Routing Results:
 - 
Design Strategy:
Environment: - + System Settings
  • Final Timing Score:
  0  (Timing Report)
+ 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Device Utilization Summary [-]
Slice Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Registers018,2240% 
Number of Slice LUTs139,1121% 
    Number used as logic139,1121% 
        Number using O6 output only13   
        Number using O5 output only0   
        Number using O5 and O60   
        Number used as ROM0   
    Number used as Memory02,1760% 
Number of occupied Slices52,2781% 
Nummber of MUXCYs used04,5560% 
Number of LUT Flip Flop pairs used13   
    Number with an unused Flip Flop1313100% 
    Number with an unused LUT0130% 
    Number of fully used LUT-FF pairs0130% 
    Number of slice register sites lost
        to control set restrictions		018,2240% 
Number of bonded IOBs182327% 
    Number of LOCed IOBs1818100% 
Number of RAMB16BWERs0320% 
Number of RAMB8BWERs0640% 
Number of BUFIO2/BUFIO2_2CLKs0320% 
Number of BUFIO2FB/BUFIO2FB_2CLKs0320% 
Number of BUFG/BUFGMUXs0160% 
Number of DCM/DCM_CLKGENs040% 
Number of ILOGIC2/ISERDES2s02480% 
Number of IODELAY2/IODRP2/IODRP2_MCBs02480% 
Number of OLOGIC2/OSERDES2s02480% 
Number of BSCANs040% 
Number of BUFHs01280% 
Number of BUFPLLs080% 
Number of BUFPLL_MCBs040% 
Number of DSP48A1s0320% 
Number of ICAPs010% 
Number of MCBs020% 
Number of PCILOGICSEs020% 
Number of PLL_ADVs020% 
Number of PMVs010% 
Number of STARTUPs010% 
Number of SUSPEND_SYNCs010% 
Average Fanout of Non-Clock Nets3.32   
- - + 
+ + + + + + + + + + + + + + + + + +
Performance Summary [-]
Final Timing Score:0 (Setup: 0, Hold: 0)Pinout Data:Pinout Report
Routing Results: +All Signals Completely RoutedClock Data:Clock Report
Timing Constraints:   
@@ -66,19 +323,21 @@ System Settings Detailed Reports [-] Report NameStatusGenerated ErrorsWarningsInfos -Synthesis ReportCurrentWed Feb 15 20:30:08 2012X 2 Errors (2 new)00 -Translation Report      -Map Report      -Place and Route Report      +Synthesis ReportCurrentThu Feb 16 20:17:08 201202 Warnings (0 new)0 +Translation ReportCurrentThu Feb 16 20:17:16 2012000 +Map ReportCurrentThu Feb 16 20:17:27 2012006 Infos (0 new) +Place and Route ReportCurrentThu Feb 16 20:17:49 2012002 Infos (0 new) Power Report      -Post-PAR Static Timing Report      -Bitgen Report      +Post-PAR Static Timing ReportCurrentThu Feb 16 20:17:57 2012003 Infos (0 new) +Bitgen ReportOut of DateThu Feb 16 20:08:03 2012000  
+ +
Secondary Reports [-]
Report NameStatusGenerated
WebTalk ReportOut of DateThu Feb 16 20:08:04 2012
WebTalk Log FileOut of DateThu Feb 16 20:08:12 2012
-
Date Generated: 02/15/2012 - 21:38:21
+
Date Generated: 02/16/2012 - 20:17:59
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