From 59d89428d6160fb672c2b6a41339505cc69344d0 Mon Sep 17 00:00:00 2001
From: Michael Abed <michaelabed@gmail.com>
Date: Fri, 17 Feb 2012 12:10:31 -0500
Subject: finish it

---
 _xmsgs/trce.xmsgs | 15 +++++++++++++++
 1 file changed, 15 insertions(+)
 create mode 100755 _xmsgs/trce.xmsgs

(limited to '_xmsgs/trce.xmsgs')

diff --git a/_xmsgs/trce.xmsgs b/_xmsgs/trce.xmsgs
new file mode 100755
index 0000000..80cb2e4
--- /dev/null
+++ b/_xmsgs/trce.xmsgs
@@ -0,0 +1,15 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<!-- IMPORTANT: This is an internal file that has been generated
+     by the Xilinx ISE software.  Any direct editing or
+     changes made to this file may result in unpredictable
+     behavior or data corruption.  It is strongly advised that
+     users do not edit the contents of this file. -->
+<messages>
+<msg type="info" file="Timing" num="2698" delta="old" >No timing constraints found, doing default enumeration.</msg>
+
+<msg type="info" file="Timing" num="2752" delta="old" >To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report.</msg>
+
+<msg type="info" file="Timing" num="3339" delta="old" >The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model.  For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet.</msg>
+
+</messages>
+
-- 
cgit v1.2.3-54-g00ecf