From 59d89428d6160fb672c2b6a41339505cc69344d0 Mon Sep 17 00:00:00 2001 From: Michael Abed Date: Fri, 17 Feb 2012 12:10:31 -0500 Subject: finish it --- _xmsgs/bitgen.xmsgs | 9 +++++++++ _xmsgs/map.xmsgs | 27 +++++++++++++++++++++++++++ _xmsgs/ngdbuild.xmsgs | 9 +++++++++ _xmsgs/par.xmsgs | 15 +++++++++++++++ _xmsgs/pn_parser.xmsgs | 24 ++++++++++++------------ _xmsgs/trce.xmsgs | 15 +++++++++++++++ _xmsgs/xst.xmsgs | 7 +++++-- 7 files changed, 92 insertions(+), 14 deletions(-) create mode 100755 _xmsgs/bitgen.xmsgs create mode 100755 _xmsgs/map.xmsgs create mode 100755 _xmsgs/ngdbuild.xmsgs create mode 100755 _xmsgs/par.xmsgs create mode 100755 _xmsgs/trce.xmsgs (limited to '_xmsgs') diff --git a/_xmsgs/bitgen.xmsgs b/_xmsgs/bitgen.xmsgs new file mode 100755 index 0000000..c42b14a --- /dev/null +++ b/_xmsgs/bitgen.xmsgs @@ -0,0 +1,9 @@ + + + + + diff --git a/_xmsgs/map.xmsgs b/_xmsgs/map.xmsgs new file mode 100755 index 0000000..4ecf2a7 --- /dev/null +++ b/_xmsgs/map.xmsgs @@ -0,0 +1,27 @@ + + + +No environment variables are currently set. + + +All of the single ended outputs in this design are using slew rate limited output drivers. The delay on speed critical single ended outputs can be dramatically reduced by designating them as fast outputs. + + +Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius) + + +Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts) + + +The Interim Design Summary has been generated in the MAP Report (.mrp). + + +Map created a placed design. + + + + diff --git a/_xmsgs/ngdbuild.xmsgs b/_xmsgs/ngdbuild.xmsgs new file mode 100755 index 0000000..c42b14a --- /dev/null +++ b/_xmsgs/ngdbuild.xmsgs @@ -0,0 +1,9 @@ + + + + + diff --git a/_xmsgs/par.xmsgs b/_xmsgs/par.xmsgs new file mode 100755 index 0000000..5f1f5f1 --- /dev/null +++ b/_xmsgs/par.xmsgs @@ -0,0 +1,15 @@ + + + +No user timing constraints were detected or you have set the option to ignore timing constraints ("par -x"). Place and Route will run in "Performance Evaluation Mode" to automatically improve the performance of all internal clocks in this design. Because there are not defined timing requirements, a timing score will not be reported in the PAR report in this mode. The PAR timing summary will list the performance achieved for each clock. Note: For the fastest runtime, set the effort level to "std". For best performance, set the effort level to "high". + + +The Clock Report is not displayed in the non timing-driven mode. + + + + diff --git a/_xmsgs/pn_parser.xmsgs b/_xmsgs/pn_parser.xmsgs index 2211003..ee464b0 100755 --- a/_xmsgs/pn_parser.xmsgs +++ b/_xmsgs/pn_parser.xmsgs @@ -1,12 +1,12 @@ - - - - - - - - - - - - + + + + + + + + + + + + diff --git a/_xmsgs/trce.xmsgs b/_xmsgs/trce.xmsgs new file mode 100755 index 0000000..80cb2e4 --- /dev/null +++ b/_xmsgs/trce.xmsgs @@ -0,0 +1,15 @@ + + + +No timing constraints found, doing default enumeration. + +To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report. + +The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet. + + + diff --git a/_xmsgs/xst.xmsgs b/_xmsgs/xst.xmsgs index 8233bd5..3e430a7 100755 --- a/_xmsgs/xst.xmsgs +++ b/_xmsgs/xst.xmsgs @@ -5,10 +5,13 @@ behavior or data corruption. It is strongly advised that users do not edit the contents of this file. --> -"\\ad\eng\users\m\g\mgabed\My Documents\ec311\lab2\ALU.v" Line 26: out3 is not a constant +"\\ad\eng\users\m\g\mgabed\My Documents\ec311\ec311-lab2\ALU.v" Line 27: Redeclaration of ansi port o is not allowed -"\\ad\eng\users\m\g\mgabed\My Documents\ec311\lab2\ALU.v" Line 21: Module <ALU> ignored due to previous errors. +"\\ad\eng\users\m\g\mgabed\My Documents\ec311\ec311-lab2\ALU.v" Line 33: Result of 32-bit expression is truncated to fit in 4-bit target. + + +"\\ad\eng\users\m\g\mgabed\My Documents\ec311\ec311-lab2\ALU.v" Line 35: Result of 32-bit expression is truncated to fit in 4-bit target. -- cgit v1.2.3