From 59d89428d6160fb672c2b6a41339505cc69344d0 Mon Sep 17 00:00:00 2001
From: Michael Abed <michaelabed@gmail.com>
Date: Fri, 17 Feb 2012 12:10:31 -0500
Subject: finish it

---
 lab2.gise | 126 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++-----
 1 file changed, 116 insertions(+), 10 deletions(-)

(limited to 'lab2.gise')

diff --git a/lab2.gise b/lab2.gise
index ec644a8..c1122dd 100755
--- a/lab2.gise
+++ b/lab2.gise
@@ -24,19 +24,61 @@
   <files xmlns="http://www.xilinx.com/XMLSchema">
     <file xil_pn:fileType="FILE_SPL" xil_pn:name="ALU.spl"/>
     <file xil_pn:fileType="FILE_SYMBOL" xil_pn:name="ALU.sym" xil_pn:origination="imported"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGDBUILD_LOG" xil_pn:name="ALUSHOW.bld"/>
     <file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="ALUSHOW.cmd_log"/>
     <file xil_pn:fileType="FILE_JHD" xil_pn:name="ALUSHOW.jhd"/>
     <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="ALUSHOW.lso"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="ALUSHOW.ncd" xil_pn:subbranch="Par"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="ALUSHOW.ngc"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGD" xil_pn:name="ALUSHOW.ngd"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGR" xil_pn:name="ALUSHOW.ngr"/>
+    <file xil_pn:fileType="FILE_PAD_MISC" xil_pn:name="ALUSHOW.pad"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAR_REPORT" xil_pn:name="ALUSHOW.par" xil_pn:subbranch="Par"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PCF" xil_pn:name="ALUSHOW.pcf" xil_pn:subbranch="Map"/>
     <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="ALUSHOW.prj"/>
+    <file xil_pn:fileType="FILE_TRCE_MISC" xil_pn:name="ALUSHOW.ptwx"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_STX" xil_pn:name="ALUSHOW.stx"/>
     <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="ALUSHOW.syr"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_TXT_REPORT" xil_pn:name="ALUSHOW.twr" xil_pn:subbranch="Par"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_XML_REPORT" xil_pn:name="ALUSHOW.twx" xil_pn:subbranch="Par"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_UNROUTES" xil_pn:name="ALUSHOW.unroutes" xil_pn:subbranch="Par"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_REPORT" xil_pn:name="ALUSHOW.ut" xil_pn:subbranch="FPGAConfiguration"/>
     <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_VERILOG" xil_pn:name="ALUSHOW.vf"/>
+    <file xil_pn:fileType="FILE_XPI" xil_pn:name="ALUSHOW.xpi"/>
     <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="ALUSHOW.xst"/>
+    <file xil_pn:fileType="FILE_HTML" xil_pn:name="ALUSHOW_envsettings.html"/>
+    <file xil_pn:fileType="FILE_NCD" xil_pn:name="ALUSHOW_guide.ncd" xil_pn:origination="imported"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="ALUSHOW_map.map" xil_pn:subbranch="Map"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="ALUSHOW_map.mrp" xil_pn:subbranch="Map"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="ALUSHOW_map.ncd" xil_pn:subbranch="Map"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGM" xil_pn:name="ALUSHOW_map.ngm" xil_pn:subbranch="Map"/>
+    <file xil_pn:fileType="FILE_XRPT" xil_pn:name="ALUSHOW_map.xrpt"/>
+    <file xil_pn:fileType="FILE_XRPT" xil_pn:name="ALUSHOW_ngdbuild.xrpt"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_EXCEL_REPORT" xil_pn:name="ALUSHOW_pad.csv" xil_pn:subbranch="Par"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_TXT_REPORT" xil_pn:name="ALUSHOW_pad.txt" xil_pn:subbranch="Par"/>
+    <file xil_pn:fileType="FILE_XRPT" xil_pn:name="ALUSHOW_par.xrpt"/>
+    <file xil_pn:fileType="FILE_HTML" xil_pn:name="ALUSHOW_summary.html"/>
+    <file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="ALUSHOW_summary.xml"/>
+    <file xil_pn:fileType="FILE_WEBTALK" xil_pn:name="ALUSHOW_usage.xml"/>
     <file xil_pn:fileType="FILE_XRPT" xil_pn:name="ALUSHOW_xst.xrpt"/>
+    <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="_ngo"/>
+    <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/bitgen.xmsgs"/>
+    <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/map.xmsgs"/>
+    <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
+    <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/par.xmsgs"/>
+    <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/trce.xmsgs"/>
     <file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/xst.xmsgs"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_REPORT" xil_pn:name="alushow.bgn" xil_pn:subbranch="FPGAConfiguration"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BIT" xil_pn:name="alushow.bit" xil_pn:subbranch="FPGAConfiguration"/>
+    <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_DRC" xil_pn:name="alushow.drc" xil_pn:subbranch="FPGAConfiguration"/>
     <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="planAhead_run_1"/>
+    <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="planAhead_run_2"/>
     <file xil_pn:fileType="FILE_SYMBOL" xil_pn:name="sev_seg_disp.sym" xil_pn:origination="imported"/>
     <file xil_pn:branch="Implementation" xil_pn:fileType="FILE_VERILOG" xil_pn:name="sev_seg_disp.vf"/>
+    <file xil_pn:fileType="FILE_HTML" xil_pn:name="usage_statistics_webtalk.html"/>
+    <file xil_pn:fileType="FILE_LOG" xil_pn:name="webtalk.log"/>
     <file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="webtalk_pn.xml"/>
+    <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xlnx_auto_0_xdb"/>
     <file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xst"/>
   </files>
 
@@ -45,11 +87,9 @@
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
     </transform>
-    <transform xil_pn:end_ts="1329359726" xil_pn:in_ck="8672901215410369526" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="8812042356535902648" xil_pn:start_ts="1329359724">
+    <transform xil_pn:end_ts="1329444900" xil_pn:in_ck="8672901215410369526" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="8812042356535902648" xil_pn:start_ts="1329444897">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
-      <status xil_pn:value="OutOfDateForInputs"/>
-      <status xil_pn:value="InputChanged"/>
       <outfile xil_pn:name="ALUSHOW.vf"/>
       <outfile xil_pn:name="sev_seg_disp.vf"/>
     </transform>
@@ -68,24 +108,23 @@
     <transform xil_pn:end_ts="1329339840" xil_pn:name="TRAN_SubProjectPreToStructuralProxy" xil_pn:prop_ck="1106364426758808884" xil_pn:start_ts="1329339840">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
-      <status xil_pn:value="OutOfDateForPredecessor"/>
     </transform>
     <transform xil_pn:end_ts="1329339840" xil_pn:name="TRAN_platgen" xil_pn:prop_ck="-7866682887845958159" xil_pn:start_ts="1329339840">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
-      <status xil_pn:value="OutOfDateForPredecessor"/>
     </transform>
-    <transform xil_pn:end_ts="1329339851" xil_pn:in_ck="3292037550190937560" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="1223802107647622166" xil_pn:start_ts="1329339840">
-      <status xil_pn:value="FailedRun"/>
+    <transform xil_pn:end_ts="1329444919" xil_pn:in_ck="3292037550190937560" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="1223802107647622166" xil_pn:start_ts="1329444900">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="WarningsGenerated"/>
       <status xil_pn:value="ReadyToRun"/>
-      <status xil_pn:value="OutOfDateForInputs"/>
-      <status xil_pn:value="OutOfDateForPredecessor"/>
       <status xil_pn:value="OutOfDateForOutputs"/>
-      <status xil_pn:value="InputChanged"/>
       <status xil_pn:value="OutputChanged"/>
       <outfile xil_pn:name="ALUSHOW.jhd"/>
       <outfile xil_pn:name="ALUSHOW.lso"/>
+      <outfile xil_pn:name="ALUSHOW.ngc"/>
+      <outfile xil_pn:name="ALUSHOW.ngr"/>
       <outfile xil_pn:name="ALUSHOW.prj"/>
+      <outfile xil_pn:name="ALUSHOW.stx"/>
       <outfile xil_pn:name="ALUSHOW.syr"/>
       <outfile xil_pn:name="ALUSHOW.xst"/>
       <outfile xil_pn:name="ALUSHOW_xst.xrpt"/>
@@ -93,6 +132,73 @@
       <outfile xil_pn:name="webtalk_pn.xml"/>
       <outfile xil_pn:name="xst"/>
     </transform>
+    <transform xil_pn:end_ts="1329440720" xil_pn:in_ck="103203085102404015" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="1262981216968708389" xil_pn:start_ts="1329440720">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="ReadyToRun"/>
+    </transform>
+    <transform xil_pn:end_ts="1329444928" xil_pn:in_ck="7902372021357138552" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="2269185898041607528" xil_pn:start_ts="1329444919">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="ReadyToRun"/>
+      <outfile xil_pn:name="ALUSHOW.bld"/>
+      <outfile xil_pn:name="ALUSHOW.ngd"/>
+      <outfile xil_pn:name="ALUSHOW_ngdbuild.xrpt"/>
+      <outfile xil_pn:name="_ngo"/>
+      <outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
+    </transform>
+    <transform xil_pn:end_ts="1329444942" xil_pn:in_ck="7952914127870865369" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="1463976855095865663" xil_pn:start_ts="1329444928">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="ReadyToRun"/>
+      <status xil_pn:value="OutOfDateForOutputs"/>
+      <status xil_pn:value="OutputChanged"/>
+      <outfile xil_pn:name="ALUSHOW.pcf"/>
+      <outfile xil_pn:name="ALUSHOW_map.map"/>
+      <outfile xil_pn:name="ALUSHOW_map.mrp"/>
+      <outfile xil_pn:name="ALUSHOW_map.ncd"/>
+      <outfile xil_pn:name="ALUSHOW_map.ngm"/>
+      <outfile xil_pn:name="ALUSHOW_map.xrpt"/>
+      <outfile xil_pn:name="ALUSHOW_summary.xml"/>
+      <outfile xil_pn:name="ALUSHOW_usage.xml"/>
+      <outfile xil_pn:name="_xmsgs/map.xmsgs"/>
+    </transform>
+    <transform xil_pn:end_ts="1329444974" xil_pn:in_ck="-6073012148532986286" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="-1178055513630676559" xil_pn:start_ts="1329444942">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="ReadyToRun"/>
+      <outfile xil_pn:name="ALUSHOW.ncd"/>
+      <outfile xil_pn:name="ALUSHOW.pad"/>
+      <outfile xil_pn:name="ALUSHOW.par"/>
+      <outfile xil_pn:name="ALUSHOW.ptwx"/>
+      <outfile xil_pn:name="ALUSHOW.unroutes"/>
+      <outfile xil_pn:name="ALUSHOW.xpi"/>
+      <outfile xil_pn:name="ALUSHOW_pad.csv"/>
+      <outfile xil_pn:name="ALUSHOW_pad.txt"/>
+      <outfile xil_pn:name="ALUSHOW_par.xrpt"/>
+      <outfile xil_pn:name="_xmsgs/par.xmsgs"/>
+    </transform>
+    <transform xil_pn:end_ts="1329445005" xil_pn:in_ck="103203085102396390" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="7811248583369236494" xil_pn:start_ts="1329444974">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="ReadyToRun"/>
+      <outfile xil_pn:name="ALUSHOW.ut"/>
+      <outfile xil_pn:name="_xmsgs/bitgen.xmsgs"/>
+      <outfile xil_pn:name="alushow.bgn"/>
+      <outfile xil_pn:name="alushow.bit"/>
+      <outfile xil_pn:name="alushow.drc"/>
+      <outfile xil_pn:name="usage_statistics_webtalk.html"/>
+      <outfile xil_pn:name="webtalk.log"/>
+      <outfile xil_pn:name="webtalk_pn.xml"/>
+    </transform>
+    <transform xil_pn:end_ts="1329441048" xil_pn:in_ck="153745191614924432" xil_pn:name="TRAN_impactProgrammingTool" xil_pn:prop_ck="2682241697568822907" xil_pn:start_ts="1329441048">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="ReadyToRun"/>
+      <status xil_pn:value="OutOfDateForInputs"/>
+      <status xil_pn:value="InputChanged"/>
+    </transform>
+    <transform xil_pn:end_ts="1329444974" xil_pn:in_ck="1281356068058925525" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416185" xil_pn:start_ts="1329444966">
+      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="ReadyToRun"/>
+      <outfile xil_pn:name="ALUSHOW.twr"/>
+      <outfile xil_pn:name="ALUSHOW.twx"/>
+      <outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
+    </transform>
   </transforms>
 
 </generated_project>
-- 
cgit v1.2.3