From 0bdf2f0b18f7e2986336f8afc67fe18b8b382e7a Mon Sep 17 00:00:00 2001
From: Michael Abed <michaelabed@gmail.com>
Date: Thu, 16 Feb 2012 15:46:55 -0500
Subject: initial commit

---
 planAhead_run_2/lab2.data/constrs_1/fileset.xml | 25 ++++++++++++
 planAhead_run_2/lab2.data/sources_1/fileset.xml | 51 +++++++++++++++++++++++++
 planAhead_run_2/lab2.data/wt/webtalk_pa.xml     | 30 +++++++++++++++
 planAhead_run_2/lab2.ppr                        | 13 +++++++
 4 files changed, 119 insertions(+)
 create mode 100644 planAhead_run_2/lab2.data/constrs_1/fileset.xml
 create mode 100644 planAhead_run_2/lab2.data/sources_1/fileset.xml
 create mode 100644 planAhead_run_2/lab2.data/wt/webtalk_pa.xml
 create mode 100644 planAhead_run_2/lab2.ppr

(limited to 'planAhead_run_2')

diff --git a/planAhead_run_2/lab2.data/constrs_1/fileset.xml b/planAhead_run_2/lab2.data/constrs_1/fileset.xml
new file mode 100644
index 0000000..528719e
--- /dev/null
+++ b/planAhead_run_2/lab2.data/constrs_1/fileset.xml
@@ -0,0 +1,25 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<DARoots Version="1"
+		Minor="19">
+	<FileSet Name="constrs_1"
+			Type="Constrs"
+			RelSrcDir="$PSRCDIR/constrs_1">
+		<Filter Type="Constrs"/>
+		<File Path="$PPRDIR/../ALUSHOW.ucf">
+			<FileInfo>
+				<Attr Name="UsedInSynthesis"
+						Val="1"/>
+				<Attr Name="UsedInImplementation"
+						Val="1"/>
+				<Attr Name="UsedInSimulation"
+						Val="1"/>
+			</FileInfo>
+		</File>
+		<Config>
+			<Option Name="TargetConstrsFile"
+					Val="$PPRDIR/../ALUSHOW.ucf"/>
+			<Option Name="ConstrsType"
+					Val="UCF"/>
+		</Config>
+	</FileSet>
+</DARoots>
diff --git a/planAhead_run_2/lab2.data/sources_1/fileset.xml b/planAhead_run_2/lab2.data/sources_1/fileset.xml
new file mode 100644
index 0000000..3358a4c
--- /dev/null
+++ b/planAhead_run_2/lab2.data/sources_1/fileset.xml
@@ -0,0 +1,51 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<DARoots Version="1"
+		Minor="19">
+	<FileSet Name="sources_1"
+			Type="DesignSrcs"
+			RelSrcDir="$PSRCDIR/sources_1">
+		<Filter Type="Srcs"/>
+		<File Path="$PPRDIR/../sev_seg_disp.vf">
+			<FileInfo>
+				<Attr Name="UsedInSynthesis"
+						Val="1"/>
+				<Attr Name="UsedInImplementation"
+						Val="1"/>
+				<Attr Name="UsedInSimulation"
+						Val="1"/>
+			</FileInfo>
+		</File>
+		<File Path="$PPRDIR/../ALU.v">
+			<FileInfo>
+				<Attr Name="UsedInSynthesis"
+						Val="1"/>
+				<Attr Name="UsedInImplementation"
+						Val="1"/>
+				<Attr Name="UsedInSimulation"
+						Val="1"/>
+			</FileInfo>
+		</File>
+		<File Path="$PPRDIR/../ALUSHOW.vf">
+			<FileInfo>
+				<Attr Name="UsedInSynthesis"
+						Val="1"/>
+				<Attr Name="UsedInImplementation"
+						Val="1"/>
+				<Attr Name="UsedInSimulation"
+						Val="1"/>
+			</FileInfo>
+		</File>
+		<Config>
+			<Option Name="DesignMode"
+					Val="RTL"/>
+			<Option Name="TopModule"
+					Val="ALUSHOW"/>
+			<Option Name="TopLib"
+					Val="work"/>
+			<Option Name="TopRTLFile"
+					Val="$PPRDIR/../ALUSHOW.vf"/>
+			<Option Name="TopAutoSet"
+					Val="TRUE"/>
+		</Config>
+	</FileSet>
+</DARoots>
diff --git a/planAhead_run_2/lab2.data/wt/webtalk_pa.xml b/planAhead_run_2/lab2.data/wt/webtalk_pa.xml
new file mode 100644
index 0000000..f06abbd
--- /dev/null
+++ b/planAhead_run_2/lab2.data/wt/webtalk_pa.xml
@@ -0,0 +1,30 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<document>
+<!--The data in this file is primarily intended for consumption by Xilinx tools.
+The structure and the elements are likely to change over the next few releases.
+This means code written to parse this file will need to be revisited each subsequent release.-->
+<application name="pa" timeStamp="Wed Feb 15 21:37:58 2012">
+<section name="Project Information" visible="false">
+<property name="ProjectID" value="f01d355e589f494db7281c1ebb207295" type="ProjectID"/>
+<property name="ProjectIteration" value="1" type="ProjectIteration"/>
+</section>
+<section name="PlanAhead Usage" visible="true">
+<item name="Project Data">
+<property name="SrcSetCount" value="1" type="SrcSetCount"/>
+<property name="ConstraintSetCount" value="1" type="ConstraintSetCount"/>
+<property name="DesignMode" value="RTL" type="DesignMode"/>
+<property name="SynthesisStrategy" value="PlanAhead Defaults" type="SynthesisStrategy"/>
+<property name="ImplStrategy" value="ISE Defaults" type="ImplStrategy"/>
+</item>
+<item name="Java Command Handlers">
+<property name="FileExit" value="1" type="JavaHandler"/>
+</item>
+<item name="Other">
+<property name="GuiMode" value="0" type="GuiMode"/>
+<property name="BatchMode" value="0" type="BatchMode"/>
+<property name="TclMode" value="0" type="TclMode"/>
+<property name="ISEMode" value="2" type="ISEMode"/>
+</item>
+</section>
+</application>
+</document>
diff --git a/planAhead_run_2/lab2.ppr b/planAhead_run_2/lab2.ppr
new file mode 100644
index 0000000..99df0f9
--- /dev/null
+++ b/planAhead_run_2/lab2.ppr
@@ -0,0 +1,13 @@
+<?xml version="1.0"?>
+<Project Version="4" Minor="27">
+	<FileSet Dir="sources_1" File="fileset.xml"/>
+	<FileSet Dir="constrs_1" File="fileset.xml"/>
+	<DefaultLaunch Dir="$PRUNDIR"/>
+	<DefaultPromote Dir="$PROMOTEDIR"/>
+	<Config>
+		<Option Name="Part" Val="xc6slx16csg324-3"/>
+		<Option Name="TargetLanguage" Val="Verilog"/>
+		<Option Name="SourceMgmtMode" Val="All"/>
+	</Config>
+</Project>
+
-- 
cgit v1.2.3-54-g00ecf