From 59d89428d6160fb672c2b6a41339505cc69344d0 Mon Sep 17 00:00:00 2001
From: Michael Abed <michaelabed@gmail.com>
Date: Fri, 17 Feb 2012 12:10:31 -0500
Subject: finish it

---
 .../lab2.data/constrs_1/designprops.xml            |  29 ++++++
 planAhead_run_2/lab2.data/constrs_1/fileset.xml    |  70 ++++++++-----
 planAhead_run_2/lab2.data/constrs_1/usercols.xml   |   4 +
 planAhead_run_2/lab2.data/sources_1/fileset.xml    | 112 +++++++++++----------
 planAhead_run_2/lab2.data/sources_1/ports.xml      |  28 ++++++
 planAhead_run_2/lab2.ppr                           |  26 ++---
 planAhead_run_2/planAhead.jou                      |  12 +++
 planAhead_run_2/planAhead.log                      |  22 ++++
 planAhead_run_2/planAhead_run.log                  |  17 ++++
 9 files changed, 231 insertions(+), 89 deletions(-)
 create mode 100755 planAhead_run_2/lab2.data/constrs_1/designprops.xml
 mode change 100644 => 100755 planAhead_run_2/lab2.data/constrs_1/fileset.xml
 create mode 100755 planAhead_run_2/lab2.data/constrs_1/usercols.xml
 mode change 100644 => 100755 planAhead_run_2/lab2.data/sources_1/fileset.xml
 create mode 100755 planAhead_run_2/lab2.data/sources_1/ports.xml
 mode change 100644 => 100755 planAhead_run_2/lab2.ppr
 create mode 100755 planAhead_run_2/planAhead.jou
 create mode 100755 planAhead_run_2/planAhead.log
 create mode 100755 planAhead_run_2/planAhead_run.log

(limited to 'planAhead_run_2')

diff --git a/planAhead_run_2/lab2.data/constrs_1/designprops.xml b/planAhead_run_2/lab2.data/constrs_1/designprops.xml
new file mode 100755
index 0000000..841b5cf
--- /dev/null
+++ b/planAhead_run_2/lab2.data/constrs_1/designprops.xml
@@ -0,0 +1,29 @@
+<?xml version="1.0"?>
+<Compat Version="1" Minor="4">
+	<CompatParts>
+	</CompatParts>
+	<ConfigModes>
+		<Mode Id="JTAG"/>
+	</ConfigModes>
+	<PortProps>
+		<Port Name="A[3]" OffChipTerm="NONE"/>
+		<Port Name="A[2]" OffChipTerm="NONE"/>
+		<Port Name="A[1]" OffChipTerm="NONE"/>
+		<Port Name="A[0]" OffChipTerm="NONE"/>
+		<Port Name="S[1]" OffChipTerm="NONE"/>
+		<Port Name="S[0]" OffChipTerm="NONE"/>
+		<Port Name="AN0" OffChipTerm="FP_VTT_50"/>
+		<Port Name="AN1" OffChipTerm="FP_VTT_50"/>
+		<Port Name="AN2" OffChipTerm="FP_VTT_50"/>
+		<Port Name="AN3" OffChipTerm="FP_VTT_50"/>
+		<Port Name="ao" OffChipTerm="FP_VTT_50"/>
+		<Port Name="bo" OffChipTerm="FP_VTT_50"/>
+		<Port Name="co" OffChipTerm="FP_VTT_50"/>
+		<Port Name="do" OffChipTerm="FP_VTT_50"/>
+		<Port Name="eo" OffChipTerm="FP_VTT_50"/>
+		<Port Name="fo" OffChipTerm="FP_VTT_50"/>
+		<Port Name="go" OffChipTerm="FP_VTT_50"/>
+		<Port Name="sign" OffChipTerm="FP_VTT_50"/>
+	</PortProps>
+</Compat>
+
diff --git a/planAhead_run_2/lab2.data/constrs_1/fileset.xml b/planAhead_run_2/lab2.data/constrs_1/fileset.xml
old mode 100644
new mode 100755
index 528719e..46533c8
--- a/planAhead_run_2/lab2.data/constrs_1/fileset.xml
+++ b/planAhead_run_2/lab2.data/constrs_1/fileset.xml
@@ -1,25 +1,45 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<DARoots Version="1"
-		Minor="19">
-	<FileSet Name="constrs_1"
-			Type="Constrs"
-			RelSrcDir="$PSRCDIR/constrs_1">
-		<Filter Type="Constrs"/>
-		<File Path="$PPRDIR/../ALUSHOW.ucf">
-			<FileInfo>
-				<Attr Name="UsedInSynthesis"
-						Val="1"/>
-				<Attr Name="UsedInImplementation"
-						Val="1"/>
-				<Attr Name="UsedInSimulation"
-						Val="1"/>
-			</FileInfo>
-		</File>
-		<Config>
-			<Option Name="TargetConstrsFile"
-					Val="$PPRDIR/../ALUSHOW.ucf"/>
-			<Option Name="ConstrsType"
-					Val="UCF"/>
-		</Config>
-	</FileSet>
-</DARoots>
+<?xml version="1.0" encoding="UTF-8"?>
+<DARoots Version="1"
+		Minor="19">
+	<FileSet Name="constrs_1"
+			Type="Constrs"
+			RelSrcDir="$PSRCDIR/constrs_1">
+		<Filter Type="Constrs"/>
+		<File Path="$PPRDIR/../ALUSHOW.ucf">
+			<FileInfo>
+				<Attr Name="UsedInSynthesis"
+						Val="1"/>
+				<Attr Name="UsedInImplementation"
+						Val="1"/>
+				<Attr Name="UsedInSimulation"
+						Val="1"/>
+			</FileInfo>
+		</File>
+		<File Path="$PDATADIR/constrs_1/designprops.xml">
+			<FileInfo SFType="CompatPartsDb">
+				<Attr Name="UsedInSynthesis"
+						Val="1"/>
+				<Attr Name="UsedInImplementation"
+						Val="1"/>
+				<Attr Name="UsedInSimulation"
+						Val="1"/>
+			</FileInfo>
+		</File>
+		<File Path="$PDATADIR/constrs_1/usercols.xml">
+			<FileInfo SFType="UserColsDb">
+				<Attr Name="UsedInSynthesis"
+						Val="1"/>
+				<Attr Name="UsedInImplementation"
+						Val="1"/>
+				<Attr Name="UsedInSimulation"
+						Val="1"/>
+			</FileInfo>
+		</File>
+		<Config>
+			<Option Name="TargetConstrsFile"
+					Val="$PPRDIR/../ALUSHOW.ucf"/>
+			<Option Name="ConstrsType"
+					Val="UCF"/>
+		</Config>
+	</FileSet>
+</DARoots>
diff --git a/planAhead_run_2/lab2.data/constrs_1/usercols.xml b/planAhead_run_2/lab2.data/constrs_1/usercols.xml
new file mode 100755
index 0000000..b2e369a
--- /dev/null
+++ b/planAhead_run_2/lab2.data/constrs_1/usercols.xml
@@ -0,0 +1,4 @@
+<?xml version="1.0"?>
+<UserColInfo Version="1" Minor="0">
+</UserColInfo>
+
diff --git a/planAhead_run_2/lab2.data/sources_1/fileset.xml b/planAhead_run_2/lab2.data/sources_1/fileset.xml
old mode 100644
new mode 100755
index 3358a4c..81193a8
--- a/planAhead_run_2/lab2.data/sources_1/fileset.xml
+++ b/planAhead_run_2/lab2.data/sources_1/fileset.xml
@@ -1,51 +1,61 @@
-<?xml version="1.0" encoding="UTF-8"?>
-<DARoots Version="1"
-		Minor="19">
-	<FileSet Name="sources_1"
-			Type="DesignSrcs"
-			RelSrcDir="$PSRCDIR/sources_1">
-		<Filter Type="Srcs"/>
-		<File Path="$PPRDIR/../sev_seg_disp.vf">
-			<FileInfo>
-				<Attr Name="UsedInSynthesis"
-						Val="1"/>
-				<Attr Name="UsedInImplementation"
-						Val="1"/>
-				<Attr Name="UsedInSimulation"
-						Val="1"/>
-			</FileInfo>
-		</File>
-		<File Path="$PPRDIR/../ALU.v">
-			<FileInfo>
-				<Attr Name="UsedInSynthesis"
-						Val="1"/>
-				<Attr Name="UsedInImplementation"
-						Val="1"/>
-				<Attr Name="UsedInSimulation"
-						Val="1"/>
-			</FileInfo>
-		</File>
-		<File Path="$PPRDIR/../ALUSHOW.vf">
-			<FileInfo>
-				<Attr Name="UsedInSynthesis"
-						Val="1"/>
-				<Attr Name="UsedInImplementation"
-						Val="1"/>
-				<Attr Name="UsedInSimulation"
-						Val="1"/>
-			</FileInfo>
-		</File>
-		<Config>
-			<Option Name="DesignMode"
-					Val="RTL"/>
-			<Option Name="TopModule"
-					Val="ALUSHOW"/>
-			<Option Name="TopLib"
-					Val="work"/>
-			<Option Name="TopRTLFile"
-					Val="$PPRDIR/../ALUSHOW.vf"/>
-			<Option Name="TopAutoSet"
-					Val="TRUE"/>
-		</Config>
-	</FileSet>
-</DARoots>
+<?xml version="1.0" encoding="UTF-8"?>
+<DARoots Version="1"
+		Minor="19">
+	<FileSet Name="sources_1"
+			Type="DesignSrcs"
+			RelSrcDir="$PSRCDIR/sources_1">
+		<Filter Type="Srcs"/>
+		<File Path="$PPRDIR/../sev_seg_disp.vf">
+			<FileInfo>
+				<Attr Name="UsedInSynthesis"
+						Val="1"/>
+				<Attr Name="UsedInImplementation"
+						Val="1"/>
+				<Attr Name="UsedInSimulation"
+						Val="1"/>
+			</FileInfo>
+		</File>
+		<File Path="$PPRDIR/../ALU.v">
+			<FileInfo>
+				<Attr Name="UsedInSynthesis"
+						Val="1"/>
+				<Attr Name="UsedInImplementation"
+						Val="1"/>
+				<Attr Name="UsedInSimulation"
+						Val="1"/>
+			</FileInfo>
+		</File>
+		<File Path="$PPRDIR/../ALUSHOW.vf">
+			<FileInfo>
+				<Attr Name="UsedInSynthesis"
+						Val="1"/>
+				<Attr Name="UsedInImplementation"
+						Val="1"/>
+				<Attr Name="UsedInSimulation"
+						Val="1"/>
+			</FileInfo>
+		</File>
+		<File Path="$PDATADIR/sources_1/ports.xml">
+			<FileInfo SFType="PortsDb">
+				<Attr Name="UsedInSynthesis"
+						Val="1"/>
+				<Attr Name="UsedInImplementation"
+						Val="1"/>
+				<Attr Name="UsedInSimulation"
+						Val="1"/>
+			</FileInfo>
+		</File>
+		<Config>
+			<Option Name="DesignMode"
+					Val="RTL"/>
+			<Option Name="TopModule"
+					Val="ALUSHOW"/>
+			<Option Name="TopLib"
+					Val="work"/>
+			<Option Name="TopRTLFile"
+					Val="$PPRDIR/../ALUSHOW.vf"/>
+			<Option Name="TopAutoSet"
+					Val="TRUE"/>
+		</Config>
+	</FileSet>
+</DARoots>
diff --git a/planAhead_run_2/lab2.data/sources_1/ports.xml b/planAhead_run_2/lab2.data/sources_1/ports.xml
new file mode 100755
index 0000000..1eae741
--- /dev/null
+++ b/planAhead_run_2/lab2.data/sources_1/ports.xml
@@ -0,0 +1,28 @@
+<?xml version="1.0"?>
+<Interface Version="1" Minor="1">
+	<Ifc Id="ROOT" Top="1">
+		<Bus Id="A">
+			<Port Id="3" Dir="IN"/>
+			<Port Id="2" Dir="IN"/>
+			<Port Id="1" Dir="IN"/>
+			<Port Id="0" Dir="IN"/>
+		</Bus>
+		<Bus Id="S">
+			<Port Id="1" Dir="IN"/>
+			<Port Id="0" Dir="IN"/>
+		</Bus>
+		<Port Id="AN0" Dir="OUT"/>
+		<Port Id="AN1" Dir="OUT"/>
+		<Port Id="AN2" Dir="OUT"/>
+		<Port Id="AN3" Dir="OUT"/>
+		<Port Id="ao" Dir="OUT"/>
+		<Port Id="bo" Dir="OUT"/>
+		<Port Id="co" Dir="OUT"/>
+		<Port Id="do" Dir="OUT"/>
+		<Port Id="eo" Dir="OUT"/>
+		<Port Id="fo" Dir="OUT"/>
+		<Port Id="go" Dir="OUT"/>
+		<Port Id="sign" Dir="OUT"/>
+	</Ifc>
+</Interface>
+
diff --git a/planAhead_run_2/lab2.ppr b/planAhead_run_2/lab2.ppr
old mode 100644
new mode 100755
index 99df0f9..22481f8
--- a/planAhead_run_2/lab2.ppr
+++ b/planAhead_run_2/lab2.ppr
@@ -1,13 +1,13 @@
-<?xml version="1.0"?>
-<Project Version="4" Minor="27">
-	<FileSet Dir="sources_1" File="fileset.xml"/>
-	<FileSet Dir="constrs_1" File="fileset.xml"/>
-	<DefaultLaunch Dir="$PRUNDIR"/>
-	<DefaultPromote Dir="$PROMOTEDIR"/>
-	<Config>
-		<Option Name="Part" Val="xc6slx16csg324-3"/>
-		<Option Name="TargetLanguage" Val="Verilog"/>
-		<Option Name="SourceMgmtMode" Val="All"/>
-	</Config>
-</Project>
-
+<?xml version="1.0"?>
+<Project Version="4" Minor="27">
+	<FileSet Dir="sources_1" File="fileset.xml"/>
+	<FileSet Dir="constrs_1" File="fileset.xml"/>
+	<DefaultLaunch Dir="$PRUNDIR"/>
+	<DefaultPromote Dir="$PROMOTEDIR"/>
+	<Config>
+		<Option Name="Part" Val="xc6slx16csg324-3"/>
+		<Option Name="TargetLanguage" Val="Verilog"/>
+		<Option Name="SourceMgmtMode" Val="All"/>
+	</Config>
+</Project>
+
diff --git a/planAhead_run_2/planAhead.jou b/planAhead_run_2/planAhead.jou
new file mode 100755
index 0000000..b6014a9
--- /dev/null
+++ b/planAhead_run_2/planAhead.jou
@@ -0,0 +1,12 @@
+#-----------------------------------------------------------
+# PlanAhead v13.3 (64-bit)
+# Build 147507 by hdbuild on Tue Oct  4 19:13:50 MDT 2011
+# Start of session at: Thu Feb 16 20:01:49 2012
+# Process ID: 3352
+# Log file: X:/My Documents/ec311/ec311-lab2/planAhead_run_2/planAhead.log
+# Journal file: X:/My Documents/ec311/ec311-lab2/planAhead_run_2/planAhead.jou
+#-----------------------------------------------------------
+start_gui
+source {X:/My Documents/ec311/ec311-lab2/pa.fromHdl.tcl}
+exit
+stop_gui
diff --git a/planAhead_run_2/planAhead.log b/planAhead_run_2/planAhead.log
new file mode 100755
index 0000000..ddaab13
--- /dev/null
+++ b/planAhead_run_2/planAhead.log
@@ -0,0 +1,22 @@
+#-----------------------------------------------------------
+# PlanAhead v13.3 (64-bit)
+# Build 147507 by hdbuild on Tue Oct  4 19:13:50 MDT 2011
+# Start of session at: Thu Feb 16 20:01:49 2012
+# Process ID: 3352
+# Log file: X:/My Documents/ec311/ec311-lab2/planAhead_run_2/planAhead.log
+# Journal file: X:/My Documents/ec311/ec311-lab2/planAhead_run_2/planAhead.jou
+#-----------------------------------------------------------
+INFO: [Common-78] Attempting to get a license: PlanAhead
+INFO: [Common-82] Got a license: PlanAhead
+INFO: [Device-25] Loading parts and site information from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts\arch.xmlParsing RTL primitives file [C:/Xilinx/13.3/ISE_DS/PlanAhead\parts\xilinx\rtl\prims\rtl_prims.xml]
+Finished parsing RTL primitives file [C:/Xilinx/13.3/ISE_DS/PlanAhead\parts\xilinx\rtl\prims\rtl_prims.xml]
+start_gui
+source {X:/My Documents/ec311/ec311-lab2/pa.fromHdl.tcl}
+# create_project -name lab2 -dir "X:/My Documents/ec311/ec311-lab2/planAhead_run_2" -part xc6slx16csg324-3
+ERROR: [Common-53] User Exception: Project already exists on disk, please use '-force' option to overwrite: 
+     X:\My Documents\ec311\ec311-lab2\planAhead_run_2\lab2.ppr
+     X:\My Documents\ec311\ec311-lab2\planAhead_run_2\lab2.data
+exit
+stop_gui
+INFO: [PlanAhead-261] Exiting PlanAhead...
+INFO: [Common-83] Releasing license: PlanAhead
diff --git a/planAhead_run_2/planAhead_run.log b/planAhead_run_2/planAhead_run.log
new file mode 100755
index 0000000..aede38c
--- /dev/null
+++ b/planAhead_run_2/planAhead_run.log
@@ -0,0 +1,17 @@
+
+****** PlanAhead v13.3 (64-bit)
+  **** Build 147507 by hdbuild on Tue Oct  4 19:13:50 MDT 2011
+    ** Copyright 1986-1999, 2001-2011 Xilinx, Inc. All Rights Reserved.
+
+INFO: [Common-78] Attempting to get a license: PlanAhead
+INFO: [Common-82] Got a license: PlanAhead
+INFO: [Device-25] Loading parts and site information from C:/Xilinx/13.3/ISE_DS/PlanAhead\parts\arch.xmlParsing RTL primitives file [C:/Xilinx/13.3/ISE_DS/PlanAhead\parts\xilinx\rtl\prims\rtl_prims.xml]
+Finished parsing RTL primitives file [C:/Xilinx/13.3/ISE_DS/PlanAhead\parts\xilinx\rtl\prims\rtl_prims.xml]
+start_gui
+starting gui ...
+source {X:/My Documents/ec311/ec311-lab2/pa.fromHdl.tcl}
+# create_project -name lab2 -dir "X:/My Documents/ec311/ec311-lab2/planAhead_run_2" -part xc6slx16csg324-3
+exit
+stop_gui
+INFO: [PlanAhead-261] Exiting PlanAhead...
+INFO: [Common-83] Releasing license: PlanAhead
-- 
cgit v1.2.3-54-g00ecf