`timescale 1ns / 1ps
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// Company: 
// Engineer: 
// 
// Create Date:    15:30:47 02/15/2012 
// Design Name: 
// Module Name:    ALU 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module ALU(
	input [1:0] s,
	input [3:0] a,
	output [3:0] o
    );

reg [3:0] o;

always @ ( * )
begin 	 
	case ( s )
		2'd0 : o = a;
		2'd1 : o = ~a+1;
		2'd2 : o = a >> 1;
		2'd3 : o = a % 3;
	endcase
end
endmodule