ALUSHOW Project Status (02/16/2012 - 20:17:59) | |||
Project File: | lab2.xise | Parser Errors: | No Errors |
Module Name: | ALUSHOW | Implementation State: | Placed and Routed |
Target Device: | xc6slx16-3csg324 |
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No Errors |
Product Version: | ISE 13.3 |
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2 Warnings (0 new) |
Design Goal: | Balanced |
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All Signals Completely Routed |
Design Strategy: | Xilinx Default (unlocked) |
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Environment: | System Settings |
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0 (Timing Report) |
Device Utilization Summary | [-] | ||||
Slice Logic Utilization | Used | Available | Utilization | Note(s) | |
Number of Slice Registers | 0 | 18,224 | 0% | ||
Number of Slice LUTs | 13 | 9,112 | 1% | ||
Number used as logic | 13 | 9,112 | 1% | ||
Number using O6 output only | 13 | ||||
Number using O5 output only | 0 | ||||
Number using O5 and O6 | 0 | ||||
Number used as ROM | 0 | ||||
Number used as Memory | 0 | 2,176 | 0% | ||
Number of occupied Slices | 5 | 2,278 | 1% | ||
Nummber of MUXCYs used | 0 | 4,556 | 0% | ||
Number of LUT Flip Flop pairs used | 13 | ||||
Number with an unused Flip Flop | 13 | 13 | 100% | ||
Number with an unused LUT | 0 | 13 | 0% | ||
Number of fully used LUT-FF pairs | 0 | 13 | 0% | ||
Number of slice register sites lost to control set restrictions |
0 | 18,224 | 0% | ||
Number of bonded IOBs | 18 | 232 | 7% | ||
Number of LOCed IOBs | 18 | 18 | 100% | ||
Number of RAMB16BWERs | 0 | 32 | 0% | ||
Number of RAMB8BWERs | 0 | 64 | 0% | ||
Number of BUFIO2/BUFIO2_2CLKs | 0 | 32 | 0% | ||
Number of BUFIO2FB/BUFIO2FB_2CLKs | 0 | 32 | 0% | ||
Number of BUFG/BUFGMUXs | 0 | 16 | 0% | ||
Number of DCM/DCM_CLKGENs | 0 | 4 | 0% | ||
Number of ILOGIC2/ISERDES2s | 0 | 248 | 0% | ||
Number of IODELAY2/IODRP2/IODRP2_MCBs | 0 | 248 | 0% | ||
Number of OLOGIC2/OSERDES2s | 0 | 248 | 0% | ||
Number of BSCANs | 0 | 4 | 0% | ||
Number of BUFHs | 0 | 128 | 0% | ||
Number of BUFPLLs | 0 | 8 | 0% | ||
Number of BUFPLL_MCBs | 0 | 4 | 0% | ||
Number of DSP48A1s | 0 | 32 | 0% | ||
Number of ICAPs | 0 | 1 | 0% | ||
Number of MCBs | 0 | 2 | 0% | ||
Number of PCILOGICSEs | 0 | 2 | 0% | ||
Number of PLL_ADVs | 0 | 2 | 0% | ||
Number of PMVs | 0 | 1 | 0% | ||
Number of STARTUPs | 0 | 1 | 0% | ||
Number of SUSPEND_SYNCs | 0 | 1 | 0% | ||
Average Fanout of Non-Clock Nets | 3.32 |
Performance Summary | [-] | |||
Final Timing Score: | 0 (Setup: 0, Hold: 0) | Pinout Data: | Pinout Report | |
Routing Results: | All Signals Completely Routed | Clock Data: | Clock Report | |
Timing Constraints: |
Detailed Reports | [-] | |||||
Report Name | Status | Generated | Errors | Warnings | Infos | |
Synthesis Report | Current | Thu Feb 16 20:17:08 2012 | 0 | 2 Warnings (0 new) | 0 | |
Translation Report | Current | Thu Feb 16 20:17:16 2012 | 0 | 0 | 0 | |
Map Report | Current | Thu Feb 16 20:17:27 2012 | 0 | 0 | 6 Infos (0 new) | |
Place and Route Report | Current | Thu Feb 16 20:17:49 2012 | 0 | 0 | 2 Infos (0 new) | |
Power Report | ||||||
Post-PAR Static Timing Report | Current | Thu Feb 16 20:17:57 2012 | 0 | 0 | 3 Infos (0 new) | |
Bitgen Report | Out of Date | Thu Feb 16 20:08:03 2012 | 0 | 0 | 0 |
Secondary Reports | [-] | ||
Report Name | Status | Generated | |
WebTalk Report | Out of Date | Thu Feb 16 20:08:04 2012 | |
WebTalk Log File | Out of Date | Thu Feb 16 20:08:12 2012 |