# PlanAhead Launch Script for Pre-Synthesis Floorplanning, created by Project Navigator

create_project -name lab2 -dir "X:/My Documents/ec311/ec311-lab2/planAhead_run_2" -part xc6slx16csg324-3
set_param project.pinAheadLayout yes
set srcset [get_property srcset [current_run -impl]]
set_property top ALUSHOW $srcset
set_property target_constrs_file "ALUSHOW.ucf" [current_fileset -constrset]
set hdlfile [add_files [list {sev_seg_disp.vf}]]
set_property file_type Verilog $hdlfile
set_property library work $hdlfile
set hdlfile [add_files [list {ALU.v}]]
set_property file_type Verilog $hdlfile
set_property library work $hdlfile
set hdlfile [add_files [list {ALUSHOW.vf}]]
set_property file_type Verilog $hdlfile
set_property library work $hdlfile
add_files [list {ALUSHOW.ucf}] -fileset [get_property constrset [current_run]]
open_rtl_design -part xc6slx16csg324-3