****** PlanAhead v13.4 (64-bit)
  **** Build 157570 by hdbuild on Fri Dec 16 12:49:33 MST 2011
    ** Copyright 1986-1999, 2001-2011 Xilinx, Inc. All Rights Reserved.

INFO: [Common-78] Attempting to get a license: PlanAhead
INFO: [Common-82] Got a license: PlanAhead
INFO: [Device-25] Loading parts and site information from /home/michael/opt/Xilinx/13.4/ISE_DS/PlanAhead/parts/arch.xmlParsing RTL primitives file [/home/michael/opt/Xilinx/13.4/ISE_DS/PlanAhead/parts/xilinx/rtl/prims/rtl_prims.xml]
Finished parsing RTL primitives file [/home/michael/opt/Xilinx/13.4/ISE_DS/PlanAhead/parts/xilinx/rtl/prims/rtl_prims.xml]
start_gui
starting gui ...
source /home/michael/Documents/School/EC311/lab2/pa.fromHdl.tcl
# create_project -name lab2 -dir "/home/michael/Documents/School/EC311/lab2/planAhead_run_2" -part xc6slx16csg324-3
Parsing template File [/home/michael/opt/Xilinx/13.4/ISE_DS/ISE/data/projnav/templates/verilog.xml].
Finished parsing template File [/home/michael/opt/Xilinx/13.4/ISE_DS/ISE/data/projnav/templates/verilog.xml].
Parsing template File [/home/michael/opt/Xilinx/13.4/ISE_DS/ISE/data/projnav/templates/vhdl.xml].
Finished parsing template File [/home/michael/opt/Xilinx/13.4/ISE_DS/ISE/data/projnav/templates/vhdl.xml].
Parsing template File [/home/michael/opt/Xilinx/13.4/ISE_DS/ISE/data/projnav/templates/ucf.xml].
Finished parsing template File [/home/michael/opt/Xilinx/13.4/ISE_DS/ISE/data/projnav/templates/ucf.xml].
# set_param project.pinAheadLayout yes
# set srcset [get_property srcset [current_run -impl]]
# set_property target_constrs_file "ALUSHOW.ucf" [current_fileset -constrset]
Adding file '/home/michael/Documents/School/EC311/lab2/ALUSHOW.ucf' to fileset 'constrs_1'
# set hdlfile [add_files [list {sev_seg_disp.vf}]]
# set_property file_type Verilog $hdlfile
# set_property library work $hdlfile
# set hdlfile [add_files [list {ALU.v}]]
# set_property file_type Verilog $hdlfile
# set_property library work $hdlfile
# set hdlfile [add_files [list {ALUSHOW.vf}]]
# set_property file_type Verilog $hdlfile
# set_property library work $hdlfile
# set_property top ALUSHOW $srcset
# add_files [list {ALUSHOW.ucf}] -fileset [get_property constrset [current_run]]
# open_rtl_design -part xc6slx16csg324-3
INFO: [PlanAhead-58] Using Verific elaboration
Parsing VHDL file "/home/michael/opt/Xilinx/13.4/ISE_DS/PlanAhead/parts/xilinx/rtl/lib/synplify/synattr.vhd" into library synplify
Analyzing Verilog file "/home/michael/Documents/School/EC311/lab2/ALU.v" into library work
Analyzing Verilog file "/home/michael/Documents/School/EC311/lab2/ALUSHOW.vf" into library work
Loading clock regions from /home/michael/opt/Xilinx/13.4/ISE_DS/PlanAhead/parts/xilinx/spartan6/spartan6lx/xc6slx16/ClockRegion.xml
Loading clock buffers from /home/michael/opt/Xilinx/13.4/ISE_DS/PlanAhead/parts/xilinx/spartan6/spartan6lx/xc6slx16/ClockBuffers.xml
Loading package pin functions from /home/michael/opt/Xilinx/13.4/ISE_DS/PlanAhead/parts/xilinx/spartan6/PinFunctions.xml...
Loading package from /home/michael/opt/Xilinx/13.4/ISE_DS/PlanAhead/parts/xilinx/spartan6/spartan6lx/xc6slx16/csg324/Package.xml
Loading io standards from /home/michael/opt/Xilinx/13.4/ISE_DS/PlanAhead/./parts/xilinx/spartan6/IOStandards.xml
Loading device configuration modes from /home/michael/opt/Xilinx/13.4/ISE_DS/PlanAhead/parts/xilinx/spartan6/ConfigModes.xml
Loading list of drcs for the architecture : /home/michael/opt/Xilinx/13.4/ISE_DS/PlanAhead/./parts/xilinx/spartan6/drc.xml
Parsing UCF File [/home/michael/Documents/School/EC311/lab2/ALUSHOW.ucf]
Finished Parsing UCF File [/home/michael/Documents/School/EC311/lab2/ALUSHOW.ucf]
INFO: [PlanAhead-566] Unisim Transformation Summary:
No Unisim elements were transformed.open_rtl_design: Time (s): 20.520u 0.570s 28.760w. Memory (MB): 4537.992p 149.031g
exit
stop_gui
INFO: [PlanAhead-261] Exiting PlanAhead...
INFO: [Common-83] Releasing license: PlanAhead