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PROP_OverwriteSym=true |
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PROP_Simulator=ISim (VHDL/Verilog) |
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PROP_Top_Level_Module_Type=HDL |
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PROP_UserConstraintEditorPreference=Text Editor |
| PROP_intProjectCreationTimestamp=2012-02-15T15:29:59 |
PROP_intWbtProjectID=CFA30C52A63E43D8A2FABC7B29B0C236 |
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PROP_intWorkingDirLocWRTProjDir=Same |
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PROP_DevFamily=Spartan6 |
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PROP_DevFamilyPMName=spartan6 |
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FILE_UCF=1 |
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