diff options
Diffstat (limited to 'lab4.xise')
| -rw-r--r-- | lab4.xise | 66 |
1 files changed, 35 insertions, 31 deletions
@@ -12,12 +12,12 @@ <!-- Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved. --> </header> - <version xil_pn:ise_version="13.4" xil_pn:schema_version="2"/> + <version xil_pn:ise_version="13.3" xil_pn:schema_version="2"/> <files> <file xil_pn:name="Bin2BCD.v" xil_pn:type="FILE_VERILOG"> - <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/> - <association xil_pn:name="Implementation" xil_pn:seqID="1"/> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> + <association xil_pn:name="Implementation" xil_pn:seqID="7"/> </file> <file xil_pn:name="TEST_Bin2BCD.v" xil_pn:type="FILE_VERILOG"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> @@ -26,8 +26,8 @@ <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="2"/> </file> <file xil_pn:name="Increment.v" xil_pn:type="FILE_VERILOG"> - <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/> - <association xil_pn:name="Implementation" xil_pn:seqID="15"/> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> + <association xil_pn:name="Implementation" xil_pn:seqID="2"/> </file> <file xil_pn:name="TEST_Increment.v" xil_pn:type="FILE_VERILOG"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> @@ -36,12 +36,12 @@ <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="16"/> </file> <file xil_pn:name="debouncer.v" xil_pn:type="FILE_VERILOG"> - <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/> - <association xil_pn:name="Implementation" xil_pn:seqID="21"/> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> + <association xil_pn:name="Implementation" xil_pn:seqID="4"/> </file> <file xil_pn:name="BCD2Bin.v" xil_pn:type="FILE_VERILOG"> - <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/> - <association xil_pn:name="Implementation" xil_pn:seqID="22"/> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> + <association xil_pn:name="Implementation" xil_pn:seqID="8"/> </file> <file xil_pn:name="TEST_BCD2Bin.v" xil_pn:type="FILE_VERILOG"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> @@ -50,18 +50,18 @@ <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="23"/> </file> <file xil_pn:name="Countdown.v" xil_pn:type="FILE_VERILOG"> - <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/> - <association xil_pn:name="Implementation" xil_pn:seqID="27"/> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/> + <association xil_pn:name="Implementation" xil_pn:seqID="5"/> </file> <file xil_pn:name="TEST_Countdown.v" xil_pn:type="FILE_VERILOG"> - <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/> <association xil_pn:name="PostMapSimulation" xil_pn:seqID="28"/> <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="28"/> <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="28"/> </file> <file xil_pn:name="ClockDivider.v" xil_pn:type="FILE_VERILOG"> - <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/> - <association xil_pn:name="Implementation" xil_pn:seqID="32"/> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> + <association xil_pn:name="Implementation" xil_pn:seqID="6"/> </file> <file xil_pn:name="TEST_ClockDivider.v" xil_pn:type="FILE_VERILOG"> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> @@ -70,19 +70,19 @@ <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="33"/> </file> <file xil_pn:name="SevSegDisp.v" xil_pn:type="FILE_VERILOG"> - <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/> - <association xil_pn:name="Implementation" xil_pn:seqID="41"/> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> + <association xil_pn:name="Implementation" xil_pn:seqID="1"/> </file> <file xil_pn:name="DisplayController.v" xil_pn:type="FILE_VERILOG"> - <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/> - <association xil_pn:name="Implementation" xil_pn:seqID="42"/> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> + <association xil_pn:name="Implementation" xil_pn:seqID="3"/> </file> <file xil_pn:name="CountdownController.v" xil_pn:type="FILE_VERILOG"> - <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/> - <association xil_pn:name="Implementation" xil_pn:seqID="45"/> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> + <association xil_pn:name="Implementation" xil_pn:seqID="9"/> </file> <file xil_pn:name="Test_ContdownController.v" xil_pn:type="FILE_VERILOG"> - <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/> + <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/> <association xil_pn:name="PostMapSimulation" xil_pn:seqID="33"/> <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="33"/> <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="33"/> @@ -99,6 +99,9 @@ <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="46"/> <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="46"/> </file> + <file xil_pn:name="CountdownController.ucf" xil_pn:type="FILE_UCF"> + <association xil_pn:name="Implementation" xil_pn:seqID="0"/> + </file> </files> <properties> @@ -126,7 +129,7 @@ <property xil_pn:name="Change Device Speed To" xil_pn:value="-3" xil_pn:valueState="default"/> <property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-3" xil_pn:valueState="default"/> <property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/> - <property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="false" xil_pn:valueState="non-default"/> <property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/> @@ -144,9 +147,9 @@ <property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Create IEEE 1532 Configuration File spartan6" xil_pn:value="false" xil_pn:valueState="default"/> - <property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/> - <property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/> - <property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Create Logic Allocation File" xil_pn:value="true" xil_pn:valueState="non-default"/> + <property xil_pn:name="Create Mask File" xil_pn:value="true" xil_pn:valueState="non-default"/> + <property xil_pn:name="Create ReadBack Data Files" xil_pn:value="true" xil_pn:valueState="non-default"/> <property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/> <property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/> @@ -180,7 +183,7 @@ <property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Extra Cost Tables Map" xil_pn:value="0" xil_pn:valueState="default"/> <property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/> - <property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/> + <property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="JTAG Clock" xil_pn:valueState="non-default"/> <property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/> <property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/> <property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/> @@ -248,7 +251,6 @@ <property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/> <property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/> - <property xil_pn:name="MultiBoot: Insert IPROG CMD in the Bitfile spartan6" xil_pn:value="Enable" xil_pn:valueState="default"/> <property xil_pn:name="MultiBoot: Next Configuration Mode spartan6" xil_pn:value="001" xil_pn:valueState="default"/> <property xil_pn:name="MultiBoot: Starting Address for Golden Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/> <property xil_pn:name="MultiBoot: Starting Address for Next Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/> @@ -287,6 +289,7 @@ <property xil_pn:name="Package" xil_pn:value="csg324" xil_pn:valueState="default"/> <property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/> + <property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Place & Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/> <property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/> <property xil_pn:name="Place MultiBoot Settings into Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/> @@ -341,8 +344,8 @@ <property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/> <property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/> - <property xil_pn:name="Selected Module Instance Name" xil_pn:value="/Test_ContdownController/uut/dbA" xil_pn:valueState="non-default"/> - <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.debouncer" xil_pn:valueState="non-default"/> + <property xil_pn:name="Selected Module Instance Name" xil_pn:value="/TEST_Increment" xil_pn:valueState="non-default"/> + <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.TEST_Increment" xil_pn:valueState="non-default"/> <property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/> @@ -360,7 +363,7 @@ <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/> <property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/> <property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/> - <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.debouncer" xil_pn:valueState="default"/> + <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.TEST_Increment" xil_pn:valueState="default"/> <property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/> <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/> <property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/> @@ -368,6 +371,7 @@ <property xil_pn:name="Starting Placer Cost Table (1-100) Map spartan6" xil_pn:value="1" xil_pn:valueState="default"/> <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/> <property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/> + <property xil_pn:name="Target UCF File Name" xil_pn:value="CountdownController.ucf" xil_pn:valueState="non-default"/> <property xil_pn:name="Timing Mode Map" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/> <property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/> <property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/> @@ -410,7 +414,7 @@ <!-- --> <!-- The following properties are for internal use only. These should not be modified.--> <!-- --> - <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Module|Test_ContdownController" xil_pn:valueState="non-default"/> + <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Module|TEST_Countdown" xil_pn:valueState="non-default"/> <property xil_pn:name="PROP_DesignName" xil_pn:value="lab4" xil_pn:valueState="non-default"/> <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/> <property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/> |