From 11a0ed5a6e8af2e224caf1cb782829dfd8737b5e Mon Sep 17 00:00:00 2001 From: Michael Abed Date: Thu, 22 Mar 2012 16:14:11 -0400 Subject: updates --- .gitignore | 1 - BCD2Bin.v | 8 +- Bin2BCD.v | 6 +- ClockDivider.v | 2 +- Countdown.v | 52 +- CountdownController.v | 46 +- CountdownController_summary.html | 6 +- DisplayController.v | 6 +- Increment.v | 10 +- SevSegDisp.v | 26 +- TEST_Increment.v | 6 +- TEST_SevSegDisp.v | 4 +- Test_ContdownController_beh.prj | 11 - _xmsgs/pn_parser.xmsgs | 30 +- fuse.log | 72 +- fuse.xmsgs | 57 +- fuseRelaunch.cmd | 2 +- iseconfig/CountdownController.xreport | 6 +- iseconfig/lab4.projectmgr | 438 +++++++------ isim.cmd | 6 +- isim.log | 28 +- .../ISimEngine-DesignHierarchy.dbg | Bin 4679 -> 4504 bytes isim/TEST_Countdown_isim_beh.exe.sim/isimcrash.log | 0 .../TEST_Countdown_isim_beh.exe.sim/isimkernel.log | 57 +- isim/TEST_Countdown_isim_beh.exe.sim/netId.dat | Bin isim/TEST_Countdown_isim_beh.exe.sim/tmp_save/_1 | Bin 2743 -> 2512 bytes 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@@ reg [2:0] i = 0; reg [19:0] work; -always @ ( hun, ten, one ) begin +always @ ( hun, ten, one, bin ) begin work = {hun, ten, one, bin}; @@ -39,13 +39,13 @@ always @ ( hun, ten, one ) begin for (i = 0; i < 7; i = i + 1) begin work = work >> 1; if (work[19:16] >= 5) begin - work[19:16] = work[19:16] - 3; + work[19:16] = work[19:16] - 4'd3; end if (work[15:12] >= 5) begin - work[15:12] = work[15:12] - 3; + work[15:12] = work[15:12] - 4'd3; end if (work[11:8] >= 5) begin - work [11:8] = work[11:8] - 3; + work [11:8] = work[11:8] - 4'd3; end end diff --git a/Bin2BCD.v b/Bin2BCD.v index ce79f2b..403fc22 100644 --- a/Bin2BCD.v +++ b/Bin2BCD.v @@ -36,13 +36,13 @@ always @( bin ) begin for (i = 0; i < 7; i = i +1) begin work = work << 1; if (work[19:16] >= 5) begin - work[19:16] = work[19:16] + 3; + work[19:16] = work[19:16] + 4'd3; end if (work[15:12] >= 5) begin - work[15:12] = work[15:12] + 3; + work[15:12] = work[15:12] + 4'd3; end if (work[11:8] >= 5) begin - work[11:8] = work[11:8] + 3; + work[11:8] = work[11:8] + 4'd3; end end diff --git a/ClockDivider.v b/ClockDivider.v index 2447e7e..7ced5a7 100644 --- a/ClockDivider.v +++ b/ClockDivider.v @@ -36,7 +36,7 @@ always @(posedge clk_in or posedge rst) begin clk_out = ~clk_out; c = 0; end else begin - c = c + 1; + c = c + 24'd1; end diff --git a/Countdown.v b/Countdown.v index 78e4162..a8c7506 100644 --- a/Countdown.v +++ b/Countdown.v @@ -23,35 +23,43 @@ module Countdown( input rst, input start, input [7:0] init, - output [7:0] t + output [7:0] t, + output running ); reg [7:0] t; -reg running = 0; +reg running = 0; +reg [7:0] count; + +always @(posedge clk_1hz or posedge rst) begin + if (rst) + count <= 0; + else if (running) + count <= count + 1; + else + count <= 0; +end -always @(init) begin - if (!running) begin - t = init; - end else begin - t = t; - end -end - -always @(posedge clk_1hz) begin - if (running) begin - t <= t - 1; - end else begin - t <= init; - end -end +always @(posedge clk_1hz or posedge rst) begin + + if (rst) + t <= 0; + else //if (running) + t <= init - count; -always @(posedge start) begin - running = 1; end -always @(rst) begin - running = 0; - t = 0; +always @(posedge start or posedge rst) begin + + if (rst) + running <= 0; + else if (count == init) begin + running <= 0; + end else if (start) + running <= 1; + else + running <= running; + end endmodule diff --git a/CountdownController.v b/CountdownController.v index 35c84f9..626eef3 100644 --- a/CountdownController.v +++ b/CountdownController.v @@ -31,16 +31,20 @@ module CountdownController( reg [6:0] ssd; reg [3:0] AN; -wire [6:0] ssdo; -wire [3:0] ANo; +wire [6:0] ssd1; +wire [6:0] ssd2; +wire [3:0] AN1; +wire [3:0] AN2; // clocks wire seconds; wire dbclk; -wire dispclk; +wire dispclk; + +wire running; // buttons -wire a, b; +wire a, b, c; // bcd things wire [3:0] ad, bd; @@ -50,34 +54,36 @@ wire [3:0] ado, bdo, cdo; wire [7:0] init; wire [7:0] tout; -//ClockDivider dbc(.count(1_000_000), .rst(rst), .clk_in(clk), .clk_out(dbclk)); -//ClockDivider sec(.count(100_000_000), .rst(rst), .clk_in(clk), .clk_out(seconds)); -//ClockDivider dcc(.count(7_500_000), .rst(rst), .clk_in(clk), .clk_out(dispclk)); +ClockDivider dbc(.count(100), .rst(rst), .clk_in(clk), .clk_out(dbclk)); +ClockDivider sec(.count(100_000_000), .rst(rst), .clk_in(clk), .clk_out(seconds)); +ClockDivider dcc(.count(7_500_0), .rst(rst), .clk_in(clk), .clk_out(dispclk)); -ClockDivider dbc(.count(10), .rst(rst), .clk_in(clk), .clk_out(dbclk)); -ClockDivider sec(.count(100), .rst(rst), .clk_in(clk), .clk_out(seconds)); -ClockDivider dcc(.count(25), .rst(rst), .clk_in(clk), .clk_out(dispclk)); +//ClockDivider dbc(.count(24'd10), .rst(rst), .clk_in(clk), .clk_out(dbclk)); +//ClockDivider sec(.count(24'd100), .rst(rst), .clk_in(clk), .clk_out(seconds)); +//ClockDivider dcc(.count(24'd25), .rst(rst), .clk_in(clk), .clk_out(dispclk)); debouncer dbA(.dout(a), .din(btnA), .rst(rst), .clk_1M(dbclk)); debouncer dbB(.dout(b), .din(btnB), .rst(rst), .clk_1M(dbclk)); +debouncer dbC(.dout(c), .din(btnC), .rst(rst), .clk_1M(dbclk)); -Increment inc1(.value(ad), .btn(a)); -Increment inc2(.value(bd), .btn(b)); +Increment inc1(.value(ad), .btn(a), .rst(rst)); +Increment inc2(.value(bd), .btn(b), .rst(rst)); -//Increment inc1(.value(ad), .btn(btnA)); +//Increment inc1(.value(ad), .btn(btnA)); //Increment inc2(.value(bd), .btn(btnB)); -BCD2Bin bcd2b(.hun(0), .ten(ad), .one(bd), .bin(init)); +BCD2Bin bcd2b(.hun(4'd0), .ten(ad), .one(bd), .bin(init)); -Countdown cntdwn(.t(tout), .rst(rst), .init(init), .clk_1hz(seconds), .start(btnC)); +Countdown cntdwn(.t(tout), .running(running), .rst(rst), .init(init), .clk_1hz(seconds), .start(c)); Bin2BCD b2bcb(.hun(cdo), .ten(ado), .one(bdo), .bin(tout)); -DisplayController dispcont(.result(ssdo), .AN(ANo), .A(ado), .B(bdo), .clk_in(dispclk), .rst(rst)); - - -assign ssd = ssdo; -assign AN = ANo; +DisplayController dispcont1(.result(ssd1), .AN(AN1), .A(ado), .B(bdo), .clk_in(dispclk), .rst(rst)); +DisplayController dispcont2(.result(ssd2), .AN(AN2), .A(ad), .B(bd), .clk_in(dispclk), .rst(rst)); +always @(posedge clk) begin + ssd <= running ? ssd1 : ssd2; + AN <= running ? AN1 : AN2; +end endmodule diff --git a/CountdownController_summary.html b/CountdownController_summary.html index b9ce724..d2dc1c9 100644 --- a/CountdownController_summary.html +++ b/CountdownController_summary.html @@ -22,7 +22,7 @@   -Product Version:ISE 13.4 +Product Version:ISE 13.3   @@ -72,9 +72,9 @@  
- +
Secondary Reports [-]
Report NameStatusGenerated
ISIM Simulator LogCurrentWed Mar 21 13:14:04 2012
ISIM Simulator LogCurrentWed Mar 21 13:22:33 2012
-
Date Generated: 03/21/2012 - 13:43:14
+
Date Generated: 03/21/2012 - 17:32:54
\ No newline at end of file diff --git a/DisplayController.v b/DisplayController.v index 1ea2bf1..108d7a9 100644 --- a/DisplayController.v +++ b/DisplayController.v @@ -35,13 +35,13 @@ wire [6:0] ssd2; reg prev = 0; -SevSegDisp d1(.A(A), .out(ssd1)); -SevSegDisp d2(.A(B), .out(ssd2)); +SevSegDisp d1(.A(A), .result(ssd1)); +SevSegDisp d2(.A(B), .result(ssd2)); always @( posedge clk_in ) begin prev <= ~prev; result <= prev ? ssd1 : ssd2; - AN <= { 2'b11, prev, ~prev }; + AN <= { 2'b11, ~prev, prev }; end diff --git a/Increment.v b/Increment.v index b386d13..105a557 100644 --- a/Increment.v +++ b/Increment.v @@ -19,14 +19,18 @@ // ////////////////////////////////////////////////////////////////////////////////// module Increment( - input btn, + input btn, + input rst, output [3:0] value ); reg [3:0] value = 0; -always @ ( posedge btn ) begin - value = value == 9 ? 0 : value + 1; +always @ ( posedge btn or posedge rst) begin + if (rst) + value <= 0; + else + value <= value == 4'd9 ? 4'd0 : value + 4'd1; end endmodule diff --git a/SevSegDisp.v b/SevSegDisp.v index f0b6ee9..8d2c3b1 100644 --- a/SevSegDisp.v +++ b/SevSegDisp.v @@ -21,24 +21,24 @@ module SevSegDisp( input [3:0] A, - output [6:0] out + output [6:0] result ); -reg [6:0] out = 0; +reg [6:0] result = 0; always @ ( * ) begin case ( A ) - 4'b0000 : out = 7'b0000001; - 4'b0001 : out = 7'b1001111; - 4'b0010 : out = 7'b0010010; - 4'b0011 : out = 7'b0000110; - 4'b0100 : out = 7'b1001100; - 4'b0101 : out = 7'b0100100; - 4'b0110 : out = 7'b0100000; - 4'b0111 : out = 7'b0001111; - 4'b1000 : out = 7'b0000000; - 4'b1001 : out = 7'b0001100; - default : out = 7'b0011010; + 4'b0000 : result = 7'b0000001; + 4'b0001 : result = 7'b1001111; + 4'b0010 : result = 7'b0010010; + 4'b0011 : result = 7'b0000110; + 4'b0100 : result = 7'b1001100; + 4'b0101 : result = 7'b0100100; + 4'b0110 : result = 7'b0100000; + 4'b0111 : result = 7'b0001111; + 4'b1000 : result = 7'b0000000; + 4'b1001 : result = 7'b0001100; + default : result = 7'b0011010; endcase end diff --git a/TEST_Increment.v b/TEST_Increment.v index 2ff393a..894c734 100644 --- a/TEST_Increment.v +++ b/TEST_Increment.v @@ -25,7 +25,8 @@ module TEST_Increment; // Inputs - reg btn; + reg btn; + reg rst; // Outputs wire [3 :0] value; @@ -36,7 +37,8 @@ module TEST_Increment; // Instantiate the Unit Under Test (UUT) Increment uut ( - .btn(btn), + .btn(btn), + .rst(rst), .value(value) ); diff --git a/TEST_SevSegDisp.v b/TEST_SevSegDisp.v index a818547..e03bfae 100644 --- a/TEST_SevSegDisp.v +++ b/TEST_SevSegDisp.v @@ -28,12 +28,12 @@ module TEST_SevSegDisp; reg [3:0] A; // Outputs - wire [6:0] out; + wire [6:0] result; // Instantiate the Unit Under Test (UUT) SevSegDisp uut ( .A(A), - .out(out) + .result(result) ); reg [3:0] i = 0; initial begin diff --git a/Test_ContdownController_beh.prj b/Test_ContdownController_beh.prj deleted file mode 100644 index 9f8f6b9..0000000 --- a/Test_ContdownController_beh.prj +++ /dev/null @@ -1,11 +0,0 @@ -verilog work "SevSegDisp.v" -verilog work "Increment.v" -verilog work "DisplayController.v" -verilog work "debouncer.v" -verilog work "Countdown.v" -verilog work "ClockDivider.v" -verilog work "Bin2BCD.v" -verilog work "BCD2Bin.v" -verilog work "CountdownController.v" -verilog work "Test_ContdownController.v" -verilog work "/home/michael/opt/Xilinx/13.4/ISE_DS/ISE//verilog/src/glbl.v" diff --git a/_xmsgs/pn_parser.xmsgs b/_xmsgs/pn_parser.xmsgs index d1c52e5..446c254 100644 --- a/_xmsgs/pn_parser.xmsgs +++ b/_xmsgs/pn_parser.xmsgs @@ -1,15 +1,15 @@ - - - - - - - - - - -Analyzing Verilog file "/home/michael/Documents/School/EC311/lab4/Test_ContdownController.v" into library work - - - - + + + + + + + + + + +Analyzing Verilog file "X:/My Documents/ec311/ec311-lab4/Countdown.v" into library work + + + + diff --git a/fuse.log b/fuse.log index d9cd2af..dc0c31b 100644 --- a/fuse.log +++ b/fuse.log @@ -1,52 +1,20 @@ -Running: /home/michael/opt/Xilinx/13.4/ISE_DS/ISE/bin/lin64/unwrapped/fuse -intstyle ise -incremental -lib unisims_ver -lib unimacro_ver -lib xilinxcorelib_ver -lib secureip -o /home/michael/Documents/School/EC311/lab4/Test_ContdownController_isim_beh.exe -prj /home/michael/Documents/School/EC311/lab4/Test_ContdownController_beh.prj work.Test_ContdownController work.glbl -ISim O.87xd (signature 0x8ddf5b5d) -Number of CPUs detected in this system: 2 -Turning on mult-threading, number of parallel sub-compilation jobs: 4 -Determining compilation order of HDL files -Analyzing Verilog file "/home/michael/Documents/School/EC311/lab4/SevSegDisp.v" into library work -WARNING:HDLCompiler:751 - "/home/michael/Documents/School/EC311/lab4/SevSegDisp.v" Line 27: Redeclaration of ansi port out is not allowed -Analyzing Verilog file "/home/michael/Documents/School/EC311/lab4/Increment.v" into library work -WARNING:HDLCompiler:751 - "/home/michael/Documents/School/EC311/lab4/Increment.v" Line 26: Redeclaration of ansi port value is not allowed -Analyzing Verilog file "/home/michael/Documents/School/EC311/lab4/DisplayController.v" into library work -WARNING:HDLCompiler:751 - "/home/michael/Documents/School/EC311/lab4/DisplayController.v" Line 30: Redeclaration of ansi port AN is not allowed -WARNING:HDLCompiler:751 - "/home/michael/Documents/School/EC311/lab4/DisplayController.v" Line 31: Redeclaration of ansi port result is not allowed -Analyzing Verilog file "/home/michael/Documents/School/EC311/lab4/debouncer.v" into library work -Analyzing Verilog file "/home/michael/Documents/School/EC311/lab4/Countdown.v" into library work -WARNING:HDLCompiler:751 - "/home/michael/Documents/School/EC311/lab4/Countdown.v" Line 29: Redeclaration of ansi port t is not allowed -Analyzing Verilog file "/home/michael/Documents/School/EC311/lab4/ClockDivider.v" into library work -WARNING:HDLCompiler:751 - "/home/michael/Documents/School/EC311/lab4/ClockDivider.v" Line 28: Redeclaration of ansi port clk_out is not allowed -Analyzing Verilog file "/home/michael/Documents/School/EC311/lab4/Bin2BCD.v" into library work -WARNING:HDLCompiler:751 - "/home/michael/Documents/School/EC311/lab4/Bin2BCD.v" Line 28: Redeclaration of ansi port one is not allowed -Analyzing Verilog file "/home/michael/Documents/School/EC311/lab4/BCD2Bin.v" into library work -WARNING:HDLCompiler:751 - "/home/michael/Documents/School/EC311/lab4/BCD2Bin.v" Line 28: Redeclaration of ansi port bin is not allowed -Analyzing Verilog file "/home/michael/Documents/School/EC311/lab4/CountdownController.v" into library work -WARNING:HDLCompiler:751 - "/home/michael/Documents/School/EC311/lab4/CountdownController.v" Line 31: Redeclaration of ansi port ssd is not allowed -WARNING:HDLCompiler:751 - "/home/michael/Documents/School/EC311/lab4/CountdownController.v" Line 32: Redeclaration of ansi port AN is not allowed -Analyzing Verilog file "/home/michael/Documents/School/EC311/lab4/Test_ContdownController.v" into library work -Analyzing Verilog file "/home/michael/opt/Xilinx/13.4/ISE_DS/ISE//verilog/src/glbl.v" into library work -Starting static elaboration -WARNING:HDLCompiler:189 - "/home/michael/Documents/School/EC311/lab4/CountdownController.v" Line 54: Size mismatch in connection of port . Formal port size is 24-bit while actual signal size is 32-bit. -WARNING:HDLCompiler:189 - "/home/michael/Documents/School/EC311/lab4/CountdownController.v" Line 55: Size mismatch in connection of port . Formal port size is 24-bit while actual signal size is 32-bit. -WARNING:HDLCompiler:189 - "/home/michael/Documents/School/EC311/lab4/CountdownController.v" Line 53: Size mismatch in connection of port . Formal port size is 24-bit while actual signal size is 32-bit. -WARNING:HDLCompiler:189 - "/home/michael/Documents/School/EC311/lab4/CountdownController.v" Line 66: Size mismatch in connection of port . Formal port size is 4-bit while actual signal size is 32-bit. -Completed static elaboration -Fuse Memory Usage: 95008 KB -Fuse CPU Usage: 1560 ms -Compiling module ClockDivider -Compiling module debouncer -Compiling module Increment -Compiling module BCD2Bin -Compiling module Countdown -Compiling module Bin2BCD -Compiling module SevSegDisp -Compiling module DisplayController -Compiling module CountdownController -Compiling module Test_ContdownController -Compiling module glbl -Time Resolution for simulation is 1ps. -Waiting for 8 sub-compilation(s) to finish... -Compiled 11 Verilog Units -Built simulation executable /home/michael/Documents/School/EC311/lab4/Test_ContdownController_isim_beh.exe -Fuse Memory Usage: 393132 KB -Fuse CPU Usage: 1610 ms -GCC CPU Usage: 1250 ms +Running: C:\Xilinx\13.3\ISE_DS\ISE\bin\nt64\unwrapped\fuse.exe -intstyle ise -incremental -lib unisims_ver -lib unimacro_ver -lib xilinxcorelib_ver -lib secureip -o X:/My Documents/ec311/ec311-lab4/TEST_Countdown_isim_beh.exe -prj X:/My Documents/ec311/ec311-lab4/TEST_Countdown_beh.prj work.TEST_Countdown work.glbl +ISim O.76xd (signature 0xc3576ebc) +Number of CPUs detected in this system: 2 +Turning on mult-threading, number of parallel sub-compilation jobs: 4 +Determining compilation order of HDL files +Analyzing Verilog file "X:/My Documents/ec311/ec311-lab4/Countdown.v" into library work +WARNING:HDLCompiler:751 - "X:/My Documents/ec311/ec311-lab4/Countdown.v" Line 29: Redeclaration of ansi port t is not allowed +Analyzing Verilog file "X:/My Documents/ec311/ec311-lab4/TEST_Countdown.v" into library work +Analyzing Verilog file "C:/Xilinx/13.3/ISE_DS/ISE//verilog/src/glbl.v" into library work +Starting static elaboration +Completed static elaboration +Compiling module Countdown +Compiling module TEST_Countdown +Compiling module glbl +Time Resolution for simulation is 1ps. +Waiting for 1 sub-compilation(s) to finish... +Compiled 3 Verilog Units +Built simulation executable X:/My Documents/ec311/ec311-lab4/TEST_Countdown_isim_beh.exe +Fuse Memory Usage: 26940 KB +Fuse CPU Usage: 467 ms diff --git a/fuse.xmsgs b/fuse.xmsgs old mode 100644 new mode 100755 index 39e40a2..c3f8604 --- a/fuse.xmsgs +++ b/fuse.xmsgs @@ -1,51 +1,12 @@ - - + + -"/home/michael/Documents/School/EC311/lab4/SevSegDisp.v" Line 27: Redeclaration of ansi port out is not allowed - - -"/home/michael/Documents/School/EC311/lab4/Increment.v" Line 26: Redeclaration of ansi port value is not allowed - - -"/home/michael/Documents/School/EC311/lab4/DisplayController.v" Line 30: Redeclaration of ansi port AN is not allowed - - -"/home/michael/Documents/School/EC311/lab4/DisplayController.v" Line 31: Redeclaration of ansi port result is not allowed - - -"/home/michael/Documents/School/EC311/lab4/Countdown.v" Line 29: Redeclaration of ansi port t is not allowed - - -"/home/michael/Documents/School/EC311/lab4/ClockDivider.v" Line 28: Redeclaration of ansi port clk_out is not allowed - - -"/home/michael/Documents/School/EC311/lab4/Bin2BCD.v" Line 28: Redeclaration of ansi port one is not allowed - - -"/home/michael/Documents/School/EC311/lab4/BCD2Bin.v" Line 28: Redeclaration of ansi port bin is not allowed - - -"/home/michael/Documents/School/EC311/lab4/CountdownController.v" Line 31: Redeclaration of ansi port ssd is not allowed - - -"/home/michael/Documents/School/EC311/lab4/CountdownController.v" Line 32: Redeclaration of ansi port AN is not allowed - - -"/home/michael/Documents/School/EC311/lab4/CountdownController.v" Line 54: Size mismatch in connection of port <count>. Formal port size is 24-bit while actual signal size is 32-bit. - - -"/home/michael/Documents/School/EC311/lab4/CountdownController.v" Line 55: Size mismatch in connection of port <count>. Formal port size is 24-bit while actual signal size is 32-bit. - - -"/home/michael/Documents/School/EC311/lab4/CountdownController.v" Line 53: Size mismatch in connection of port <count>. Formal port size is 24-bit while actual signal size is 32-bit. - - -"/home/michael/Documents/School/EC311/lab4/CountdownController.v" Line 66: Size mismatch in connection of port <hun>. Formal port size is 4-bit while actual signal size is 32-bit. - +"X:/My Documents/ec311/ec311-lab4/Countdown.v" Line 29: Redeclaration of ansi port t is not allowed + - + diff --git a/fuseRelaunch.cmd b/fuseRelaunch.cmd index 2314a76..d506760 100644 --- a/fuseRelaunch.cmd +++ b/fuseRelaunch.cmd @@ -1 +1 @@ --intstyle "ise" -incremental -lib "unisims_ver" -lib "unimacro_ver" -lib "xilinxcorelib_ver" -lib "secureip" -o "/home/michael/Documents/School/EC311/lab4/Test_ContdownController_isim_beh.exe" -prj "/home/michael/Documents/School/EC311/lab4/Test_ContdownController_beh.prj" "work.Test_ContdownController" "work.glbl" +-intstyle "ise" -incremental -lib "unisims_ver" -lib "unimacro_ver" -lib "xilinxcorelib_ver" -lib "secureip" -o "X:/My Documents/ec311/ec311-lab4/TEST_Countdown_isim_beh.exe" -prj "X:/My Documents/ec311/ec311-lab4/TEST_Countdown_beh.prj" "work.TEST_Countdown" "work.glbl" diff --git a/iseconfig/CountdownController.xreport b/iseconfig/CountdownController.xreport index f2c2a7b..38c9927 100644 --- a/iseconfig/CountdownController.xreport +++ b/iseconfig/CountdownController.xreport @@ -1,11 +1,11 @@
- 2012-03-21T13:31:48 + 2012-03-21T17:32:54 CountdownController Unknown - /home/michael/Documents/School/EC311/lab4/iseconfig/CountdownController.xreport - /home/michael/Documents/School/EC311/lab4/ + X:/My Documents/ec311/ec311-lab4/iseconfig/CountdownController.xreport + X:/My Documents/ec311/ec311-lab4\ 2012-03-17T11:17:09 false
diff --git a/iseconfig/lab4.projectmgr b/iseconfig/lab4.projectmgr index 325fe45..3a7193a 100644 --- a/iseconfig/lab4.projectmgr +++ b/iseconfig/lab4.projectmgr @@ -1,212 +1,226 @@ - - - - - - - - - 2 - /CountdownController |home|michael|Documents|School|EC311|lab4|CountdownController.v/DisplayController - DisplayController - - - cntdwn - Countdown (/home/michael/Documents/School/EC311/lab4/Countdown.v) - - 0 - 0 - 000000ff0000000000000001000000010000000000000000000000000000000002020000000100000001000000640000017a000000020000000000000000000000000200000064ffffffff0000008100000003000000020000017a0000000100000003000000000000000100000003 - true - cntdwn - Countdown (/home/michael/Documents/School/EC311/lab4/Countdown.v) - - - - 1 - Design Utilities - - - - - 0 - 0 - 000000ff00000000000000010000000100000000000000000000000000000000000000000000000183000000010000000100000000000000000000000064ffffffff000000810000000000000001000001830000000100000000 - false - - - - - 1 - - - debouncer.v - - 0 - 0 - 000000ff00000000000000010000000000000000010000000000000000000000000000000000000287000000040101000100000000000000000000000064ffffffff0000008100000000000000040000004a0000000100000000000000640000000100000000000000790000000100000000000001600000000100000000 - false - debouncer.v - - - - 1 - work - - - 0 - 0 - 000000ff00000000000000010000000000000000010000000000000000000000000000000000000117000000010001000100000000000000000000000064ffffffff000000810000000000000001000001170000000100000000 - false - work - - - - 1 - Configure Target Device - Implement Design/Map - Implement Design/Place & Route/Back-annotate Pin Locations - Implement Design/Place & Route/Generate IBIS Model - Implement Design/Place & Route/Generate Post-Place & Route Static Timing - Implement Design/Translate - User Constraints - - - - - 0 - 0 - 000000ff00000000000000010000000100000000000000000000000000000000000000000000000183000000010000000100000000000000000000000064ffffffff000000810000000000000001000001830000000100000000 - false - - - - - 2 - /CountdownController |home|michael|Documents|School|EC311|lab4|CountdownController.v/DisplayController - DisplayController - /DisplayController |home|michael|Documents|School|EC311|lab4|DisplayController.v - /TEST_BCD2Bin |home|michael|Documents|School|EC311|lab4|TEST_BCD2Bin.v - /TEST_Bin2BCD |home|michael|Documents|School|EC311|lab4|TEST_Bin2BCD.v - /TEST_ClockDivider |home|michael|Documents|School|EC311|lab4|TEST_ClockDivider.v - /TEST_DisplayController |home|michael|Documents|School|EC311|lab4|TEST_DisplayController.v - /TEST_DisplayController |home|michael|Documents|School|EC311|lab4|TEST_DisplayController.v/uut - DisplayController - /TEST_Increment |home|michael|Documents|School|EC311|lab4|TEST_Increment.v - /TEST_SevSegDisp |home|michael|Documents|School|EC311|lab4|TEST_SevSegDisp.v - - - Test_ContdownController (/home/michael/Documents/School/EC311/lab4/Test_ContdownController.v) - - 4 - 0 - 000000ff0000000000000001000000010000000000000000000000000000000002020000000100000001000000640000018f000000020000000000000000000000000200000064ffffffff0000008100000003000000020000018f0000000100000003000000000000000100000003 - true - Test_ContdownController (/home/michael/Documents/School/EC311/lab4/Test_ContdownController.v) - - - - 1 - Design Utilities/Compile HDL Simulation Libraries - - - - - 0 - 0 - 000000ff00000000000000010000000100000000000000000000000000000000000000000000000183000000010000000100000000000000000000000064ffffffff000000810000000000000001000001830000000100000000 - false - - - - - 1 - - - Simulate Behavioral Model - - 0 - 0 - 000000ff00000000000000010000000100000000000000000000000000000000000000000000000183000000010000000100000000000000000000000064ffffffff000000810000000000000001000001830000000100000000 - false - Simulate Behavioral Model - - - - 2 - /TEST_Bin2BCD |home|michael|Documents|School|EC311|lab4|TEST_Bin2BCD.v - - - Unassigned User Library Modules - - 0 - 0 - 000000ff0000000000000001000000010000000000000000000000000000000002020000000100000001000000640000010d000000020000000000000000000000000200000064ffffffff0000008100000003000000020000010d0000000100000003000000000000000100000003 - false - Unassigned User Library Modules - - - - 1 - - - Compile HDL Simulation Libraries - - 0 - 0 - 000000ff00000000000000010000000100000000000000000000000000000000000000000000000183000000010000000100000000000000000000000064ffffffff000000810000000000000001000001830000000100000000 - false - Compile HDL Simulation Libraries - - - - 2 - /TEST_Bin2BCD |home|michael|Documents|School|EC311|lab4|TEST_Bin2BCD.v - - - Unassigned User Library Modules - - 0 - 0 - 000000ff0000000000000001000000010000000000000000000000000000000002020000000100000001000000640000010d000000020000000000000000000000000200000064ffffffff0000008100000003000000020000010d0000000100000003000000000000000100000003 - false - Unassigned User Library Modules - - - - 1 - - - Compile HDL Simulation Libraries - - 0 - 0 - 000000ff00000000000000010000000100000000000000000000000000000000000000000000000183000000010000000100000000000000000000000064ffffffff000000810000000000000001000001830000000100000000 - false - Compile HDL Simulation Libraries - - - - 2 - /TEST_Bin2BCD |home|michael|Documents|School|EC311|lab4|TEST_Bin2BCD.v - - - Unassigned User Library Modules - - 0 - 0 - 000000ff0000000000000001000000010000000000000000000000000000000002020000000100000001000000640000010d000000020000000000000000000000000200000064ffffffff0000008100000003000000020000010d0000000100000003000000000000000100000003 - false - Unassigned User Library Modules - - - - 1 - - - Compile HDL Simulation Libraries - - 0 - 0 - 000000ff00000000000000010000000100000000000000000000000000000000000000000000000183000000010000000100000000000000000000000064ffffffff000000810000000000000001000001830000000100000000 - false - Compile HDL Simulation Libraries - - 000000ff00000000000000020000010a0000009d01000000060100000002 - Behavioral Simulation - + + + + + + + + + 2 + /CountdownController |home|michael|Documents|School|EC311|lab4|CountdownController.v/DisplayController - DisplayController + + + CountdownController (X:/My Documents/ec311/ec311-lab4/CountdownController.v) + + 0 + 0 + 000000ff00000000000000010000000100000000000000000000000000000000020200000001000000010000006400000160000000020000000000000000000000000200000064ffffffff000000810000000300000002000001600000000100000003000000000000000100000003 + true + CountdownController (X:/My Documents/ec311/ec311-lab4/CountdownController.v) + + + + 1 + Design Utilities + + + + + 0 + 0 + 000000ff00000000000000010000000100000000000000000000000000000000000000000000000183000000010000000100000000000000000000000064ffffffff000000810000000000000001000001830000000100000000 + false + + + + + 1 + + + debouncer.v + + 0 + 0 + 000000ff00000000000000010000000000000000010000000000000000000000000000000000000263000000040101000100000000000000000000000064ffffffff0000008100000000000000040000004a00000001000000000000006400000001000000000000007900000001000000000000013c0000000100000000 + false + debouncer.v + + + + 1 + work + + + 0 + 0 + 000000ff00000000000000010000000000000000010000000000000000000000000000000000000263000000010001000100000000000000000000000064ffffffff000000810000000000000001000002630000000100000000 + false + work + + + + 1 + Implement Design/Map + Implement Design/Place & Route + Implement Design/Place & Route/Back-annotate Pin Locations + Implement Design/Place & Route/Generate IBIS Model + Implement Design/Place & Route/Generate Post-Place & Route Static Timing + Implement Design/Translate + Synthesize - XST + + + Generate Programming File + + 7 + 0 + 000000ff000000000000000100000001000000000000000000000000000000000000000000000000e7000000010000000100000000000000000000000064ffffffff000000810000000000000001000000e70000000100000000 + false + Generate Programming File + + + + 2 + /CountdownController |home|michael|Documents|School|EC311|lab4|CountdownController.v/DisplayController - DisplayController + /DisplayController |home|michael|Documents|School|EC311|lab4|DisplayController.v + /TEST_BCD2Bin |home|michael|Documents|School|EC311|lab4|TEST_BCD2Bin.v + /TEST_Bin2BCD |home|michael|Documents|School|EC311|lab4|TEST_Bin2BCD.v + /TEST_ClockDivider |home|michael|Documents|School|EC311|lab4|TEST_ClockDivider.v + /TEST_DisplayController |home|michael|Documents|School|EC311|lab4|TEST_DisplayController.v + /TEST_DisplayController |home|michael|Documents|School|EC311|lab4|TEST_DisplayController.v/uut - DisplayController + /TEST_Increment |home|michael|Documents|School|EC311|lab4|TEST_Increment.v + /TEST_SevSegDisp |home|michael|Documents|School|EC311|lab4|TEST_SevSegDisp.v + + + TEST_Increment (X:/My Documents/ec311/ec311-lab4/TEST_Increment.v) + + 19 + 120 + 000000ff00000000000000010000000100000000000000000000000000000000020200000001000000010000006400000170000000020000000000000000000000000200000064ffffffff000000810000000300000002000001700000000100000003000000000000000100000003 + true + TEST_Increment (X:/My Documents/ec311/ec311-lab4/TEST_Increment.v) + + + + 1 + Design Utilities/Compile HDL Simulation Libraries + + + + + 0 + 0 + 000000ff000000000000000100000001000000000000000000000000000000000000000000000000f8000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f80000000100000000 + false + + + + + 1 + + + + + 0 + 0 + 000000ff000000000000000100000001000000000000000000000000000000000000000000000000f8000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f80000000100000000 + false + + + + + 2 + /TEST_Bin2BCD |home|michael|Documents|School|EC311|lab4|TEST_Bin2BCD.v + + + Unassigned User Library Modules + + 0 + 0 + 000000ff0000000000000001000000010000000000000000000000000000000002020000000100000001000000640000010d000000020000000000000000000000000200000064ffffffff0000008100000003000000020000010d0000000100000003000000000000000100000003 + false + Unassigned User Library Modules + + + + 1 + + + Compile HDL Simulation Libraries + + 0 + 0 + 000000ff00000000000000010000000100000000000000000000000000000000000000000000000183000000010000000100000000000000000000000064ffffffff000000810000000000000001000001830000000100000000 + false + Compile HDL Simulation Libraries + + + + 2 + /TEST_Bin2BCD |home|michael|Documents|School|EC311|lab4|TEST_Bin2BCD.v + + + Unassigned User Library Modules + + 0 + 0 + 000000ff0000000000000001000000010000000000000000000000000000000002020000000100000001000000640000010d000000020000000000000000000000000200000064ffffffff00000081000000