From 2ac48fa0e44016a6cb49cab84a154eb7ec2dcab4 Mon Sep 17 00:00:00 2001 From: Michael Abed Date: Wed, 21 Mar 2012 13:17:47 -0400 Subject: Initial Commit --- .gitignore | 4 + BCD2Bin.v | 58 ++ Bin2BCD.v | 56 ++ Bin2BCD_beh.prj | 2 + Bin2BCD_summary.html | 79 +++ ClockDivider.v | 47 ++ Countdown.v | 57 ++ CountdownController.v | 79 +++ CountdownController_summary.html | 80 +++ DisplayController.v | 48 ++ DisplayController_summary.html | 80 +++ Increment.v | 32 + SevSegDisp.v | 45 ++ SevSegDisp_stx_beh.prj | 2 + TEST_BCD2Bin.v | 61 ++ TEST_Bin2BCD.v | 61 ++ TEST_Bin2BCD_stx_beh.prj | 3 + TEST_ClockDivider.v | 65 ++ TEST_Countdown.v | 70 ++ TEST_DisplayController.v | 71 ++ TEST_DisplayController_stx_beh.prj | 5 + TEST_Increment.v | 61 ++ TEST_SevSegDisp.v | 55 ++ Test_ContdownController.v | 94 +++ Test_ContdownController_beh.prj | 11 + _xmsgs/pn_parser.xmsgs | 15 + clockdiv.wcfg | 36 + countdown.wcfg | 40 ++ debouncer.v | 56 ++ fuse.log | 52 ++ fuse.xmsgs | 51 ++ fuseRelaunch.cmd | 1 + iseconfig/Bin2BCD.xreport | 215 ++++++ iseconfig/CountdownController.xreport | 215 ++++++ iseconfig/DisplayController.xreport | 215 ++++++ iseconfig/lab4.projectmgr | 213 ++++++ isim.cmd | 3 + isim.log | 18 + .../ISimEngine-DesignHierarchy.dbg | Bin 0 -> 4679 bytes isim/TEST_Countdown_isim_beh.exe.sim/isimcrash.log | 0 .../TEST_Countdown_isim_beh.exe.sim/isimkernel.log | 29 + isim/TEST_Countdown_isim_beh.exe.sim/netId.dat | Bin 0 -> 76 bytes isim/TEST_Countdown_isim_beh.exe.sim/tmp_save/_1 | Bin 0 -> 2743 bytes .../work/TEST_Countdown_isim_beh.exe_main.c | 36 + .../work/TEST_Countdown_isim_beh.exe_main.lin64.o | Bin 0 -> 2432 bytes .../work/m_01236816096418509971_3448823162.c | 329 ++++++++++ .../work/m_01236816096418509971_3448823162.didat | Bin 0 -> 3364 bytes .../work/m_01236816096418509971_3448823162.lin64.o | Bin 0 -> 5496 bytes .../work/m_06453055231304268951_4281377536.c | 279 ++++++++ .../work/m_06453055231304268951_4281377536.didat | Bin 0 -> 3080 bytes .../work/m_06453055231304268951_4281377536.lin64.o | Bin 0 -> 5264 bytes .../work/m_16541823861846354283_2073120511.c | 337 ++++++++++ .../work/m_16541823861846354283_2073120511.didat | Bin 0 -> 5556 bytes .../work/m_16541823861846354283_2073120511.lin64.o | Bin 0 -> 5216 bytes .../ISimEngine-DesignHierarchy.dbg | Bin 0 -> 13768 bytes .../isimcrash.log | 0 .../isimkernel.log | 29 + .../netId.dat | Bin 0 -> 108 bytes .../tmp_save/_1 | Bin 0 -> 9766 bytes .../Test_ContdownController_isim_beh.exe_main.c | 44 ++ ...st_ContdownController_isim_beh.exe_main.lin64.o | Bin 0 -> 3264 bytes .../work/m_01832328269938973087_1606112044.c | 205 ++++++ .../work/m_01832328269938973087_1606112044.didat | Bin 0 -> 2428 bytes .../work/m_01832328269938973087_1606112044.lin64.o | Bin 0 -> 5920 bytes .../work/m_06185630164696979556_3598138731.c | 718 ++++++++++++++++++++ .../work/m_06185630164696979556_3598138731.didat | Bin 0 -> 3204 bytes .../work/m_06185630164696979556_3598138731.lin64.o | Bin 0 -> 7144 bytes .../work/m_06453055231304268951_4281377536.c | 279 ++++++++ .../work/m_06453055231304268951_4281377536.didat | Bin 0 -> 3088 bytes .../work/m_06453055231304268951_4281377536.lin64.o | Bin 0 -> 5264 bytes .../work/m_08578567565259243700_1151371814.c | 192 ++++++ .../work/m_08578567565259243700_1151371814.didat | Bin 0 -> 10888 bytes .../work/m_08578567565259243700_1151371814.lin64.o | Bin 0 -> 3976 bytes .../work/m_09461933616065074075_2531671071.c | 273 ++++++++ .../work/m_09461933616065074075_2531671071.didat | Bin 0 -> 2680 bytes .../work/m_09461933616065074075_2531671071.lin64.o | Bin 0 -> 4224 bytes .../work/m_09637473393135046702_3413554552.c | 722 +++++++++++++++++++++ .../work/m_09637473393135046702_3413554552.didat | Bin 0 -> 3904 bytes .../work/m_09637473393135046702_3413554552.lin64.o | Bin 0 -> 8800 bytes .../work/m_14079594305330756291_2618506667.c | 590 +++++++++++++++++ .../work/m_14079594305330756291_2618506667.didat | Bin 0 -> 2732 bytes .../work/m_14079594305330756291_2618506667.lin64.o | Bin 0 -> 7672 bytes .../work/m_14181161885881575918_3845763652.c | 249 +++++++ .../work/m_14181161885881575918_3845763652.didat | Bin 0 -> 3664 bytes .../work/m_14181161885881575918_3845763652.lin64.o | Bin 0 -> 3776 bytes .../work/m_14878824473863214981_2647877144.c | 203 ++++++ .../work/m_14878824473863214981_2647877144.didat | Bin 0 -> 2376 bytes .../work/m_14878824473863214981_2647877144.lin64.o | Bin 0 -> 3344 bytes .../work/m_16541823861846354283_2073120511.c | 337 ++++++++++ .../work/m_16541823861846354283_2073120511.didat | Bin 0 -> 5564 bytes .../work/m_16541823861846354283_2073120511.lin64.o | Bin 0 -> 5216 bytes .../work/m_17579661360444318263_0092613024.c | 538 +++++++++++++++ .../work/m_17579661360444318263_0092613024.didat | Bin 0 -> 2792 bytes .../work/m_17579661360444318263_0092613024.lin64.o | Bin 0 -> 6880 bytes isim/isim_usage_statistics.html | 16 + isim/lockfile | 0 isim/pn_info | 1 + isim/work/@b@c@d2@bin.sdb | Bin 0 -> 4984 bytes isim/work/@bin2@b@c@d.sdb | Bin 0 -> 5420 bytes isim/work/@clock@divider.sdb | Bin 0 -> 2521 bytes isim/work/@countdown.sdb | Bin 0 -> 3310 bytes isim/work/@countdown@controller.sdb | Bin 0 -> 6830 bytes isim/work/@display@controller.sdb | Bin 0 -> 3306 bytes isim/work/@increment.sdb | Bin 0 -> 1538 bytes isim/work/@sev@seg@disp.sdb | Bin 0 -> 2916 bytes isim/work/@test_@contdown@controller.sdb | Bin 0 -> 6172 bytes isim/work/debouncer.sdb | Bin 0 -> 4503 bytes isim/work/glbl.sdb | Bin 0 -> 5478 bytes lab4.gise | 135 ++++ lab4.xise | 441 +++++++++++++ xilinxsim.ini | 1 + 111 files changed, 8339 insertions(+) create mode 100644 .gitignore create mode 100644 BCD2Bin.v create mode 100644 Bin2BCD.v create mode 100644 Bin2BCD_beh.prj create mode 100644 Bin2BCD_summary.html create mode 100644 ClockDivider.v create mode 100644 Countdown.v create mode 100644 CountdownController.v create mode 100644 CountdownController_summary.html create mode 100644 DisplayController.v create mode 100644 DisplayController_summary.html create mode 100644 Increment.v create mode 100644 SevSegDisp.v create mode 100644 SevSegDisp_stx_beh.prj create mode 100644 TEST_BCD2Bin.v create mode 100644 TEST_Bin2BCD.v create mode 100644 TEST_Bin2BCD_stx_beh.prj create mode 100644 TEST_ClockDivider.v create mode 100644 TEST_Countdown.v create mode 100644 TEST_DisplayController.v create mode 100644 TEST_DisplayController_stx_beh.prj create mode 100644 TEST_Increment.v create mode 100644 TEST_SevSegDisp.v create mode 100644 Test_ContdownController.v create mode 100644 Test_ContdownController_beh.prj create mode 100644 _xmsgs/pn_parser.xmsgs create mode 100644 clockdiv.wcfg create mode 100644 countdown.wcfg create mode 100644 debouncer.v create mode 100644 fuse.log create mode 100644 fuse.xmsgs create mode 100644 fuseRelaunch.cmd create mode 100644 iseconfig/Bin2BCD.xreport create mode 100644 iseconfig/CountdownController.xreport create mode 100644 iseconfig/DisplayController.xreport create mode 100644 iseconfig/lab4.projectmgr create mode 100644 isim.cmd create mode 100644 isim.log create mode 100644 isim/TEST_Countdown_isim_beh.exe.sim/ISimEngine-DesignHierarchy.dbg create mode 100644 isim/TEST_Countdown_isim_beh.exe.sim/isimcrash.log create mode 100644 isim/TEST_Countdown_isim_beh.exe.sim/isimkernel.log create mode 100644 isim/TEST_Countdown_isim_beh.exe.sim/netId.dat create mode 100644 isim/TEST_Countdown_isim_beh.exe.sim/tmp_save/_1 create mode 100644 isim/TEST_Countdown_isim_beh.exe.sim/work/TEST_Countdown_isim_beh.exe_main.c create mode 100644 isim/TEST_Countdown_isim_beh.exe.sim/work/TEST_Countdown_isim_beh.exe_main.lin64.o create mode 100644 isim/TEST_Countdown_isim_beh.exe.sim/work/m_01236816096418509971_3448823162.c create mode 100644 isim/TEST_Countdown_isim_beh.exe.sim/work/m_01236816096418509971_3448823162.didat create mode 100644 isim/TEST_Countdown_isim_beh.exe.sim/work/m_01236816096418509971_3448823162.lin64.o create mode 100644 isim/TEST_Countdown_isim_beh.exe.sim/work/m_06453055231304268951_4281377536.c create mode 100644 isim/TEST_Countdown_isim_beh.exe.sim/work/m_06453055231304268951_4281377536.didat create mode 100644 isim/TEST_Countdown_isim_beh.exe.sim/work/m_06453055231304268951_4281377536.lin64.o create mode 100644 isim/TEST_Countdown_isim_beh.exe.sim/work/m_16541823861846354283_2073120511.c create mode 100644 isim/TEST_Countdown_isim_beh.exe.sim/work/m_16541823861846354283_2073120511.didat create mode 100644 isim/TEST_Countdown_isim_beh.exe.sim/work/m_16541823861846354283_2073120511.lin64.o create mode 100644 isim/Test_ContdownController_isim_beh.exe.sim/ISimEngine-DesignHierarchy.dbg create mode 100644 isim/Test_ContdownController_isim_beh.exe.sim/isimcrash.log create mode 100644 isim/Test_ContdownController_isim_beh.exe.sim/isimkernel.log create mode 100644 isim/Test_ContdownController_isim_beh.exe.sim/netId.dat create mode 100644 isim/Test_ContdownController_isim_beh.exe.sim/tmp_save/_1 create mode 100644 isim/Test_ContdownController_isim_beh.exe.sim/work/Test_ContdownController_isim_beh.exe_main.c create mode 100644 isim/Test_ContdownController_isim_beh.exe.sim/work/Test_ContdownController_isim_beh.exe_main.lin64.o create mode 100644 isim/Test_ContdownController_isim_beh.exe.sim/work/m_01832328269938973087_1606112044.c create mode 100644 isim/Test_ContdownController_isim_beh.exe.sim/work/m_01832328269938973087_1606112044.didat create mode 100644 isim/Test_ContdownController_isim_beh.exe.sim/work/m_01832328269938973087_1606112044.lin64.o create mode 100644 isim/Test_ContdownController_isim_beh.exe.sim/work/m_06185630164696979556_3598138731.c create mode 100644 isim/Test_ContdownController_isim_beh.exe.sim/work/m_06185630164696979556_3598138731.didat create mode 100644 isim/Test_ContdownController_isim_beh.exe.sim/work/m_06185630164696979556_3598138731.lin64.o create mode 100644 isim/Test_ContdownController_isim_beh.exe.sim/work/m_06453055231304268951_4281377536.c create mode 100644 isim/Test_ContdownController_isim_beh.exe.sim/work/m_06453055231304268951_4281377536.didat create mode 100644 isim/Test_ContdownController_isim_beh.exe.sim/work/m_06453055231304268951_4281377536.lin64.o create mode 100644 isim/Test_ContdownController_isim_beh.exe.sim/work/m_08578567565259243700_1151371814.c create mode 100644 isim/Test_ContdownController_isim_beh.exe.sim/work/m_08578567565259243700_1151371814.didat create mode 100644 isim/Test_ContdownController_isim_beh.exe.sim/work/m_08578567565259243700_1151371814.lin64.o create mode 100644 isim/Test_ContdownController_isim_beh.exe.sim/work/m_09461933616065074075_2531671071.c create mode 100644 isim/Test_ContdownController_isim_beh.exe.sim/work/m_09461933616065074075_2531671071.didat create mode 100644 isim/Test_ContdownController_isim_beh.exe.sim/work/m_09461933616065074075_2531671071.lin64.o create mode 100644 isim/Test_ContdownController_isim_beh.exe.sim/work/m_09637473393135046702_3413554552.c create mode 100644 isim/Test_ContdownController_isim_beh.exe.sim/work/m_09637473393135046702_3413554552.didat create mode 100644 isim/Test_ContdownController_isim_beh.exe.sim/work/m_09637473393135046702_3413554552.lin64.o create mode 100644 isim/Test_ContdownController_isim_beh.exe.sim/work/m_14079594305330756291_2618506667.c create mode 100644 isim/Test_ContdownController_isim_beh.exe.sim/work/m_14079594305330756291_2618506667.didat create mode 100644 isim/Test_ContdownController_isim_beh.exe.sim/work/m_14079594305330756291_2618506667.lin64.o create mode 100644 isim/Test_ContdownController_isim_beh.exe.sim/work/m_14181161885881575918_3845763652.c create mode 100644 isim/Test_ContdownController_isim_beh.exe.sim/work/m_14181161885881575918_3845763652.didat create mode 100644 isim/Test_ContdownController_isim_beh.exe.sim/work/m_14181161885881575918_3845763652.lin64.o create mode 100644 isim/Test_ContdownController_isim_beh.exe.sim/work/m_14878824473863214981_2647877144.c create mode 100644 isim/Test_ContdownController_isim_beh.exe.sim/work/m_14878824473863214981_2647877144.didat create mode 100644 isim/Test_ContdownController_isim_beh.exe.sim/work/m_14878824473863214981_2647877144.lin64.o create mode 100644 isim/Test_ContdownController_isim_beh.exe.sim/work/m_16541823861846354283_2073120511.c create mode 100644 isim/Test_ContdownController_isim_beh.exe.sim/work/m_16541823861846354283_2073120511.didat create mode 100644 isim/Test_ContdownController_isim_beh.exe.sim/work/m_16541823861846354283_2073120511.lin64.o create mode 100644 isim/Test_ContdownController_isim_beh.exe.sim/work/m_17579661360444318263_0092613024.c create mode 100644 isim/Test_ContdownController_isim_beh.exe.sim/work/m_17579661360444318263_0092613024.didat create mode 100644 isim/Test_ContdownController_isim_beh.exe.sim/work/m_17579661360444318263_0092613024.lin64.o create mode 100644 isim/isim_usage_statistics.html create mode 100644 isim/lockfile create mode 100644 isim/pn_info create mode 100644 isim/work/@b@c@d2@bin.sdb create mode 100644 isim/work/@bin2@b@c@d.sdb create mode 100644 isim/work/@clock@divider.sdb create mode 100644 isim/work/@countdown.sdb create mode 100644 isim/work/@countdown@controller.sdb create mode 100644 isim/work/@display@controller.sdb create mode 100644 isim/work/@increment.sdb create mode 100644 isim/work/@sev@seg@disp.sdb create mode 100644 isim/work/@test_@contdown@controller.sdb create mode 100644 isim/work/debouncer.sdb create mode 100644 isim/work/glbl.sdb create mode 100644 lab4.gise create mode 100644 lab4.xise create mode 100644 xilinxsim.ini diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..57cdc36 --- /dev/null +++ b/.gitignore @@ -0,0 +1,4 @@ + +*.wdb +*.exe +*.un~ diff --git a/BCD2Bin.v b/BCD2Bin.v new file mode 100644 index 0000000..06a38c8 --- /dev/null +++ b/BCD2Bin.v @@ -0,0 +1,58 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 14:39:02 03/16/2012 +// Design Name: +// Module Name: BCD2Bin +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module BCD2Bin( + input [3:0] hun, + input [3:0] ten, + input [3:0] one, + output [7:0] bin + ); + +reg [7:0] bin = 0; +reg [2:0] i = 0; + +reg [19:0] work; + +always @ ( hun, ten, one ) begin + + work = {hun, ten, one, bin}; + + //work = work >> 1; + + for (i = 0; i < 7; i = i + 1) begin + work = work >> 1; + if (work[19:16] >= 5) begin + work[19:16] = work[19:16] - 3; + end + if (work[15:12] >= 5) begin + work[15:12] = work[15:12] - 3; + end + if (work[11:8] >= 5) begin + work [11:8] = work[11:8] - 3; + end + end + + work = work >> 1; + + bin = work[7:0]; + +end + +endmodule diff --git a/Bin2BCD.v b/Bin2BCD.v new file mode 100644 index 0000000..ce79f2b --- /dev/null +++ b/Bin2BCD.v @@ -0,0 +1,56 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 10:16:12 03/16/2012 +// Design Name: +// Module Name: Bin2BCD +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module Bin2BCD( + input [7:0] bin, + output [3:0] one, + output [3:0] ten, + output [3:0] hun + ); + +reg [3:0] one, ten, hun; +reg [19:0] work; +reg [3:0] i; + +always @( bin ) begin + hun = 0; ten = 0; one = 0; + work = {hun, ten, one, bin}; + + for (i = 0; i < 7; i = i +1) begin + work = work << 1; + if (work[19:16] >= 5) begin + work[19:16] = work[19:16] + 3; + end + if (work[15:12] >= 5) begin + work[15:12] = work[15:12] + 3; + end + if (work[11:8] >= 5) begin + work[11:8] = work[11:8] + 3; + end + end + + work = work << 1; + + hun = work[19:16]; + ten = work[15:12]; + one = work[11:8]; +end + +endmodule diff --git a/Bin2BCD_beh.prj b/Bin2BCD_beh.prj new file mode 100644 index 0000000..837a173 --- /dev/null +++ b/Bin2BCD_beh.prj @@ -0,0 +1,2 @@ +verilog work "Bin2BCD.v" +verilog work "/home/michael/opt/Xilinx/13.4/ISE_DS/ISE//verilog/src/glbl.v" diff --git a/Bin2BCD_summary.html b/Bin2BCD_summary.html new file mode 100644 index 0000000..f11693f --- /dev/null +++ b/Bin2BCD_summary.html @@ -0,0 +1,79 @@ +Xilinx Design Summary + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Bin2BCD Project Status
Project File:lab4.xiseParser Errors: No Errors
Module Name:Bin2BCDImplementation State:New
Target Device:xc6slx16-3csg324
  • Errors:
 
Product Version:ISE 13.4
  • Warnings:
 
Design Goal:Balanced
  • Routing Results:
 + 
Design Strategy:Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment: 
  • Final Timing Score:
  
+ + + + + + + + + + + + 
+ + + + + + + + + + +
Detailed Reports [-]
Report NameStatusGeneratedErrorsWarningsInfos
Synthesis Report     
Translation Report     
Map Report     
Place and Route Report     
Power Report     
Post-PAR Static Timing Report     
Bitgen Report     
+ 
+ + +
Secondary Reports [-]
Report NameStatusGenerated
+ + +
Date Generated: 03/16/2012 - 11:06:11
+ \ No newline at end of file diff --git a/ClockDivider.v b/ClockDivider.v new file mode 100644 index 0000000..2447e7e --- /dev/null +++ b/ClockDivider.v @@ -0,0 +1,47 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 15:24:11 03/16/2012 +// Design Name: +// Module Name: ClockDivider +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module ClockDivider( + input clk_in, + input rst, + input [23:0] count, + output clk_out + ); + +reg clk_out = 0; +reg [23:0] c = 0; + +always @(posedge clk_in or posedge rst) begin + if (rst == 1) begin + c = 0; + clk_out = 0; + end else if (c == count) begin + clk_out = ~clk_out; + c = 0; + end else begin + c = c + 1; + end + + +end + + + +endmodule diff --git a/Countdown.v b/Countdown.v new file mode 100644 index 0000000..78e4162 --- /dev/null +++ b/Countdown.v @@ -0,0 +1,57 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 14:51:02 03/16/2012 +// Design Name: +// Module Name: Countdown +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module Countdown( + input clk_1hz, + input rst, + input start, + input [7:0] init, + output [7:0] t + ); + +reg [7:0] t; +reg running = 0; + +always @(init) begin + if (!running) begin + t = init; + end else begin + t = t; + end +end + +always @(posedge clk_1hz) begin + if (running) begin + t <= t - 1; + end else begin + t <= init; + end +end + +always @(posedge start) begin + running = 1; +end + +always @(rst) begin + running = 0; + t = 0; +end + +endmodule diff --git a/CountdownController.v b/CountdownController.v new file mode 100644 index 0000000..b06fa4b --- /dev/null +++ b/CountdownController.v @@ -0,0 +1,79 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 16:21:11 03/16/2012 +// Design Name: +// Module Name: CountdownController +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module CountdownController( + input btnA, + input btnB, + input btnC, + input clk, + input rst, + output [6:0] ssd, + output [3:0] AN + ); + +reg [6:0] ssd; +reg [3:0] AN; + +wire [6:0] ssdo; +wire [3:0] ANo; + +// clocks +wire seconds; +wire dbclk; +wire dispclk; + +// buttons +wire a, b; + +// bcd things +wire [3:0] ad, bd; +wire [3:0] ado, bdo, cdo; + +// time +wire [7:0] init; +wire [7:0] tout; + +ClockDivider dbc(.count(100), .rst(rst), .clk_in(clk), .clk_out(dbclk)); +ClockDivider sec(.count(100), .rst(rst), .clk_in(clk), .clk_out(seconds)); +ClockDivider dcc(.count(50), .rst(rst), .clk_in(clk), .clk_out(dispclk)); + +debouncer dbA(.dout(a), .din(btnA), .rst(rst), .clk_1M(dbclk)); +debouncer dbB(.dout(b), .din(btnB), .rst(rst), .clk_1M(dbclk)); + +//Increment inc1(.value(ad), .btn(a)); +//Increment inc2(.value(bd), .btn(b)); + +Increment inc1(.value(ad), .btn(btnA)); +Increment inc2(.value(bd), .btn(btnB)); + +BCD2Bin bcd2b(.hun(0), .ten(ad), .one(bd), .bin(init)); + +Countdown cntdwn(.t(tout), .rst(rst), .init(init), .clk_1hz(seconds), .start(btnC)); + +Bin2BCD b2bcb(.hun(cdo), .ten(ado), .one(bdo), .bin(tout)); + +DisplayController dispcont(.result(ssdo), .AN(ANo), .A(ado), .B(bdo), .clk_in(dispclk), .rst(rst)); + + +always @(posedge clk) begin + ssd <= ssdo; + AN <= ANo; +end +endmodule diff --git a/CountdownController_summary.html b/CountdownController_summary.html new file mode 100644 index 0000000..8dcf2d2 --- /dev/null +++ b/CountdownController_summary.html @@ -0,0 +1,80 @@ +Xilinx Design Summary + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
CountdownController Project Status
Project File:lab4.xiseParser Errors: No Errors
Module Name:CountdownControllerImplementation State:New
Target Device:xc6slx16-3csg324
  • Errors:
 
Product Version:ISE 13.4
  • Warnings:
 
Design Goal:Balanced
  • Routing Results:
 + 
Design Strategy:Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment: 
  • Final Timing Score:
  
+ + + + + + + + + + + + 
+ + + + + + + + + + +
Detailed Reports [-]
Report NameStatusGeneratedErrorsWarningsInfos
Synthesis Report     
Translation Report     
Map Report     
Place and Route Report     
Power Report     
Post-PAR Static Timing Report     
Bitgen Report     
+ 
+ + + +
Secondary Reports [-]
Report NameStatusGenerated
ISIM Simulator LogCurrentTue Mar 20 18:13:57 2012
+ + +
Date Generated: 03/21/2012 - 11:25:15
+ \ No newline at end of file diff --git a/DisplayController.v b/DisplayController.v new file mode 100644 index 0000000..1ea2bf1 --- /dev/null +++ b/DisplayController.v @@ -0,0 +1,48 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 16:03:47 03/16/2012 +// Design Name: +// Module Name: DisplayController +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module DisplayController( + input [3:0] A, + input [3:0] B, + input clk_in, + input rst, + output [6:0] result, + output [3:0] AN + ); + +reg [3:0] AN; +reg [6:0] result = 0; + +wire [6:0] ssd1; +wire [6:0] ssd2; + +reg prev = 0; + +SevSegDisp d1(.A(A), .out(ssd1)); +SevSegDisp d2(.A(B), .out(ssd2)); + +always @( posedge clk_in ) begin + prev <= ~prev; + result <= prev ? ssd1 : ssd2; + AN <= { 2'b11, prev, ~prev }; +end + + +endmodule diff --git a/DisplayController_summary.html b/DisplayController_summary.html new file mode 100644 index 0000000..2b4b547 --- /dev/null +++ b/DisplayController_summary.html @@ -0,0 +1,80 @@ +Xilinx Design Summary + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
DisplayController Project Status
Project File:lab4.xiseParser Errors: No Errors
Module Name:DisplayControllerImplementation State:New
Target Device:xc6slx16-3csg324
  • Errors:
 
Product Version:ISE 13.4
  • Warnings:
 
Design Goal:Balanced
  • Routing Results:
 + 
Design Strategy:Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment: 
  • Final Timing Score:
  
+ + + + + + + + + + + + 
+ + + + + + + + + + +
Detailed Reports [-]
Report NameStatusGeneratedErrorsWarningsInfos
Synthesis Report     
Translation Report     
Map Report     
Place and Route Report     
Power Report     
Post-PAR Static Timing Report     
Bitgen Report     
+ 
+ + + +
Secondary Reports [-]
Report NameStatusGenerated
ISIM Simulator LogCurrentFri Mar 16 16:17:01 2012
+ + +
Date Generated: 03/16/2012 - 17:11:20
+ \ No newline at end of file diff --git a/Increment.v b/Increment.v new file mode 100644 index 0000000..b386d13 --- /dev/null +++ b/Increment.v @@ -0,0 +1,32 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 14:21:53 03/16/2012 +// Design Name: +// Module Name: Increment +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// +module Increment( + input btn, + output [3:0] value + ); + +reg [3:0] value = 0; + +always @ ( posedge btn ) begin + value = value == 9 ? 0 : value + 1; +end + +endmodule diff --git a/SevSegDisp.v b/SevSegDisp.v new file mode 100644 index 0000000..f0b6ee9 --- /dev/null +++ b/SevSegDisp.v @@ -0,0 +1,45 @@ +`timescale 1ns / 1ps +////////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 16:01:14 03/16/2012 +// Design Name: +// Module Name: SevSegDisp +// Project Name: +// Target Devices: +// Tool versions: +// Description: +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +////////////////////////////////////////////////////////////////////////////////// + +module SevSegDisp( + input [3:0] A, + output [6:0] out + ); + +reg [6:0] out = 0; + +always @ ( * ) begin + case ( A ) + 4'b0000 : out = 7'b0000001; + 4'b0001 : out = 7'b1001111; + 4'b0010 : out = 7'b0010010; + 4'b0011 : out = 7'b0000110; + 4'b0100 : out = 7'b1001100; + 4'b0101 : out = 7'b0100100; + 4'b0110 : out = 7'b0100000; + 4'b0111 : out = 7'b0001111; + 4'b1000 : out = 7'b0000000; + 4'b1001 : out = 7'b0001100; + default : out = 7'b0011010; + endcase +end + +endmodule diff --git a/SevSegDisp_stx_beh.prj b/SevSegDisp_stx_beh.prj new file mode 100644 index 0000000..6dbd776 --- /dev/null +++ b/SevSegDisp_stx_beh.prj @@ -0,0 +1,2 @@ +verilog isim_temp "SevSegDisp.v" +verilog isim_temp "/home/michael/opt/Xilinx/13.4/ISE_DS/ISE//verilog/src/glbl.v" diff --git a/TEST_BCD2Bin.v b/TEST_BCD2Bin.v new file mode 100644 index 0000000..56edd04 --- /dev/null +++ b/TEST_BCD2Bin.v @@ -0,0 +1,61 @@ +`timescale 1ns / 1ps + +//////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 14:42:39 03/16/2012 +// Design Name: BCD2Bin +// Module Name: /home/michael/Documents/School/EC311/lab4/TEST_BCD2Bin.v +// Project Name: lab4 +// Target Device: +// Tool versions: +// Description: +// +// Verilog Test Fixture created by ISE for module: BCD2Bin +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +//////////////////////////////////////////////////////////////////////////////// + +module TEST_BCD2Bin; + + // Inputs + reg [3:0] hun; + reg [3:0] ten; + reg [3:0] one; + wire [7:0] bin; + + // Instantiate the Unit Under Test (UUT) + BCD2Bin uut ( + .hun(hun), + .ten(ten), + .one(one), + .bin(bin) + ); + + initial begin + // Initialize Inputs + hun = 0; + ten = 0; + one = 0; + + // Wait 100 ns for global reset to finish + #100; + + one = 5; ten = 2; hun = 1; #10; + one = 4; ten = 7; hun = 1; #10; + one = 8; ten = 2; hun = 0; #10; + one = 3; ten = 1; hun = 0; #10; + one = 2; ten = 0; hun = 0; #10; + + // Add stimulus here + + end + +endmodule + diff --git a/TEST_Bin2BCD.v b/TEST_Bin2BCD.v new file mode 100644 index 0000000..e13ee07 --- /dev/null +++ b/TEST_Bin2BCD.v @@ -0,0 +1,61 @@ +`timescale 1ns / 1ps + +//////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 10:35:33 03/16/2012 +// Design Name: Bin2BCD +// Module Name: /home/michael/Documents/School/EC311/lab4/TEST_Bin2BCD.v +// Project Name: lab4 +// Target Device: +// Tool versions: +// Description: +// +// Verilog Test Fixture created by ISE for module: Bin2BCD +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +//////////////////////////////////////////////////////////////////////////////// + +module TEST_Bin2BCD; + + // Inputs + reg [7:0] bin; + + // Outputs + wire [3:0] one; + wire [3:0] ten; + wire [3:0] hun; + + // Instantiate the Unit Under Test (UUT) + Bin2BCD uut ( + .bin(bin), + .one(one), + .ten(ten), + .hun(hun) + ); + + initial begin + // Initialize Inputs + bin = 0; + #10 bin = 3; + #10 bin = 9; + #10 bin = 15; + #10 bin = 124; + #10 bin = 174; + #10 bin = 234; + + // Wait 100 ns for global reset to finish + #100; + + // Add stimulus here + + end + +endmodule + diff --git a/TEST_Bin2BCD_stx_beh.prj b/TEST_Bin2BCD_stx_beh.prj new file mode 100644 index 0000000..e2ff8e3 --- /dev/null +++ b/TEST_Bin2BCD_stx_beh.prj @@ -0,0 +1,3 @@ +verilog isim_temp "Bin2BCD.v" +verilog isim_temp "TEST_Bin2BCD.v" +verilog isim_temp "/home/michael/opt/Xilinx/13.4/ISE_DS/ISE//verilog/src/glbl.v" diff --git a/TEST_ClockDivider.v b/TEST_ClockDivider.v new file mode 100644 index 0000000..e7f6cfe --- /dev/null +++ b/TEST_ClockDivider.v @@ -0,0 +1,65 @@ +`timescale 1ns / 1ps + +//////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 15:29:06 03/16/2012 +// Design Name: ClockDivider +// Module Name: /home/michael/Documents/School/EC311/lab4/TEST_ClockDivider.v +// Project Name: lab4 +// Target Device: +// Tool versions: +// Description: +// +// Verilog Test Fixture created by ISE for module: ClockDivider +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +//////////////////////////////////////////////////////////////////////////////// + +module TEST_ClockDivider; + + // Inputs + reg clk_in; + reg rst; + reg [23:0] count; + + // Outputs + wire clk_out; + + // Instantiate the Unit Under Test (UUT) + ClockDivider uut ( + .clk_in(clk_in), + .rst(rst), + .count(count), + .clk_out(clk_out) + ); + + reg [15:0] i = 0; + + initial begin + // Initialize Inputs + clk_in = 0; + rst = 0; + count = 0; + + // Wait 100 ns for global reset to finish + #50; + + // Add stimulus here + + count = 15; + + for (i = 0; i < 200; i = i + 1) begin + #5; clk_in = ~clk_in; + end + + end + +endmodule + diff --git a/TEST_Countdown.v b/TEST_Countdown.v new file mode 100644 index 0000000..5f47c07 --- /dev/null +++ b/TEST_Countdown.v @@ -0,0 +1,70 @@ +`timescale 1ns / 1ps + +//////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 14:57:17 03/16/2012 +// Design Name: Countdown +// Module Name: /home/michael/Documents/School/EC311/lab4/TEST_Countdown.v +// Project Name: lab4 +// Target Device: +// Tool versions: +// Description: +// +// Verilog Test Fixture created by ISE for module: Countdown +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +//////////////////////////////////////////////////////////////////////////////// + +module TEST_Countdown; + + // Inputs + reg clk_1hz; + reg rst; + reg start; + reg [7:0] init; + + // Outputs + wire [7:0] t; + + reg [7:0] i=0; + // Instantiate the Unit Under Test (UUT) + Countdown uut ( + .clk_1hz(clk_1hz), + .rst(rst), + .start(start), + .init(init), + .t(t) + ); + + initial begin + // Initialize Inputs + clk_1hz = 0; + rst = 0; + start = 0; + init = 0; + + // Wait 50 ns for global reset to finish + #50; + + // Add stimulus here + + init = 218; #50; + + for (i = 0; i < 255; i = i + 1) begin + #5; clk_1hz = ~clk_1hz; + if (i == 10) begin + start = 1; #5; clk_1hz = ~clk_1hz; start = 0; + end + end + + end + +endmodule + diff --git a/TEST_DisplayController.v b/TEST_DisplayController.v new file mode 100644 index 0000000..74ce40a --- /dev/null +++ b/TEST_DisplayController.v @@ -0,0 +1,71 @@ +`timescale 1ns / 1ps + +//////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 17:39:11 03/16/2012 +// Design Name: DisplayController +// Module Name: /home/michael/Documents/School/EC311/lab4/TEST_DisplayController.v +// Project Name: lab4 +// Target Device: +// Tool versions: +// Description: +// +// Verilog Test Fixture created by ISE for module: DisplayController +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +//////////////////////////////////////////////////////////////////////////////// + +module TEST_DisplayController; + + // Inputs + reg [3:0] A; + reg [3:0] B; + reg clk_in; + reg rst; + + // Outputs + wire [6:0] result; + wire [3:0] AN; + + // Instantiate the Unit Under Test (UUT) + DisplayController uut ( + .A(A), + .B(B), + .clk_in(clk_in), + .rst(rst), + .result(result), + .AN(AN) + ); + + initial begin + // Initialize Inputs + A = 0; + B = 0; + clk_in = 0; + rst = 0; + + // Wait 100 ns for global reset to finish + #100; + + // Add stimulus here + + A = 4'd7; + B = 4'd9; + + #10; + + while (1) begin + clk_in = ~clk_in; #10; + end + + end + +endmodule + diff --git a/TEST_DisplayController_stx_beh.prj b/TEST_DisplayController_stx_beh.prj new file mode 100644 index 0000000..70a1bcc --- /dev/null +++ b/TEST_DisplayController_stx_beh.prj @@ -0,0 +1,5 @@ +verilog isim_temp "SevSegDisp.v" +verilog isim_temp "ClockDivider.v" +verilog isim_temp "DisplayController.v" +verilog isim_temp "TEST_DisplayController.v" +verilog isim_temp "/home/michael/opt/Xilinx/13.4/ISE_DS/ISE//verilog/src/glbl.v" diff --git a/TEST_Increment.v b/TEST_Increment.v new file mode 100644 index 0000000..2ff393a --- /dev/null +++ b/TEST_Increment.v @@ -0,0 +1,61 @@ +`timescale 1ns / 1ps + +//////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 14:24:49 03/16/2012 +// Design Name: Increment +// Module Name: /home/michael/Documents/School/EC311/lab4/TEST_Increment.v +// Project Name: lab4 +// Target Device: +// Tool versions: +// Description: +// +// Verilog Test Fixture created by ISE for module: Increment +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +//////////////////////////////////////////////////////////////////////////////// + +module TEST_Increment; + + // Inputs + reg btn; + + // Outputs + wire [3 :0] value; + + // count + reg [4:0] i; + + + // Instantiate the Unit Under Test (UUT) + Increment uut ( + .btn(btn), + .value(value) + ); + + initial begin + // Initialize Inputs + btn = 0; + + // Wait 100 ns for global reset to finish + #100; + + for (i = 0; i < 20; i = i + 1) begin + btn = 1; #10; + btn = 0; #10; + end + + #100; + // Add stimulus here + + end + +endmodule + diff --git a/TEST_SevSegDisp.v b/TEST_SevSegDisp.v new file mode 100644 index 0000000..a818547 --- /dev/null +++ b/TEST_SevSegDisp.v @@ -0,0 +1,55 @@ +`timescale 1ns / 1ps + +//////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 17:48:24 03/16/2012 +// Design Name: SevSegDisp +// Module Name: /home/michael/Documents/School/EC311/lab4/TEST_SevSegDisp.v +// Project Name: lab4 +// Target Device: +// Tool versions: +// Description: +// +// Verilog Test Fixture created by ISE for module: SevSegDisp +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +//////////////////////////////////////////////////////////////////////////////// + +module TEST_SevSegDisp; + + // Inputs + reg [3:0] A; + + // Outputs + wire [6:0] out; + + // Instantiate the Unit Under Test (UUT) + SevSegDisp uut ( + .A(A), + .out(out) + ); + reg [3:0] i = 0; + initial begin + // Initialize Inputs + A = 0; + + // Wait 100 ns for global reset to finish + #100; + + // Add stimulus here + + for (i = 0; i < 10; i = i + 1) begin + A = A + 1; #50; + end + + end + +endmodule + diff --git a/Test_ContdownController.v b/Test_ContdownController.v new file mode 100644 index 0000000..ba3b63c --- /dev/null +++ b/Test_ContdownController.v @@ -0,0 +1,94 @@ +`timescale 1ns / 1ps + +//////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 17:21:16 03/16/2012 +// Design Name: CountdownController +// Module Name: /home/michael/Documents/School/EC311/lab4/Test_ContdownController.v +// Project Name: lab4 +// Target Device: +// Tool versions: +// Description: +// +// Verilog Test Fixture created by ISE for module: CountdownController +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +//////////////////////////////////////////////////////////////////////////////// + +module Test_ContdownController; + + // Inputs + reg btnA; + reg btnB; + reg btnC; + reg clk; + reg rst; + + // Outputs + wire [6:0] ssd; + wire [3:0] AN; + + // Instantiate the Unit Under Test (UUT) + CountdownController uut ( + .btnA(btnA), + .btnB(btnB), + .btnC(btnC), + .clk(clk), + .rst(rst), + .ssd(ssd), + .AN(AN) + ); + + reg [31:0] i = 0; + reg [3:0] j = 0; + initial begin + // Initialize Inputs + btnA = 0; + btnB = 0; + btnC = 0; + clk = 0; + rst = 0; + + // Wait 100 ns for global reset to finish + #100; + + // Add stimulus here + + + + + while (11) begin + clk = ~clk; #1; + if (i < 100) begin + i = i + 1; + if (i == 50) begin + for (j = 0; j < 5; j = j + 1) begin + btnA = 1; #1 + clk = ~clk; + btnA = 0; #1; + clk = ~clk; + end + for (j = 0; j < 2; j = j + 1) begin + btnB = 1; #1; + clk = ~clk; + btnB = 0; #1; + clk = ~clk; + end + end + if (i == 90) begin + btnC = 1; #1; clk = ~clk; btnC = 0; + end + end + end + + end + +endmodule + diff --git a/Test_ContdownController_beh.prj b/Test_ContdownController_beh.prj new file mode 100644 index 0000000..9f8f6b9 --- /dev/null +++ b/Test_ContdownController_beh.prj @@ -0,0 +1,11 @@ +verilog work "SevSegDisp.v" +verilog work "Increment.v" +verilog work "DisplayController.v" +verilog work "debouncer.v" +verilog work "Countdown.v" +verilog work "ClockDivider.v" +verilog work "Bin2BCD.v" +verilog work "BCD2Bin.v" +verilog work "CountdownController.v" +verilog work "Test_ContdownController.v" +verilog work "/home/michael/opt/Xilinx/13.4/ISE_DS/ISE//verilog/src/glbl.v" diff --git a/_xmsgs/pn_parser.xmsgs b/_xmsgs/pn_parser.xmsgs new file mode 100644 index 0000000..009b8f5 --- /dev/null +++ b/_xmsgs/pn_parser.xmsgs @@ -0,0 +1,15 @@ + + + + + + + + + + +Analyzing Verilog file "/home/michael/Documents/School/EC311/lab4/Countdown.v" into library work + + + + diff --git a/clockdiv.wcfg b/clockdiv.wcfg new file mode 100644 index 0000000..ca45f5a --- /dev/null +++ b/clockdiv.wcfg @@ -0,0 +1,36 @@ + + + + + + + + + + + + + + + clk_out + clk_out + + + clk_in + clk_in + + + rst + rst + + + count[23:0] + count[23:0] + UNSIGNEDDECRADIX + + + i[15:0] + i[15:0] + UNSIGNEDDECRADIX + + diff --git a/countdown.wcfg b/countdown.wcfg new file mode 100644 index 0000000..9935ede --- /dev/null +++ b/countdown.wcfg @@ -0,0 +1,40 @@ + + + + + + + + + + + + + + + t[7:0] + t[7:0] + UNSIGNEDDECRADIX + + + clk_1hz + clk_1hz + + + rst + rst + + + start + start + + + init[7:0] + init[7:0] + + + i[7:0] + i[7:0] + UNSIGNEDDECRADIX + + diff --git a/debouncer.v b/debouncer.v new file mode 100644 index 0000000..d37cf6d --- /dev/null +++ b/debouncer.v @@ -0,0 +1,56 @@ +module debouncer(clk_1M, rst, din, dout); + input clk_1M; + input rst; + input din; + output dout; + + reg dout; + reg [21:0] count; + + reg sync0; // first stage of synchronizer + reg sync1; // second stage of synchronizer + + reg prev; // register for edge detection + + // synchronize input. (Synchronizers will be discussed in a future lab.) + always @(posedge clk_1M or posedge rst) begin + if (rst == 1) begin + sync0 <= 0; + sync1 <= 0; + end + else begin + sync0 <= din; + sync1 <= sync0; + end + end // always + + // perform an edge detect on the synchronized input. + always @(posedge clk_1M or posedge rst) begin + if (rst == 1) begin + prev <= 0; + end + else begin + prev <= sync1; + end + end // always + + // state machine/counter for timing the debouncing. + always @(posedge clk_1M or posedge rst) begin + if (rst == 1) begin + count <= 0; + end + else begin + if (count == 0) begin + if (sync1 == 1 && prev == 0) begin // rising edge detect + count <= 22'd100000; // 100,000 us = 100ms delay + end + dout <= 0; + end + else begin + count <= count - 22'd1; + dout <= 1; + end + end + end // always + +endmodule diff --git a/fuse.log b/fuse.log new file mode 100644 index 0000000..d9cd2af --- /dev/null +++ b/fuse.log @@ -0,0 +1,52 @@ +Running: /home/michael/opt/Xilinx/13.4/ISE_DS/ISE/bin/lin64/unwrapped/fuse -intstyle ise -incremental -lib unisims_ver -lib unimacro_ver -lib xilinxcorelib_ver -lib secureip -o /home/michael/Documents/School/EC311/lab4/Test_ContdownController_isim_beh.exe -prj /home/michael/Documents/School/EC311/lab4/Test_ContdownController_beh.prj work.Test_ContdownController work.glbl +ISim O.87xd (signature 0x8ddf5b5d) +Number of CPUs detected in this system: 2 +Turning on mult-threading, number of parallel sub-compilation jobs: 4 +Determining compilation order of HDL files +Analyzing Verilog file "/home/michael/Documents/School/EC311/lab4/SevSegDisp.v" into library work +WARNING:HDLCompiler:751 - "/home/michael/Documents/School/EC311/lab4/SevSegDisp.v" Line 27: Redeclaration of ansi port out is not allowed +Analyzing Verilog file "/home/michael/Documents/School/EC311/lab4/Increment.v" into library work +WARNING:HDLCompiler:751 - "/home/michael/Documents/School/EC311/lab4/Increment.v" Line 26: Redeclaration of ansi port value is not allowed +Analyzing Verilog file "/home/michael/Documents/School/EC311/lab4/DisplayController.v" into library work +WARNING:HDLCompiler:751 - "/home/michael/Documents/School/EC311/lab4/DisplayController.v" Line 30: Redeclaration of ansi port AN is not allowed +WARNING:HDLCompiler:751 - "/home/michael/Documents/School/EC311/lab4/DisplayController.v" Line 31: Redeclaration of ansi port result is not allowed +Analyzing Verilog file "/home/michael/Documents/School/EC311/lab4/debouncer.v" into library work +Analyzing Verilog file "/home/michael/Documents/School/EC311/lab4/Countdown.v" into library work +WARNING:HDLCompiler:751 - "/home/michael/Documents/School/EC311/lab4/Countdown.v" Line 29: Redeclaration of ansi port t is not allowed +Analyzing Verilog file "/home/michael/Documents/School/EC311/lab4/ClockDivider.v" into library work +WARNING:HDLCompiler:751 - "/home/michael/Documents/School/EC311/lab4/ClockDivider.v" Line 28: Redeclaration of ansi port clk_out is not allowed +Analyzing Verilog file "/home/michael/Documents/School/EC311/lab4/Bin2BCD.v" into library work +WARNING:HDLCompiler:751 - "/home/michael/Documents/School/EC311/lab4/Bin2BCD.v" Line 28: Redeclaration of ansi port one is not allowed +Analyzing Verilog file "/home/michael/Documents/School/EC311/lab4/BCD2Bin.v" into library work +WARNING:HDLCompiler:751 - "/home/michael/Documents/School/EC311/lab4/BCD2Bin.v" Line 28: Redeclaration of ansi port bin is not allowed +Analyzing Verilog file "/home/michael/Documents/School/EC311/lab4/CountdownController.v" into library work +WARNING:HDLCompiler:751 - "/home/michael/Documents/School/EC311/lab4/CountdownController.v" Line 31: Redeclaration of ansi port ssd is not allowed +WARNING:HDLCompiler:751 - "/home/michael/Documents/School/EC311/lab4/CountdownController.v" Line 32: Redeclaration of ansi port AN is not allowed +Analyzing Verilog file "/home/michael/Documents/School/EC311/lab4/Test_ContdownController.v" into library work +Analyzing Verilog file "/home/michael/opt/Xilinx/13.4/ISE_DS/ISE//verilog/src/glbl.v" into library work +Starting static elaboration +WARNING:HDLCompiler:189 - "/home/michael/Documents/School/EC311/lab4/CountdownController.v" Line 54: Size mismatch in connection of port . Formal port size is 24-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/michael/Documents/School/EC311/lab4/CountdownController.v" Line 55: Size mismatch in connection of port . Formal port size is 24-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/michael/Documents/School/EC311/lab4/CountdownController.v" Line 53: Size mismatch in connection of port . Formal port size is 24-bit while actual signal size is 32-bit. +WARNING:HDLCompiler:189 - "/home/michael/Documents/School/EC311/lab4/CountdownController.v" Line 66: Size mismatch in connection of port . Formal port size is 4-bit while actual signal size is 32-bit. +Completed static elaboration +Fuse Memory Usage: 95008 KB +Fuse CPU Usage: 1560 ms +Compiling module ClockDivider +Compiling module debouncer +Compiling module Increment +Compiling module BCD2Bin +Compiling module Countdown +Compiling module Bin2BCD +Compiling module SevSegDisp +Compiling module DisplayController +Compiling module CountdownController +Compiling module Test_ContdownController +Compiling module glbl +Time Resolution for simulation is 1ps. +Waiting for 8 sub-compilation(s) to finish... +Compiled 11 Verilog Units +Built simulation executable /home/michael/Documents/School/EC311/lab4/Test_ContdownController_isim_beh.exe +Fuse Memory Usage: 393132 KB +Fuse CPU Usage: 1610 ms +GCC CPU Usage: 1250 ms diff --git a/fuse.xmsgs b/fuse.xmsgs new file mode 100644 index 0000000..39e40a2 --- /dev/null +++ b/fuse.xmsgs @@ -0,0 +1,51 @@ + + + +"/home/michael/Documents/School/EC311/lab4/SevSegDisp.v" Line 27: Redeclaration of ansi port out is not allowed + + +"/home/michael/Documents/School/EC311/lab4/Increment.v" Line 26: Redeclaration of ansi port value is not allowed + + +"/home/michael/Documents/School/EC311/lab4/DisplayController.v" Line 30: Redeclaration of ansi port AN is not allowed + + +"/home/michael/Documents/School/EC311/lab4/DisplayController.v" Line 31: Redeclaration of ansi port result is not allowed + + +"/home/michael/Documents/School/EC311/lab4/Countdown.v" Line 29: Redeclaration of ansi port t is not allowed + + +"/home/michael/Documents/School/EC311/lab4/ClockDivider.v" Line 28: Redeclaration of ansi port clk_out is not allowed + + +"/home/michael/Documents/School/EC311/lab4/Bin2BCD.v" Line 28: Redeclaration of ansi port one is not allowed + + +"/home/michael/Documents/School/EC311/lab4/BCD2Bin.v" Line 28: Redeclaration of ansi port bin is not allowed + + +"/home/michael/Documents/School/EC311/lab4/CountdownController.v" Line 31: Redeclaration of ansi port ssd is not allowed + + +"/home/michael/Documents/School/EC311/lab4/CountdownController.v" Line 32: Redeclaration of ansi port AN is not allowed + + +"/home/michael/Documents/School/EC311/lab4/CountdownController.v" Line 54: Size mismatch in connection of port <count>. Formal port size is 24-bit while actual signal size is 32-bit. + + +"/home/michael/Documents/School/EC311/lab4/CountdownController.v" Line 55: Size mismatch in connection of port <count>. Formal port size is 24-bit while actual signal size is 32-bit. + + +