From 2ac48fa0e44016a6cb49cab84a154eb7ec2dcab4 Mon Sep 17 00:00:00 2001 From: Michael Abed Date: Wed, 21 Mar 2012 13:17:47 -0400 Subject: Initial Commit --- TEST_Bin2BCD.v | 61 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 61 insertions(+) create mode 100644 TEST_Bin2BCD.v (limited to 'TEST_Bin2BCD.v') diff --git a/TEST_Bin2BCD.v b/TEST_Bin2BCD.v new file mode 100644 index 0000000..e13ee07 --- /dev/null +++ b/TEST_Bin2BCD.v @@ -0,0 +1,61 @@ +`timescale 1ns / 1ps + +//////////////////////////////////////////////////////////////////////////////// +// Company: +// Engineer: +// +// Create Date: 10:35:33 03/16/2012 +// Design Name: Bin2BCD +// Module Name: /home/michael/Documents/School/EC311/lab4/TEST_Bin2BCD.v +// Project Name: lab4 +// Target Device: +// Tool versions: +// Description: +// +// Verilog Test Fixture created by ISE for module: Bin2BCD +// +// Dependencies: +// +// Revision: +// Revision 0.01 - File Created +// Additional Comments: +// +//////////////////////////////////////////////////////////////////////////////// + +module TEST_Bin2BCD; + + // Inputs + reg [7:0] bin; + + // Outputs + wire [3:0] one; + wire [3:0] ten; + wire [3:0] hun; + + // Instantiate the Unit Under Test (UUT) + Bin2BCD uut ( + .bin(bin), + .one(one), + .ten(ten), + .hun(hun) + ); + + initial begin + // Initialize Inputs + bin = 0; + #10 bin = 3; + #10 bin = 9; + #10 bin = 15; + #10 bin = 124; + #10 bin = 174; + #10 bin = 234; + + // Wait 100 ns for global reset to finish + #100; + + // Add stimulus here + + end + +endmodule + -- cgit v1.2.3