From 2ac48fa0e44016a6cb49cab84a154eb7ec2dcab4 Mon Sep 17 00:00:00 2001
From: Michael Abed <michaelabed@gmail.com>
Date: Wed, 21 Mar 2012 13:17:47 -0400
Subject: Initial Commit

---
 TEST_Increment.v | 61 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 61 insertions(+)
 create mode 100644 TEST_Increment.v

(limited to 'TEST_Increment.v')

diff --git a/TEST_Increment.v b/TEST_Increment.v
new file mode 100644
index 0000000..2ff393a
--- /dev/null
+++ b/TEST_Increment.v
@@ -0,0 +1,61 @@
+`timescale 1ns / 1ps
+
+////////////////////////////////////////////////////////////////////////////////
+// Company: 
+// Engineer:
+//
+// Create Date:   14:24:49 03/16/2012
+// Design Name:   Increment
+// Module Name:   /home/michael/Documents/School/EC311/lab4/TEST_Increment.v
+// Project Name:  lab4
+// Target Device:  
+// Tool versions:  
+// Description: 
+//
+// Verilog Test Fixture created by ISE for module: Increment
+//
+// Dependencies:
+// 
+// Revision:
+// Revision 0.01 - File Created
+// Additional Comments:
+// 
+////////////////////////////////////////////////////////////////////////////////
+
+module TEST_Increment;
+
+	// Inputs
+	reg btn;
+
+	// Outputs
+	wire [3	:0] value;
+	
+	// count
+	reg [4:0] i;
+	
+	
+	// Instantiate the Unit Under Test (UUT)
+	Increment uut (
+		.btn(btn), 
+		.value(value)
+	);
+
+	initial begin
+		// Initialize Inputs
+		btn = 0;
+
+		// Wait 100 ns for global reset to finish
+		#100;
+		
+		for (i = 0; i < 20; i = i + 1) begin
+		    btn = 1; #10;
+			 btn = 0; #10;
+		end
+		
+      #100;
+		// Add stimulus here
+
+	end
+      
+endmodule
+
-- 
cgit v1.2.3