`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    14:39:02 03/16/2012 
// Design Name: 
// Module Name:    BCD2Bin 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module BCD2Bin(
    input [3:0] hun,
    input [3:0] ten,
    input [3:0] one,
    output [7:0] bin
    );

reg [7:0] bin = 0;
reg [2:0] i = 0;

reg [19:0] work;

always @ ( hun, ten, one, bin ) begin

	work = {hun, ten, one, bin};
	
	//work = work >> 1;
	
	for (i = 0; i < 7; i = i + 1) begin
		work = work >> 1;
		if (work[19:16] >= 5) begin
			work[19:16] = work[19:16] - 4'd3;
		end
		if (work[15:12] >= 5) begin
			work[15:12] = work[15:12] - 4'd3;
		end
		if (work[11:8] >= 5) begin
			work [11:8] = work[11:8] - 4'd3;
		end
	end
	
	work = work >> 1;
	
	bin = work[7:0];

end

endmodule