`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    14:51:02 03/16/2012 
// Design Name: 
// Module Name:    Countdown 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module Countdown(
    input clk_1hz,
    input rst,
    input start,
    input [7:0] init,
    output [7:0] t
    );

reg [7:0] t;
reg running = 0;

always @(init) begin
	if (!running) begin
		t = init;
	end else begin
		t = t;
	end
end

always @(posedge clk_1hz) begin
	if (running) begin
		t <= t - 1;
	end else begin
		t <= init;
	end
end

always @(posedge start) begin
	running = 1;
end

always @(rst) begin
	running = 0;
	t = 0;
end

endmodule