`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    16:21:11 03/16/2012 
// Design Name: 
// Module Name:    CountdownController 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module CountdownController(
    input btnA,
    input btnB,
    input btnC,
    input clk,
    input rst,
    output [6:0] ssd,
    output [3:0] AN
    );

reg [6:0] ssd;
reg [3:0] AN;

wire [6:0] ssd1;
wire [6:0] ssd2;
wire [3:0] AN1;
wire [3:0] AN2;

// clocks
wire seconds;
wire dbclk;
wire dispclk;

wire running;

// buttons
wire a, b, c;

// bcd things
wire [3:0] ad, bd;
wire [3:0] ado, bdo, cdo;

// time
wire [7:0] init;
wire [7:0] tout;

ClockDivider dbc(.count(100), .rst(rst), .clk_in(clk), .clk_out(dbclk));
ClockDivider sec(.count(100_000_000), .rst(rst), .clk_in(clk), .clk_out(seconds));
ClockDivider dcc(.count(7_500_0), .rst(rst), .clk_in(clk), .clk_out(dispclk));

//ClockDivider dbc(.count(24'd10), .rst(rst), .clk_in(clk), .clk_out(dbclk));
//ClockDivider sec(.count(24'd100), .rst(rst), .clk_in(clk), .clk_out(seconds));
//ClockDivider dcc(.count(24'd25), .rst(rst), .clk_in(clk), .clk_out(dispclk));


debouncer dbA(.dout(a), .din(btnA), .rst(rst), .clk_1M(dbclk));
debouncer dbB(.dout(b), .din(btnB), .rst(rst), .clk_1M(dbclk));
debouncer dbC(.dout(c), .din(btnC), .rst(rst), .clk_1M(dbclk));

Increment inc1(.value(ad), .btn(a), .rst(rst));
Increment inc2(.value(bd), .btn(b), .rst(rst));

//Increment inc1(.value(ad), .btn(btnA));
//Increment inc2(.value(bd), .btn(btnB));

BCD2Bin bcd2b(.hun(4'd0), .ten(ad), .one(bd), .bin(init));

Countdown cntdwn(.t(tout), .running(running), .rst(rst), .init(init), .clk_1hz(seconds), .start(c));

Bin2BCD b2bcb(.hun(cdo), .ten(ado), .one(bdo), .bin(tout));

DisplayController dispcont1(.result(ssd1), .AN(AN1), .A(ado), .B(bdo), .clk_in(dispclk), .rst(rst));
DisplayController dispcont2(.result(ssd2), .AN(AN2), .A(ad), .B(bd), .clk_in(dispclk), .rst(rst));
always @(posedge clk) begin
	ssd <= running ? ssd1 : ssd2;
	AN <= running ? AN1 : AN2;
end

endmodule