`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   15:29:06 03/16/2012
// Design Name:   ClockDivider
// Module Name:   /home/michael/Documents/School/EC311/lab4/TEST_ClockDivider.v
// Project Name:  lab4
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: ClockDivider
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module TEST_ClockDivider;

	// Inputs
	reg clk_in;
	reg rst;
	reg [23:0] count;

	// Outputs
	wire clk_out;

	// Instantiate the Unit Under Test (UUT)
	ClockDivider uut (
		.clk_in(clk_in), 
		.rst(rst), 
		.count(count), 
		.clk_out(clk_out)
	);
	
	reg [15:0] i = 0;

	initial begin
		// Initialize Inputs
		clk_in = 0;
		rst = 0;
		count = 0;

		// Wait 100 ns for global reset to finish
		#50;
        
		// Add stimulus here
		
		count = 15;
		
		for (i = 0; i < 200; i = i + 1) begin
			#5; clk_in = ~clk_in;
		end
		
	end
      
endmodule