`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   17:39:11 03/16/2012
// Design Name:   DisplayController
// Module Name:   /home/michael/Documents/School/EC311/lab4/TEST_DisplayController.v
// Project Name:  lab4
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: DisplayController
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module TEST_DisplayController;

	// Inputs
	reg [3:0] A;
	reg [3:0] B;
	reg clk_in;
	reg rst;

	// Outputs
	wire [6:0] result;
	wire [3:0] AN;

	// Instantiate the Unit Under Test (UUT)
	DisplayController uut (
		.A(A), 
		.B(B), 
		.clk_in(clk_in), 
		.rst(rst), 
		.result(result), 
		.AN(AN)
	);
		
	initial begin
		// Initialize Inputs
		A = 0;
		B = 0;
		clk_in = 0;
		rst = 0;

		// Wait 100 ns for global reset to finish
		#100;
        
		// Add stimulus here
		
		A = 4'd7;
		B = 4'd9;
		
		#10;
		
		while (1) begin
			clk_in = ~clk_in; #10;
		end
		
	end
      
endmodule