`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   17:48:24 03/16/2012
// Design Name:   SevSegDisp
// Module Name:   /home/michael/Documents/School/EC311/lab4/TEST_SevSegDisp.v
// Project Name:  lab4
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: SevSegDisp
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module TEST_SevSegDisp;

	// Inputs
	reg [3:0] A;

	// Outputs
	wire [6:0] result;

	// Instantiate the Unit Under Test (UUT)
	SevSegDisp uut (
		.A(A), 
		.result(result)
	);
	reg [3:0] i = 0;
	initial begin
		// Initialize Inputs
		A = 0;

		// Wait 100 ns for global reset to finish
		#100;
        
		// Add stimulus here

		for (i = 0; i < 10; i = i + 1) begin
			A = A + 1; #50;
		end
		
	end
      
endmodule