`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   17:21:16 03/16/2012
// Design Name:   CountdownController
// Module Name:   /home/michael/Documents/School/EC311/lab4/Test_ContdownController.v
// Project Name:  lab4
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: CountdownController
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module Test_ContdownController;

	// Inputs
	reg btnA;
	reg btnB;
	reg btnC;
	reg clk;
	reg rst;

	// Outputs
	wire [6:0] ssd;
	wire [3:0] AN;

	// Instantiate the Unit Under Test (UUT)
	CountdownController uut (
		.btnA(btnA), 
		.btnB(btnB), 
		.btnC(btnC), 
		.clk(clk), 
		.rst(rst), 
		.ssd(ssd), 
		.AN(AN)
	);
	
	reg [31:0] i = 0;
	reg [3:0] j = 0;
	initial begin
		// Initialize Inputs
		btnA = 0;
		btnB = 0;
		btnC = 0;
		clk = 0;
		rst = 0;

		// Wait 100 ns for global reset to finish
		#100;
        
		// Add stimulus here
		
		
		
		
		while (11) begin
			clk = ~clk; #1;
			if (i < 100) begin
				i = i + 1;
				if (i == 50) begin
					for (j = 0; j < 5; j = j + 1) begin
						btnA = 1; #1
						clk = ~clk; 
						btnA = 0; #1;
						clk = ~clk;
					end
					for (j = 0; j < 2; j = j + 1)  begin
						btnB = 1; #1;
						clk = ~clk; 
						btnB = 0; #1;
						clk = ~clk;
					end
				end
				if (i == 90) begin
					btnC = 1; #1; clk = ~clk; btnC = 0;
				end
			end
		end
			
	end
      
endmodule